Shweta Shinde is an Assistant Professor at ETH Zürich's Department of Computer Science. She leads the Secure & Trustworthy Systems (SECTRS) group and is affiliated with the Institute of Information Security and the ZISC Center. Her research focuses on foundational and practical aspects of trusted computing, system security, and program analysis to protect devices ranging from smartphones to cloud servers. Key areas include AMD SEV-SNP, Arm CCA, Intel SGX, and hardware-software co-design for security. Dr. Shinde has made significant contributions to confidential computing, including frameworks like OpenCCA and tools for analyzing hardware vulnerabilities. Her work has been recognized with Best Paper Awards and Distinguished Paper Awards at top venues. She advises a group of PhD students, including Mark Kuhne, Supraja Sridhara, and Benedict Schlüter. Her service includes program committee roles at IEEE Security & Privacy, USENIX Security, and as Track Co-Chair for AsiaCCS 2026.
Anantha Chandrakasan is the Vannevar Bush Professor of Electrical Engineering and Computer Science at MIT, serving as Dean of the MIT School of Engineering and Chief Innovation and Strategy Officer. His research focuses on energy-efficient integrated circuits, medical devices, and AI hardware security. He leads the MIT Energy-Efficient Circuits and Systems Group, developing systems for biomedical applications, wireless communication, and quantum computing. He holds appointments at MIT's Microsystems Technology Laboratories and has contributed to collaborations like the MIT-Takeda Program in AI-driven healthcare and a partnership with GlobalFoundries for energy-efficient AI chips. His work spans implantable drug delivery systems, conformable ultrasound patches, and secure edge computing architectures. Chandrakasan's innovations include ultra-low-power circuits for IoT devices, cryptographic processors for post-quantum security, and AI accelerators for edge applications. He emphasizes interdisciplinary research bridging electrical engineering with biomedical and quantum fields, supported by leadership roles in MIT's strategic initiatives. His contributions to energy-efficient computing have led to advancements in wearable health monitors, batteryless sensors, and secure communication protocols for medical devices. Ongoing projects include THz integrated systems and AI-enhanced analog circuit design optimization.
Dr. Amin Sakzad is an Associate Professor in the Department of Software Systems & Cybersecurity at Monash University's Faculty of Information Technology. His research focuses on lattice-based cryptography, wireless communications, and post-quantum security protocols. He holds a PhD in Applied Mathematics from Amirkabir University of Technology (2011) and has held academic roles at Carleton University and Monash since 2012. Dr. Sakzad’s expertise spans lattice coding theory, MIMO systems, and privacy-preserving technologies for genomic databases and blockchain applications. He leads multiple ARC-funded projects, including work on secure databases (SRDBMS) and post-quantum cryptographic primitives for FinTech and energy sectors. His research has been recognized through awards such as the FIT Dean’s Award for Teaching Excellence (2021). Key collaborations include projects on blockchain security (CollinStar Lab), genomic data privacy, and energy market cybersecurity. His work addresses UN SDGs through contributions to quality education (SDG 4) and industry innovation (SDG 9). Recent publications highlight advancements in lattice-based cryptography (e.g., CRYSTALS-Kyber variants), privacy-preserving energy trading, and secure blockchain protocols like FPPW watchtower systems. His research bridges theoretical cryptography with practical implementations in embedded systems and 5G telecommunications. Grants: 16 active/completed projects including $1.2M in ARC funding Advising: Supervising PhD projects on lattice applications in post-quantum crypto and blockchain Labs: Core member of Monash’s Software Defined Telecommunications (SDT) Lab and CollinStar Lab
Professor Peter Y. K. Cheung is a Professor of Digital Systems at Imperial College London, holding dual affiliations within the Department of Electrical and Electronic Engineering and the Dyson School of Design Engineering. His work focuses on reconfigurable systems, FPGA architectures, and high-level synthesis tools. He co-founded one of the UK's leading FPGA research groups with Professor Wayne Luk, addressing challenges in variability mitigation, reliability, and application-specific FPGA deployments. His research spans Field-Programmable Gate Arrays (FPGAs) Reconfigurable computing Neural network acceleration Cryptographic protocols Embedded systems He has pioneered techniques such as logic shrinkage for FPGA-based neural networks and developed frameworks like LUTNet for efficient inference. His contributions also include fault-tolerant FPGA designs and methodologies for distributed computation protocols. Key collaborations include work with the Department of Computing on FPGA-based AI acceleration and cybersecurity applications. His recent work explores edge computing, secure decentralized systems, and pandemic modeling using adaptive control strategies. Notable projects include the DSCS protocol for secure distributed computation, acceleration of gravitational wave detection algorithms, and energy-efficient CNN implementations. His research bridges hardware-software co-design with real-world applications in healthcare, finance, and aerospace.
Callie Hao is an Assistant Professor in the Department of Electrical and Computer Engineering at the Georgia Institute of Technology since 2021, holding the ON Semiconductor Junior Professorship. Her research bridges hardware efficiency and algorithmic innovation with significant industry and federal recognition. Education: Ph.D. in Electrical Engineering, Waseda University (2017) M.S. and B.S. in Computer Science and Engineering, Shanghai Jiao Tong University Research Focus: Dr. Hao pioneers software/hardware co-design for edge AI, specializing in hardware-efficient machine learning algorithms, FPGA-based reconfigurable computing, graph neural networks, and electronic design automation (EDA). Her work emphasizes neural architecture search, high-level synthesis optimization, and memory-efficient systems for embedded and IoT applications, driven by the philosophy that "1 + 1 > 2" for transformative efficiency gains. Publication Impact: Her 15 most recent publications (2023-2026) reveal a strategic shift toward machine learning-driven EDA tools, with 60% focused on high-level synthesis frameworks and 40% on graph neural network acceleration. Key trends include simulation speed breakthroughs (LightningSim), automated accelerator generation (GNNBuilder), and cryptographic hardware innovations (Cryptonite), predominantly published in top-tier venues like MICRO, ICCAD, and DAC. Awards & Recognition: NSF CAREER Award (2024) and Intel Rising Star Faculty Award (2023) Best Paper Awards at MLCAD 2024 and GLSVLSI 2021 ON Semiconductor Junior Professorship (2025) and Sutterfield Family Early Career Professorship (2022) DAC-SDC competition championships (2018-2020) Mentorship & Funding: Dr. Hao advises 8+ Ph.D. students in the Sharc Lab, with Rishov Sarkar winning the Oscar P. Cleaver Award and Qualcomm Innovation Fellowship. Her research is funded by DARPA (2021) for ultra-light video intelligence systems and supported by industry awards from Amazon and Sony. She actively serves on program committees for DAC, ICCAD, and DATE conferences. Lab Leadership: As director of the Sharc Lab (Software/Hardware Co-design lab), she cultivates interdisciplinary research at the intersection of FPGA design, machine learning, and EDA, requiring expertise in Verilog/HLS, GNNs, and compiler technologies while maintaining strict focus on real-world hardware implementation.
Brandon Reagen is an Assistant Professor in the Department of Electrical and Computer Engineering at New York University's Tandon School of Engineering, with affiliations in Computer Science, the Center for Advanced Technology in Telecommunications (CATT), and the NYU Center for Cybersecurity (CCS). He holds a PhD in Computer Science from Harvard (2018) and undergraduate degrees in Computer Systems Engineering and Applied Mathematics from the University of Massachusetts, Amherst (2012). His research focuses on computer architecture, hardware acceleration for deep learning and privacy-preserving computation, and VLSI design. He pioneered efficient deep learning accelerator designs through unsafe optimizations and contributed to benchmarking frameworks like Aladdin and MachSuite. His work spans privacy-preserving machine learning, secure computing systems, and hardware-software co-design for cryptographic protocols. Key achievements include the NSF CAREER Award (2024) and Siebel Scholar recognition (2018). His research centers on advancing secure computing through innovations like zero-knowledge proof accelerators (e.g., zkSpeed), fully homomorphic encryption frameworks (Orion), and entropy-guided privacy techniques for large language models. He leads interdisciplinary efforts at CATT and CCS to bridge hardware design and cybersecurity challenges. Reagen's contributions include over 50 publications in top-tier conferences (e.g., ISCA, ASPLOS, MLSys) and industry collaborations at Facebook AI. His work emphasizes practical solutions for encrypted computation efficiency, privacy-preserving inference, and scalable secure systems.
Caroline Trippel is an Assistant Professor in the Departments of Computer Science and Electrical Engineering at Stanford University. Her research focuses on ensuring correctness and security in computer systems through formal methods, with particular emphasis on hardware verification, memory consistency models, and mitigating vulnerabilities like Spectre/Meltdown. She previously worked at Facebook’s FAIR SysML group before joining Stanford. Education: PhD in Computer Science, Princeton University BS in Computer Engineering, Purdue University Her work has influenced the RISC-V ISA memory consistency model and produced tools like CheckMate, which automatically synthesizes hardware exploits for security verification. She explores privacy-preserving ML, ML-driven hardware optimizations (e.g., neural recommendation), and datacenter reliability. Her research has earned awards including the 2020 ACM SIGARCH Dissertation Award and NVIDIA Fellowship. Key contributions include: Formal analysis of RISC-V memory models Exploitation synthesis frameworks (CheckMate) Hardware-software contracts for security Defenses against microarchitectural side-channel attacks Current projects include: VeriCoder: LLM-enhanced RTL code verification Multi-μPATH synthesis for security validation Near-data processing (RecSSD) for recommendation systems
Assoc Prof Wu Hongjun is an Associate Professor at the Division of Mathematical Sciences, School of Physical & Mathematical Sciences, Nanyang Technological University (NTU). His research focuses on cryptography and information security, with notable contributions to lightweight authenticated encryption algorithms like TinyJAMBU and ACORN, as well as cryptanalysis of stream ciphers (e.g., ZUC, HC-128) and hash functions (e.g., JH, SHA-3 candidates). His academic career includes over 15 years of contributions to cryptographic standards, IoT security frameworks, and secure cloud data management. Key areas of expertise encompass symmetric-key cryptography, algorithm design for resource-constrained devices, and vulnerability analysis of cryptographic primitives. Prof Wu has authored influential papers on authenticated encryption modes (AEGIS, MORUS), lightweight cipher optimizations (ACORN), and cryptanalysis techniques applied to Feistel networks and stream ciphers. His work bridges theoretical cryptography with practical implementations across telecommunications, IoT, and cloud computing domains.
Nicola Nicolici is a Professor in the Department of Electrical and Computer Engineering at McMaster University. His research focuses on methods and algorithms for the design of digital integrated circuits and systems, with significant contributions in manufacturing test, post-silicon validation and debug. His work has expanded to include embedded systems, low-energy computing, and custom hardware-accelerated computing systems. Professor Nicolici's research interests span multiple areas of digital system design and validation. His early work focused on manufacturing test methodologies and power-aware testing strategies for integrated circuits. More recently, he has made significant contributions to post-silicon validation techniques, including constrained-random stimuli generation, trace signal selection, and bit-flip detection. His research has evolved to address emerging challenges in embedded computing systems, low-energy design, and specialized hardware acceleration for various applications including deep neural networks and signal processing. His recent publications reveal a strong trend toward hardware acceleration for specialized computing tasks. The research spans matrix multiplication algorithms (Strassen and Karatsuba), memory system optimization (DDR5 calibration), FPGA-based radar processing, and neural network acceleration. His work consistently bridges theoretical algorithm development with practical hardware implementation considerations, particularly focusing on precision analysis, fault tolerance, and energy efficiency. The research demonstrates a clear progression from traditional digital circuit testing to more complex system-level validation and acceleration techniques. Professor Nicolici has been actively involved in teaching courses related to system-on-chip design and test, digital systems, and embedded systems. His teaching portfolio includes advanced courses such as System-on-Chip (SOC) Design and Test and Digital Systems Design , reflecting his expertise in the field. While specific grant information isn't detailed in the provided text, his extensive publication record suggests ongoing research funding support. His research has contributed significantly to the fields of digital circuit testing, post-silicon validation, and hardware acceleration. The work has practical applications in semiconductor manufacturing, embedded systems design, and specialized computing architectures. His recent focus on neural network acceleration and memory system optimization reflects the evolving landscape of computer architecture research.
Ada Gavrilovska is a Professor at Georgia Tech's School of Computer Science under the College of Computing. Her work focuses on systems software for emerging technologies, including hybrid memory systems, edge computing, and cloud infrastructure. She leads projects in the PRISM Center and ADA Center , with funding from NSF, DoE, SRC, and industry leaders like Cisco and VMware. Education: PhD in Computer Science, Georgia Tech (2004) Research Interests: Designing systems for new hardware and applications, including edge computing, heterogeneous memory management, and LEO satellite platforms. Her work bridges low-level OS mechanisms with high-level distributed systems challenges. Recent Publications highlight trends in LEO satellite resource scheduling Edge-based ML preprocessing Hybrid memory OS abstractions Disaggregated graph analytics Compiler-assisted performance optimization Scientific Awards: Best paper, NFV World Congress (2016) Spotlight paper, IEEE Transactions on Cloud Computing (2014) ISCA-50 25-year retrospective (2023) Advising & Grants: Ada has mentored over 15 PhD students and 10 MS students, with research supported by NSF, DoE, SRC, and industry grants. She serves as PI in the SRC/DARPA PRISM Center.
Dr. Krishnendu Guha is an Assistant Professor and CONNECT Funded Investigator at the School of Computer Science and Information Technology, University College Cork. His research bridges embedded systems, cybersecurity, and quantum-safe hardware design with AI and bio-inspired strategies. PhD: University of Calcutta (Department of Science and Technology, Government of India) Postdoctoral: University of Florida Past Roles: Research Fellow at Intel India, Visiting Scientist at Indian Statistical Institute, Temporary Assistant Professor at NIT Jamshedpur His research focuses on embedded systems security , real-time security mechanisms , and quantum-safe hardware . He integrates AI (e.g., neural networks) and bio-inspired strategies (e.g., gecko crypsis behavior) into security frameworks for FPGAs and edge platforms. Recent publications highlight trends in blockchain for supply chains , quantum machine learning , secure FPGA architectures , and distributed AI systems . His work addresses energy efficiency, fault detection, and decentralized security in hardware. As a CONNECT Centre member, Dr. Guha contributes to advanced research in reconfigurable systems and cybersecurity. Grants and collaborations span quantum-safe design, cloud FPGA security, and hardware trojan mitigation.
Vincent John Mooney III is an Associate Professor at the School of Electrical and Computer Engineering and an Adjunct Associate Professor at the School of Computer Science, Georgia Institute of Technology. His research focuses on Hardware-Software Co-Design , Cyber Physical Systems Security , and Low-Power Architectures . He has authored numerous publications on topics such as probabilistic computing, hardware security, and embedded systems design. Dr. Mooney has received prestigious awards including the NSF Career Award , National Semiconductor Fellowship , and ARCS Best Paper Award . Education: Ph.D. in Electrical Engineering (1998), Stanford University MA in Philosophy (1997), Stanford University MS in Electrical Engineering (1994), Stanford University Certificate of Graduate Study (1992), University of Navarra BS in Electrical Engineering and Computer Science (1991), Yale University Research interests span hardware/software codesign, cybersecurity in embedded systems, and synthesis of reconfigurable architectures. His recent work includes Gridtrust for decentralized supply chain cybersecurity and COPPER for computation obfuscation. Dr. Mooney has supervised numerous Ph.D. students and held leadership roles in conferences such as HOST and CASES . Scientific awards include NSF Career Award (2000) National Semiconductor Fellowship (1997-1998) AT&T Engineering Scholarship Program (1987-1991) NCAA Postgraduate Scholar (1991) Senior Member, IEEE (2003) ARCS 2012 Best Paper Award Advising and grants highlight his mentorship of students like Jun Cheol Park and Yudong Tan , along with grants such as the U.S. Air Force Summer Faculty Fellowship (2007). He leads the Hardware/Software Codesign for Security Group at Georgia Tech and has contributed to advancements in real-time operating systems and deadlock detection algorithms.
Zakir Durumeric is an Assistant Professor of Computer Science at Stanford University, leading the Stanford Empirical Security Research Group. His research focuses on Internet security, trust, and safety, emphasizing large-scale network measurement and open-source tool development. He founded Censys, a platform providing global Internet device data, and maintains tools like ZMap, ZGrab, and Retina. Research interests include cybercrime prevention, censorship analysis, disinformation tracking, and platform governance for online harassment. Notable contributions include studies on the Mirai botnet, TLS certificate ecosystems, and vulnerabilities like Heartbleed and Logjam. Awards include the IRTF Applied Networking Research Prize (2015) and a Test of Time Award (2022). Teaches courses: CS155 (Computer & Network Security), CS356 (Systems & Network Security), and CS249i (Modern Internet). Advises over 20 students, including Catherine Han, Kimberly Ruth, and Liz Izhikevich. Develops open-source software such as ZMap Toolkit and ASdb, and maintains datasets like CrUX Top Million Websites. Recent work explores toxic online behavior, misinformation ecosystems, and regional censorship mechanisms in China. His lab’s tools are widely adopted in academia and industry for security research and policy guidance.
Md Sakib Hasan is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Mississippi. He holds a Ph.D. in Electrical Engineering from the University of Tennessee-Knoxville (2017). His research focuses on hardware acceleration, neuromorphic computing, and memristor-based systems. Research interests span: AI hardware accelerators and energy-efficient computing Biomimetic systems and bio-inspired electronics Hardware security through chaotic systems and PUFs Recent publications demonstrate strong emphasis on: Neuromorphic architectures for computer vision and temporal processing Biomembrane-based computing systems Chaotic cryptography and secure hardware design
Jeyavijayan 'JV' Rajendran is an Associate Professor in the Department of Electrical and Computer Engineering at Texas A&M University, part of the College of Engineering. He is an ASCEND Fellow and leads the Secure and Trustworthy Hardware (SETH) Lab. His research focuses on hardware security, computer security, and novel applications of AI in secure hardware design. Education: PhD in Electrical Engineering (NYU 2015), MS in Computer Engineering (NYU Tandon 2010), BE in Electronics and Communication Engineering (Anna University 2008). Research Interests: Hardware Security, Computer Security, Logic Locking, Hardware IP Protection, and Reinforcement Learning for Security. He explores AI-driven approaches to detect vulnerabilities, protect intellectual property, and enhance secure hardware design through fuzzing, obfuscation, and formal verification. Notable Awards: 2022 Office of Naval Research Young Investigator Award, 2021 IEEE CEDA Ernest Kuh Early Career Award, 2017 NSF CAREER Award. Lab and Teams: The SETH Lab focuses on trustworthy hardware design, developing techniques to secure integrated circuits against reverse engineering and IP theft. Current projects include LLM-based hardware code generation, formal approaches for hardware fuzzing, and AI-driven vulnerability detection.
