Tomas Palacios is a Professor of Electrical Engineering at the Massachusetts Institute of Technology (MIT) , where he directs the Center for Graphene Devices and 2D Systems and leads the Microsystems Technology Laboratories (MTL). His research focuses on pushing the boundaries of microelectronics through novel semiconductor materials and device architectures, including Gallium Nitride (GaN) and 2D materials like graphene and molybdenum disulfide (MoS2). Professor, MIT Electrical Engineering and Computer Science Director, MIT Center for Graphene Devices and 2D Systems Clarence J. LeBel Professor, MIT Faculty Director, Northeast Microelectronics Internship Program (NMIP) Research Interests span multiple cutting-edge domains: High-frequency electronics (>300 GHz) for 6G and quantum applications High-voltage power devices (600V–10kV) for energy conversion Post-silicon logic devices using 2D materials High-temperature electronics (e.g., Venus rover applications) Distributed neural networks on large-area 2D materials Graphene-based biosensors and chemical detection systems Scientific Contributions include: Double recipient of the IEEE George Smith Award for groundbreaking GaN transistor work Co-invented first MoS2 electronic circuits Developed world’s first Wi-Fi-to-electricity conversion antenna Led MIT’s Microsystems Technology Laboratories since 2021 Advising Philosophy emphasizes cross-layer expertise, with students gaining experience from materials synthesis to system-level prototyping. His lab has incubated startups like Vertical Horizons , focused on GaN power devices for AI and EVs.
Subhasish Mitra is the William E. Ayer Professor of Electrical Engineering and Computer Science at Stanford University, holding dual appointments in both departments. He leads the Stanford Robust Systems Group and serves on the leadership team of the Microelectronics Commons AI Hardware Hub under the US CHIPS and Science Act. His research spans Robust Computing, NanoSystems, Electronic Design Automation (EDA), and Neurosciences, with breakthroughs in X-Compact test compression, carbon nanotube computing, and 3D integration. He has held international roles like the Carnot Chair at CEA-LETI and Visiting Professorships globally. Education & Honors: Recipient of over 40 awards including the IEEE Computer Society’s Harry H. Goode Memorial Award, ACM/IEEE’s A. Richard Newton Technical Impact Award, and the Intel Achievement Award. He earned top academic accolades from IIT Kharagpur and Jadavpur University, and is a Fellow of ACM and IEEE. Research Impact: Pioneered first-of-their-kind systems like the carbon nanotube computer and monolithic 3D integration. His work on robust computing techniques like QED validation and X-Compact compression has industry-wide adoption, saving billions in manufacturing costs. Collaborates with industry leaders like Intel, Google, and Samsung. Publications & Grants: Over 400 publications, including award-winning papers in DAC, ISSCC, and IEEE journals. Leads grants from NSF, DoE, and industry partnerships. His lab explores cutting-edge topics like neuromorphic computing, 3D thermal scaffolding, and AI hardware acceleration. Administration & Outreach: Serves as Associate Chair (Faculty Affairs) for Stanford’s Computer Science Department. Recognized by students for mentorship, and frequently invited to global forums like the World Economic Forum and National Academy of Engineering.
Rakesh Kumar is a Professor and John Bardeen Faculty Scholar in the Electrical and Computer Engineering Department at the University of Illinois at Urbana-Champaign. His work focuses on computer architecture, system-level design automation, and low-power computing. PhD in Computer Engineering from University of California, San Diego BS in Electrical Engineering from IIT Kharagpur His research spans all layers of the computing stack, with key contributions to flexible computer systems , waferscale computing , error-resilient architectures , and approximate computing . He has pioneered work on voltage-reliability tradeoffs and peak power management techniques. Recent publications highlight trends in space microdatacenters , printed microprocessors , and neural graph accelerators . His work on plastic chips was recognized as one of the three biggest semiconductor headlines of 2022 by IEEE Spectrum. IEEE Fellow (2024) ISCA Influential Paper Award MICRO Test-of-Time Award ICCAD Ten Year Retrospective Most Influential Paper Award Best Paper Awards at CASES, SELSE, HPCA He has received teaching accolades including the Stanley H. Pierce Faculty Award and Ronald W. Pratt Outstanding Teaching Award . His research group explores hardware-software co-design for emerging applications in AI, IoT, and sustainable computing.
Daniel E. Ho holds multiple prestigious positions at Stanford University: William Benjamin Scott and Luna M. Scott Professor of Law Professor of Political Science Professor of Computer Science (by courtesy) Senior Fellow, Stanford Institute for Economic Policy Research Senior Fellow, Stanford Institute for Human-Centered Artificial Intelligence Faculty Fellow, Center for Advanced Study in the Behavioral Sciences He serves on the National Artificial Intelligence Advisory Commission (NAIAC), as Senior Advisor on Responsible AI at the U.S. Department of Labor, and as a Public Member of the Administrative Conference of the United States (ACUS). Ho earned his J.D. from Yale Law School and Ph.D. from Harvard University, completing a clerkship with Judge Stephen F. Williams on the U.S. Court of Appeals for the District of Columbia Circuit. His research bridges artificial intelligence, law, and public policy with emphasis on: Regulatory governance frameworks for AI systems Fairness and bias mitigation in algorithmic decision-making Environmental enforcement using satellite imagery and computer vision Methods for estimating racial disparities without direct demographic data Legal AI reliability and statutory research systems Analysis of his 2025 publications reveals a consistent focus on practical AI governance tools addressing real-world regulatory challenges. Key themes include developing benchmarks for legal applications, mitigating hallucination in legal AI tools, and creating systems for statutory research. His work demonstrates strong integration of technical AI methods with policy implementation, particularly in environmental enforcement and fairness assessment. As Director of the Regulation, Evaluation, and Governance Lab (RegLab), Ho leads interdisciplinary research partnerships with government agencies. While specific grant details aren't provided, RegLab's operational model indicates substantial research funding for policy-relevant AI projects. No student advisees are mentioned in available materials. Ho's leadership extends to national advisory roles where he shapes federal AI policy through evidence-based recommendations, particularly regarding environmental protection and civil rights enforcement mechanisms.
Muhannad S. Bakir is the Dan Fielder Professor in the School of Electrical and Computer Engineering at Georgia Institute of Technology and serves as the Director of the 3D Systems Packaging Research Center. His research focuses on heterogeneous integration of microsystems, including 2.5D and 3D ICs and packaging technologies, with significant contributions to advanced cooling systems, electrical and photonic interconnects, and biosensor integration with CMOS. Dr. Bakir's research interests span heterogeneous microsystem design and integration, advanced cooling and power delivery for emerging architectures, electrical and photonic interconnect technologies, biosensor technologies, and nanofabrication. His work addresses critical challenges in next-generation electronics, enabling polylithic integration that concatenates heterogeneous ICs of various functionalities while mimicking monolithic-like densities. His research particularly focuses on co-design of thermal technologies, power delivery networks, and signaling networks for silicon nanoelectronic systems. His recent publications demonstrate strong trends in fused-silica stitch-chip technology for heterogeneous integration, with particular emphasis on RF and mm-wave applications, power delivery for AI accelerators, and thermal management solutions. His work bridges electrical engineering, materials science, and thermal management to solve critical bottlenecks in computing performance and efficiency. 2013 Intel Early Career Faculty Honor Award 2012 DARPA Young Faculty Award 2011 IEEE CPMT Society Outstanding Young Engineer Award 2012 National Academy of Engineering Frontiers of Engineering Symposium Invited Participant 2015 IEEE CPMT Society Distinguished Lecturer 2014 Best Paper of the IEEE Transactions on Components Packaging and Manufacturing Technology More than 25 conference and student paper awards Twelve issued US Patents Dr. Bakir leads the Integrated 3D Systems Lab (I3DS) at Georgia Tech, which is actively researching advanced packaging, interconnects, electrical and thermal design, and system integration. His team has received significant recognition for their work, including multiple best paper awards from major conferences like ECTC, IITC, and CICC. The lab is currently seeking postdoctoral researchers and research faculty to advance next-generation electronics through collaborative research. His lab focuses on enabling the next phase of Moore's Law through polylithic integration, which concatenates heterogeneous ICs of various functionalities (digital, analog, photonic, and mm-wave) using advanced off-chip '2.5D' and '3D' heterogeneous interconnects and packaging. This work impacts applications in high-performance computing, machine learning, edge intelligence, autonomous vehicles, augmented/virtual reality, and healthcare.
Sumeet Kumar Gupta is an Associate Professor in the Department of Electrical and Computer Engineering at Purdue University. His academic career spans from his current role to a prior Assistant Professorship at Pennsylvania State University (2014-2017) and an engineering position at Qualcomm Inc. (2012-2014). He holds a PhD in Electrical and Computer Engineering from Purdue University (2012), an M.S. from the same institution (2008), and a B.Tech in Electrical Engineering from IIT Delhi (2006). B.Tech, Electrical Engineering, IIT Delhi (2006) M.S., Electrical and Computer Engineering, Purdue University (2008) PhD, Electrical and Computer Engineering, Purdue University (2012) Dr. Gupta's research focuses on neuromorphic computing, low power variation-aware VLSI design in emerging nanotechnologies, device-circuit co-design, and nano-scale device modeling/simulations. His work addresses challenges in ferroelectric materials, crossbar arrays for deep neural networks, and energy-efficient AI hardware. Recent publications (2025-2024) highlight trends in: Ferroelectric HfO2/HZO thin films Compute-in-memory architectures Variability/stochasticity analysis Machine learning for device optimization Interconnect resistance/temperature effects AI hardware fault tolerance Scientific Awards & Recognitions: DARPA Young Faculty Award (2016) Early Career Professorship, Penn State (2014) 6th TSMC Outstanding Student Research Bronze Award (2012) Magoon Award (Purdue) Outstanding Teaching Assistant Award (Purdue, 2007) Intel PhD Fellowship (2009) His professional journey includes academic appointments at Purdue University (2020-present, Associate Professor) and Pennsylvania State University (2014-2017, Assistant Professor) after industry experience at Qualcomm Inc. (2012-2014). He maintains IEEE and EDS membership while publishing over 100 refereed works.
Matteo Sonza Reorda is a Full Professor at the Polytechnic University of Turin, affiliated with the Department of Automatic Control and Computer Science (DAUIN). He holds roles such as Partnership Agreement Coordinator with SMAT and has served as Vice-Rector for Research (2021–2024). His research focuses on fault tolerance, hardware reliability, and AI acceleration, with contributions to GPU/CNN reliability, self-test libraries, and defect-oriented testing. Education: M.S. in Electronics Engineering, Politecnico di Torino (1986) Ph.D. in Computer Engineering, Politecnico di Torino (1990) Research Interests: His work spans automatic test equipment, circuit reliability, GPU fault tolerance, neural network hardening, and embedded systems safety . He leads the Electronic CAD & Reliability Group and collaborates with institutions like the ISI Foundation and the National Research Council (CNR). Publications & Impact: With over 180 publications, his recent work emphasizes AI accelerator reliability, fault injection techniques, and safety-critical systems. Key trends include GPU resilience for CNNs, self-test library optimization, and radiation fault modeling in neural networks. Awards & Recognition: IEEE Fellow (2016–) Multiple best-paper awards at IEEE conferences (DDECS, DATE, etc.) Grants & Collaborations: Coordinator of EU projects (RESCUE, TUTORIAL) Partnerships with EDF, Marelli Europe, and SMAT Lead on National HPC/Quantum Computing Spoke 1 (2022–2025) Labs/Teams: Leads the CAD Group and collaborates with the French-Italian LIA LAFISI lab on hardware-software integration.
Dana Anderson is a Professor of Physics and JILA Fellow at the University of Colorado Boulder. He holds dual affiliations with the Department of Physics and JILA, a joint institute between the University of Colorado Boulder and the National Institute of Standards and Technology (NIST). His research focuses on ultracold atoms, quantum computing, and atomtronics, with applications in quantum sensing and space-based experiments. He currently serves as Chief Strategy Officer (CSO) of Infleqtion (formerly ColdQuanta), a quantum technology company he co-founded. Anderson is a principal investigator in the Quantum Pathways Institute, a NASA-funded initiative to develop quantum-based Earth-sensing technologies. He collaborates with institutions like NIST, JPL, and ColdQuanta on projects such as the Cold Atom Laboratory (CAL) for space-based ultracold atom research. His work has been recognized by TIME Magazine and led to significant grants, including a $15M NASA award for quantum space research. Research interests include atomtronics (hybrid atom-electronics systems), neutral atom quantum computing, and ultracold atom gyroscopes. His group develops novel atom chip technologies, such as window atom chips enabling high-resolution imaging, and explores applications like matterwave transistors and quantum inertial sensors. Current projects include shaken lattice interferometry for navigation and Rydberg atom-based microwave sensors. Anderson has pioneered concepts like the matterwave transistor oscillator and contributed to the first neutral atom quantum computing arrays. His work bridges fundamental physics and applied technologies, with a focus on translating quantum phenomena into practical devices. He actively mentors students and postdocs in experimental atomic physics and quantum engineering.
Geng Yuan is an Assistant Professor at the University of Georgia's School of Computing, specializing in AI systems, energy-efficient deep learning, and hardware-software co-design. His work bridges machine learning algorithms with emerging hardware technologies like superconducting circuits and ReRAM. He holds a Ph.D. in Computer Engineering from Northeastern University (2023) and a Master's in Electrical & Computer Engineering from Syracuse University (2016). Doctor of Philosophy (Ph.D.) in Computer Engineering, Northeastern University (2023) Master of Science (M.S.) in Electrical & Computer Engineering, Syracuse University (2016) Bachelor of Science (B.S.) in Electrical Engineering, Beijing University of Technology (2014) His research focuses on optimizing deep learning systems for edge computing and mobile platforms through techniques like model compression, sparse training, and hardware-aware neural architecture search. Recent projects include adapting large language models via hybrid-grained pruning and developing ultra-low-power AQFP circuits for binary networks. Geng Yuan's publications span top venues like NeurIPS, CVPR, ICML, ICLR, ISCA, and DAC, with notable awards including a Best Paper Award at ICLR Workshop 2021, Spotlight Papers at ICLR 2023 and NeurIPS 2021, and a Design Contest 1st Place at ISLPED 2020. Best Paper Award (ICLR Workshop'21) Spotlight Paper Award (ICLR'23, NeurIPS'21) Design Contest 1st Place (ISLPED'20) Best Paper Nomination (DATE'21, ISQED'18) He actively recruits Ph.D., Master's students, and interns to his research group, focusing on advancing AI systems through interdisciplinary approaches combining machine learning, computer architecture, and electronic design automation.
Naresh R. Shanbhag is the Jack Kilby Professor in the Department of Electrical and Computer Engineering and the Coordinated Science Laboratory at the University of Illinois at Urbana-Champaign. He serves as Director of the Systems on Nanoscale Information fabriCs (SONIC) Center and held the D.J. Gandhi Distinguished Visiting Professorship at IIT Mumbai from 2015-2020. Previously, he was a visiting faculty member at National Taiwan University (2007) and Stanford University (2014). Dr. Shanbhag received his doctorate from the University of Minnesota (1993) in Electrical Engineering. From 1993 to 1995, he worked at AT&T Bell Laboratories as the lead chip architect for AT&T's 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and very high-speed digital subscriber line (VDSL) chip-sets. His research focuses on the design of energy-efficient machine learning, communications, and signal processing systems on resource-constrained embedded platforms. He explores fundamental trade-offs between energy efficiency, latency and accuracy of decision-making systems implemented in nanoscale technologies, with applications to computer vision, biomedicine, automatic target recognition, and imaging. His work spans four primary focus areas: Resource-efficient Machine Learning for the Edge, In-memory Computing (IMC), Energy-efficient High Data Rate Communications, and Shannon-inspired Statistical Error Compensation (SEC). Analysis of his recent publications reveals a strong emphasis on in-memory computing architectures (SRAM, MRAM, RRAM) for machine learning acceleration. His work consistently addresses energy-accuracy trade-offs, with increasing attention to security aspects of hardware implementations and applications to MIMO signal processing and edge AI systems. His research demonstrates a progression from theoretical foundations to practical silicon implementations. 2024 Semiconductor Research Corporation Innovation Award 2018 Semiconductor Industry Association/Semiconductor Research Corporation University Researcher Award 2018 IEEE International Symposium on Circuits and Systems Best Paper Award 2006 IEEE Fellow 1996 National Science Foundation CAREER Award Professor Shanbhag has mentored over 50 graduate students who now work at leading technology companies including Qualcomm, Amazon, Nvidia, Intel, and Apple. His research has been generously supported by the National Science Foundation, DARPA, AFRL, Semiconductor Research Corporation, Texas Instruments, Sandia National Laboratories, and industry partners including IBM, GlobalFoundries, and Intel Corporation. He led the Alternative Computational Models research theme (2006-2012) and was the founding Director of the SONIC Center (2013-2017), a 5-year multi-university center funded by DARPA and SRC. Currently, he leads research themes in the SRC and DARPA funded JUMP 2.0 Program's Center for Co-Design of Cognitive Systems and the Center for Ubiquitous Connectivity, and in the NSF IUCRC Center for Advanced Semiconductor Chips with Accelerated Performance (ASAP). As Director of the Systems on Nanoscale Information fabriCs (SONIC) Center, Professor Shanbhag leads a multidisciplinary team exploring novel computing paradigms for the nanoscale era. His group has benchmarked an extensive collection of in-memory computing and digital accelerator IC designs, maintaining a publicly available IMC benchmarking repository of metrics extracted from published IC prototypes. His research philosophy integrates concepts from information theory, statistical signal processing, detection and estimation, VLSI architectures, and digital and analog integrated circuits to develop energy-efficient systems from algorithms to silicon implementations.
Luca Peretti is an Associate Professor in Electric Machines and Drives at KTH Royal Institute of Technology, affiliated with the School of Electrical Engineering and Computer Science and the Department of Electrical Engineering, Division of Electric Power and Energy Systems. He works as a researcher in the EMD (Electric Machines and Drives) group and serves as Partner Director for KTH's strategic partnership with ABB. Education: M.Sc. in Electronic Engineering (2005) from University of Udine, Ph.D. from University of Padova (2008) Professional Experience: Postdoc at University of Padova (2009-2010), Principal Scientist at ABB Corporate Research (2010-2018), Associate Professor at KTH (2018-present) His research focuses on: Automatic parameter estimation in electric machines Multiphase drive systems Sensorless control algorithms Loss segregation in drive systems Condition monitoring of industrial and transportation applications Recent publications demonstrate expertise in variable phase-pole machines, harmonic plane decomposition, predictive control algorithms, and advanced modeling of permanent magnet motors. Key application areas include transportation electrification, wind energy systems, and industrial drive technologies. Scientific roles include: Associate Editor, IET Electric Power Applications Journal (2019-present) Theme Co-Leader, Swedish Electromobility Center (2020-present) Member, IEEE (2021-present) and IET (2006-present) He leads the strategic partnership with ABB and contributes to doctoral program committees at University of Padova.
Kristofer Pister is a Professor in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. He co-directs the Berkeley Sensor and Actuator Center (BSAC) and the Ubiquitous Swarm Lab. His career spans groundbreaking innovations in Micro/Nano Electro Mechanical Systems (MEMS), Control Systems, and Low-Power Circuits, with a focus on Smart Dust and synthetic insects. Education: Ph.D. and M.S. in EECS from UC Berkeley (1992, 1989); B.A. in Applied Physics from UC San Diego (1986). His research areas include MEMS , Control Systems , Robotics , and Integrated Circuits , with recent work on self-powered micro-sensors, crystal-free radios, and interplanetary swarm networks. Key awards include the ISA Albert F. Sperry Founder Award (2009) , Alexander Schwarzkopf Prize (2006) , and the NSF CAREER Award (1996) . He has authored numerous influential publications in wireless sensor networks and microrobotics. His lab, Ubiquitous Swarm Lab , explores distributed robotics and swarm intelligence. Pister emphasizes open collaboration in research, ethical conduct in academia, and efficient resource utilization for graduate students.
Holger Fröning is a full professor at Heidelberg University’s Institute of Computer Engineering (ZITI), where he leads the Hardware and Artificial Intelligence (HAWAII) Lab. His research focuses on embedded machine learning , high-performance computing , and hardware-software co-design , with emphasis on resource efficiency, power optimization, and emerging architectures like analog , photonic , and resistive memory systems. He has held leadership roles including Managing Director of ZITI (2023–present) and Dean of Studies for Computer Science (2019–2022) , and has collaborated with institutions such as NVIDIA Research, Chinese Academy of Sciences, and Graz University of Technology. Research Trends : His recent publications explore Bayesian neural networks , green machine learning , analog computing noise mitigation , and GPU/FPGA optimization . Articles highlight photonic computing for AI , memory-efficient training , and hardware-aware DNN compression . Scientific Awards : 2025 HiPEAC Paper Award (Nature Computational Science) 2014 Google Faculty Research Award Multiple Best Paper Awards (IPDPS, ICPP, ECML-PKDD workshops) Leadership & Service : Organized workshops (WEML, ITEM, F4HD), chaired tracks at EuroPar and ISC, and served on program committees for ICPR, ECAI, and FPL. Education & Affiliations : PhD and MSc from University of Mannheim (2007/2001). Sponsors include DFG, FWF, FFG, NVIDIA, SAP, and XILINX.
Elison Matioli is a Professor at the Institute of Electrical Engineering (STI) at EPFL and director of the POWERlab. He holds a B.Sc. in Applied Physics and Applied Mathematics from Ecole Polytechnique (France), a B.Sc. in Electrical Engineering from the University of São Paulo (Brazil), and a Ph.D. in Materials Science from the University of California, Santa Barbara. His postdoctoral research at MIT focused on electrical engineering and computer science. His research centers on advanced semiconductor devices, particularly GaN-based power electronics, microfluidic cooling systems, and nanotechnology innovations for high-power applications. Key areas include developing high-efficiency GaN transistors, optimizing power conversion systems, and exploring terahertz generation through nanoplasma switches. His work emphasizes integrating novel materials (e.g., diamond, LiNiO) and cooling solutions to enhance device performance and reliability. Publications highlight breakthroughs in GaN power devices, microfluidic integration for thermal management, and ultrafast switching technologies. His contributions span device physics, fabrication techniques, and energy-efficient systems, with applications in next-generation power electronics and renewable energy infrastructure.
Christof Paar is a Professor of Embedded Security at Ruhr University Bochum's Faculty of Computer Science. His work focuses on hardware security, cryptography, and embedded systems security. He leads the Embedded Security Group within the CASE Cluster of Excellence (Cyber Security in the Age of Large-Scale Attacks), addressing cutting-edge challenges in hardware Trojans, side-channel attacks, and cryptographic engineering. His research spans FPGA and IoT security, with contributions to physical-layer security, wireless jamming defenses, and tamper-resistant systems. Research Interests: Paar's expertise lies in hardware-software co-design for security, with a focus on embedded systems. His work includes analyzing vulnerabilities in FPGAs, developing countermeasures against side-channel attacks, and exploring physical-layer security mechanisms. He also investigates the human factors in hardware reverse engineering and the implications of adversarial machine learning on security systems. Notable Work: Recent publications highlight breakthroughs in detecting hardware Trojans across CMOS generations, breaking industry-standard IP protection mechanisms (IEEE 1735), and proposing novel defenses like IRShield against adversarial wireless sensing. His group actively contributes to standards for secure embedded systems and IoT devices, emphasizing practical implementations.
