جست‌وجوی استاد و پژوهشگر

Muhannad S Bakirمشاهده پروفایل

استاد

• Heterogeneous Integration
• 3D IC Packaging
• Advanced Cooling Systems
• +۷ مورد دیگر

Muhannad S. Bakir is the Dan Fielder Professor in the School of Electrical and Computer Engineering at Georgia Institute of Technology and serves as the Director of the 3D Systems Packaging Research Center. His research focuses on heterogeneous integration of microsystems, including 2.5D and 3D ICs and packaging technologies, with significant contributions to advanced cooling systems, electrical and photonic interconnects, and biosensor integration with CMOS. Dr. Bakir's research interests span heterogeneous microsystem design and integration, advanced cooling and power delivery for emerging architectures, electrical and photonic interconnect technologies, biosensor technologies, and nanofabrication. His work addresses critical challenges in next-generation electronics, enabling polylithic integration that concatenates heterogeneous ICs of various functionalities while mimicking monolithic-like densities. His research particularly focuses on co-design of thermal technologies, power delivery networks, and signaling networks for silicon nanoelectronic systems. His recent publications demonstrate strong trends in fused-silica stitch-chip technology for heterogeneous integration, with particular emphasis on RF and mm-wave applications, power delivery for AI accelerators, and thermal management solutions. His work bridges electrical engineering, materials science, and thermal management to solve critical bottlenecks in computing performance and efficiency. 2013 Intel Early Career Faculty Honor Award 2012 DARPA Young Faculty Award 2011 IEEE CPMT Society Outstanding Young Engineer Award 2012 National Academy of Engineering Frontiers of Engineering Symposium Invited Participant 2015 IEEE CPMT Society Distinguished Lecturer 2014 Best Paper of the IEEE Transactions on Components Packaging and Manufacturing Technology More than 25 conference and student paper awards Twelve issued US Patents Dr. Bakir leads the Integrated 3D Systems Lab (I3DS) at Georgia Tech, which is actively researching advanced packaging, interconnects, electrical and thermal design, and system integration. His team has received significant recognition for their work, including multiple best paper awards from major conferences like ECTC, IITC, and CICC. The lab is currently seeking postdoctoral researchers and research faculty to advance next-generation electronics through collaborative research. His lab focuses on enabling the next phase of Moore's Law through polylithic integration, which concatenates heterogeneous ICs of various functionalities (digital, analog, photonic, and mm-wave) using advanced off-chip '2.5D' and '3D' heterogeneous interconnects and packaging. This work impacts applications in high-performance computing, machine learning, edge intelligence, autonomous vehicles, augmented/virtual reality, and healthcare.

Peter Pietzuchمشاهده پروفایل

استاد

• Distributed Systems
• Cloud Computing
• Big Data Processing
• +۵ مورد دیگر

Peter Pietzuch is a Professor in the Department of Computing at Imperial College London, where he leads the Large-Scale Data & Systems (LSDS) group. He also serves as the Director of Research and is a Visiting Researcher at Microsoft Research Cambridge. Pietzuch holds a Ph.D. from the University of Cambridge and a B.A. from Girton College. His research spans distributed systems, cloud computing, big data processing, and systems security. Key interests include: Scalable architectures for cloud-native applications Efficient stream processing and machine learning systems Trusted execution environments and secure cloud infrastructure Optimization of serverless computing and distributed databases His recent publications focus on adaptive machine learning frameworks, secure cloud resource management, and high-performance stream processing systems. Trends show strong emphasis on hardware-software co-design, confidential computing, and fault-tolerant architectures. Awards include: Best Paper Award at Middleware'03 He actively advises PhD students and secures grants for projects like Faasm (serverless computing) and Teechain (blockchain security). His LSDS group collaborates with industry partners including Microsoft Research. Pietzuch teaches undergraduate and graduate courses including Scalable Systems for the Cloud and Operating Systems . He co-founded the ACM DEBS conference and serves on steering committees for EuroSys and Middleware.

Jonathan M. Bakerمشاهده پروفایل

استادیار

• Quantum Computing
• Quantum Computer Architecture
• Quantum Error Correction
• +۴ مورد دیگر

Jonathan M. Baker is an Assistant Professor in the Department of Electrical and Computer Engineering at The University of Texas at Austin, holding the Advanced Micro Devices Chair in Computer Engineering. His research centers on quantum computer architecture with emphasis on practical quantum error correction implementation across the quantum computing stack. His educational background includes a Ph.D. in Computer Science from the University of Chicago (advised by Fred Chong) and dual B.S. degrees in Mathematics and Chemistry and Computer Science from the University of Notre Dame. Baker's research spans quantum compilation, logic synthesis, multi-radix architectures, and error mitigation for both near-term and fault-tolerant quantum systems. His work addresses critical challenges in quantum hardware-software co-design, with particular focus on optimizing quantum circuits for real-world hardware constraints and noise characteristics. Current projects emphasize qudit-based computing, neutral atom architectures, and efficient error correction implementations. His publication record shows strong focus on quantum architecture innovations, with recent work exploring qudit advantages, modular chiplet designs, and dynamic noise adaptation. Key trends include hardware-aware compilation techniques, communication optimization across quantum systems, and practical approaches to fault tolerance. Best Paper Award Runner Up, MICRO 2020 IEEE Micro Top Pick, 2020 (Virtualized Logical Qubits) IEEE Micro Top Pick, 2020 (Extending Frontier with Qutrits) IEEE Micro Top Pick, 2021 (Emerging Technologies) Best Poster Award, MICRO 2018 Baker actively mentors graduate students in quantum computing architecture research and serves on conference review committees including MICRO and ASPLOS. His teaching includes specialized quantum systems courses at UT Austin and online EdX modules covering quantum computation fundamentals and architecture. He collaborates with the Duke Quantum Center and maintains strong industry connections through the AMD Chair position, focusing on bridging academic research with practical quantum computing implementations.

• Computer Architecture
• Computer Hardware
• Energy Efficiency
• +۴ مورد دیگر

Nam Sung Kim is the W. J. "Jerry" Sanders III-Advanced Micro Devices Inc. Endowed Chair and holds a Professorship in Electrical and Computer Engineering at the University of Illinois. He is also affiliated with the Siebel School of Computing and Data Science, Coordinated Science Lab, and National Center for Supercomputing Applications (NCSA). His research focuses on computer architecture, memory systems, chiplet integration, and hardware security. Key areas include energy-efficient computing, processing-in-memory (PIM), and mitigating hardware vulnerabilities like rowhammer attacks. Kim has received prestigious awards including IEEE Fellow (2016), MICRO Hall of Fame (2018), NAI Fellow (2023), and NSF CAREER Award (2015). His work spans publications in top venues like ASPLOS and IEEE journals, addressing topics such as CXL-based memory systems, DRAM module optimization, and GPU architecture improvements. Collaborations emphasize interdisciplinary research in hardware-software co-design and emerging technologies. His labs and teams at Coordinated Science Lab and NCSA drive innovations in scalable computing, near-memory processing, and cloud infrastructure for AI workloads. Ongoing projects include developing resilient memory hierarchies and accelerating large-scale machine learning models through novel architecture designs.

Dan Jiaoمشاهده پروفایل

استاد

• Computational Electromagnetics
• Computational Multiphysics
• Electronic Design Automation (EDA)
• +۸ مورد دیگر

Prof. Dan Jiao is the Synopsys Professor of Electrical and Computer Engineering at Purdue University's Elmore Family School. She leads the Rapid-Heterogeneous Integration (Rapid-HI) Design Institute and serves as Editor-in-Chief of the IEEE Journal on Multiscale and Multiphysics Computational Techniques. Her research focuses on computational electromagnetics, multiphysics modeling, and AI-driven design automation for advanced integrated circuits and quantum systems. She has held academic positions since 2005, progressing from Assistant to Full Professor, and has extensive industry experience at Intel Corporation (2001–2005). Education: PhD in Electrical Engineering, University of Illinois at Urbana-Champaign (2001) Senior Staff Engineer at Intel Corporation (2001–2005) Research Interests: Fast numerical methods for large-scale electromagnetic analysis AI/ML integration in design automation (EDA/MDA) Quantum circuits and spin qubit systems Heterogeneous integration and advanced packaging Multiphysics co-simulation for nano-scale devices Signal/power integrity in high-speed systems Key Projects: Leads the NSTC AIDRFIC program (first NSTC R&D Jump Start project), the DARPA NGMM Rapid-HI Design Institute, and the GENIE-RFIC generative design tool initiative. Also directs the Consortium for Electromagnetic Science and Technology. Awards & Honors: 2022 ACES Computational Electromagnetics Award IEEE Fellow (2016) Intel Outstanding Researcher Award (2019) MTT-S Distinguished Microwave Lecturer (2020–2023) 2013 Schelkunoff Prize Paper Award Advising & Grants: Advised over 30 PhD/master's students and led projects funded by NSF, DARPA, Intel, SRC, and industry partnerships. Key grants include NSF CAREER (2008), ONR Young Investigator (2006), and multiple industry-sponsored initiatives. Labs & Teams: Rapid-HI Design Institute (DARPA NGMM) Quantum device co-design group Multiphysics modeling team

Austin Rovinskiمشاهده پروفایل

استادیار

• Computer Architecture
• VLSI
• Electronic Design Automation (EDA)
• +۵ مورد دیگر

Austin Rovinski is an Assistant Professor in the Department of Electrical and Computer Engineering at New York University’s Tandon School of Engineering. He specializes in chip design, electronic design automation (EDA), and open-source hardware methodologies. His research focuses on VLSI design, domain-specific accelerators, and chiplet-based systems. Prior to NYU, he held a postdoctoral position at Cornell University and earned all his degrees (Ph.D., M.S., and B.S.) from the University of Michigan. Education: Ph.D., Electrical Engineering, University of Michigan - Ann Arbor Master’s, Electrical Engineering, University of Michigan - Ann Arbor Bachelor’s, Electrical Engineering, University of Michigan - Ann Arbor Research Focus: Developing open-source EDA frameworks like OpenROAD Optoelectronic interconnect systems for 2.5D packaging Agile hardware design methodologies Reconfigurable sparse matrix accelerators RISC-V-based manycore processors (e.g., Celerity project) Key Contributions: Austin led the development of the OpenROAD RTL-to-GDS flow and contributed to the Sirius and Celerity projects. His work emphasizes reproducibility, democratizing chip design through open-source tools. Awards: IEEE Micro Top Picks (2015) Michigan EECS Outstanding Research Award (2016) NSF Graduate Research Fellowship Honorable Mention (2017, 2018) Advising & Grants: Actively mentors graduate students in chip design and EDA. His research is supported by NYU’s Tandon School of Engineering and collaborations with industry partners. Labs & Teams: Core contributor to the OpenROAD project, part of NYU’s hardware design and EDA initiatives, and collaborator on the Celerity manycore processor project.

• Machine Learning in Electronics
• Electrostatic Discharge (ESD) Protection
• Circuit Reliability
• +۳ مورد دیگر

Elyse Rosenbaum is the Melvin and Anne Louise Hassebrock Professor in Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. She also serves as the Acting Associate Dean for Research at the Grainger College of Engineering. She is the director of the NSF-supported Center for Advanced Electronics through Machine Learning (CAEML), a collaboration between the University of Illinois, North Carolina State University, and Penn State University. Education: Ph.D. in Electrical Engineering, University of California, Berkeley, 1992 M.S. in Electrical Engineering, Stanford University B.S. in Electrical Engineering, Cornell University (with distinction) Research Interests: Her research focuses on machine learning applications in electronics, ESD-robust high-speed I/O circuit design, compact modeling, behavioral modeling of circuits, and CDM-ESD protection for advanced packaging technologies. Scientific Awards: IEEE Fellow for contributions to electrostatic discharge reliability of integrated circuits Best Student Paper Award, IEDM Outstanding and Best Paper Awards, EOS/ESD Symposium Technical Excellence Award, SRC NSF CAREER Award IBM Faculty Award ESD Association’s Industry Pioneer Recognition Award Advising and Grants: She supervises graduate and undergraduate researchers, primarily focusing on those with strong academic records and relevant experience. Her work is supported by NSF and other prominent organizations. Labs and Teams: She leads the CAEML center, which aims to apply machine learning to optimize microelectronic circuits and systems, enhancing design automation and reliability.

Muhannad S. Bakirمشاهده پروفایل

استاد

• Heterogeneous Integration
• Electrical and Photonic Interconnects
• Thermal Modeling for Electronics
• +۳ مورد دیگر

Muhannad S. Bakir is the Dan Fielder Professor in the School of Electrical and Computer Engineering at Georgia Institute of Technology, and Director of the 3D Systems Packaging Research Center . His research focuses on heterogeneous integration , electrical/photonic interconnects , thermal modeling , and electronics for healthcare , with over 180 publications and 12 U.S. patents. Research areas include: Advanced cooling and power delivery for emerging systems Biosensor-CMOS integration 2.5D/3D IC packaging Polylithic integration technology Nanofabrication for microsystems Scientific accolades include: 2018 IEEE EPS Exceptional Technical Achievement Award 2013 Intel Early Career Faculty Honor Award 2012 DARPA Young Faculty Award 2011 IEEE CPMT Outstanding Young Engineer Award Best paper awards at IEEE ECTC, IITC, and CICC 2020 Georgia Tech Doctoral Thesis Advisor Award His lab explores integrated 3D systems with emphasis on co-design of thermal, power, and electrical networks for machine learning and healthcare applications.

David Wentzlaffمشاهده پروفایل

استاد

• Computer Architecture
• Green Computing
• Cloud Computing
• +۶ مورد دیگر

David Wentzlaff is a Professor of Electrical and Computer Engineering at Princeton University, with associated faculty roles in Computer Science and the High Meadows Environmental Institute (HMEI). He leads research in computing architecture, green computing, and sustainable system design. As Director of Undergraduate Studies, he shapes educational programs in his field. Education: Ph.D., Electrical Engineering, MIT (2012) M.S., Electrical Engineering and Computer Science, MIT (2002) B.S., Electrical Engineering, University of Illinois at Urbana-Champaign (2000) Research Focus: Future Computing Systems: Designing manycore architectures, cloud computing infrastructure, and chiplet-based systems for exascale computing. Sustainability: Developing energy-efficient hardware, recyclable computing systems, and eco-friendly decommissioning strategies. Hardware-Software Co-Design: Exploring FPGA integration, in-memory computing, and parallel processing frameworks. Advising & Grants: Advises 8 current graduate students, focusing on topics like chiplet design, neural acceleration, and sustainable computing. Recipient of NSF grants for projects like OpenPiton (open-source manycore research platform) and CAREER awards for energy-efficient architectures. Labs & Collaborations: Leads the Wentzlaff Research Group at Princeton. Develops open-source frameworks like PRGA (FPGA prototyping) and OpenPiton (manycore processor).

Jeff Zhangمشاهده پروفایل

استادیار

• Deep learning
• Computer architecture
• Embedded systems
• +۵ مورد دیگر

Jeff Zhang is an Assistant Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University. He joined ASU in January 2023 after completing a postdoctoral fellowship at Harvard University. His research spans deep learning, computer architecture, embedded systems, and EDA, with particular emphasis on energy-efficient and fault-tolerant design for AI/ML systems and hardware accelerators. Education: Ph.D., New York University M.Eng., B.Eng., Hunan University Dr. Zhang's research bridges theoretical machine learning with practical hardware implementation, developing novel architectures that optimize performance, power consumption, and reliability. He has pioneered approaches for hardware acceleration of large language models, efficient sparse matrix operations, and novel memory technologies for AI workloads. His work has received multiple awards including IEEE Top Picks in Test and Reliability (2023) and IEEE Micro Best Paper Award (2022). His recent publications demonstrate a strong trend toward heterogeneous computing, with significant work in chiplet-based AI accelerators, photonic computing for AI, and 2.5D/3D integration techniques. The research spans from high-level compiler frameworks to circuit-level innovations, with a consistent theme of co-designing algorithms and hardware for optimal AI performance. His work on the SODA toolchain has been particularly influential in bridging Python to silicon. Scientific Awards: IEEE Top Picks in Test and Reliability, IEEE ITC, 2023 Best Paper Award, IEEE Micro, 2022 Best Paper Award Candidate, IEEE DATE, 2022 Best Presentation Award Nomination, ACM SIGDA DATE PhD Forum, 2020 Best Paper Award Nomination, IEEE VLSI Test Symposium, 2018 Ernst Weber Ph.D. Fellowship, New York University, 2015, 2016 Dr. Zhang actively mentors a diverse group of graduate and undergraduate students, with several alumni now working at leading technology companies including Apple, TSMC, and Ansys. His research is supported by prestigious grants from NSF, Sandia National Labs, and industry partners. He serves on technical program committees of numerous top conferences and has organized special sessions on emerging topics like Gen AI for Chip Design and LLM-Aided Design. Dr. Zhang leads a vibrant research group that collaborates extensively with industry partners and national laboratories. Current projects focus on next-generation AI hardware, including chiplet-based systems, photonic accelerators, and novel memory technologies for large language models. His group has developed several open-source tools and frameworks, including the SODA toolchain for bridging Python to silicon.

Kimia Zamiri Azarمشاهده پروفایل

استادیار

• Hardware Security
• Verification Formal Methods
• Advanced VLSI Testing
• +۳ مورد دیگر

Kimia Zamiri Azar serves as an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Central Florida, focusing on hardware security and verification methodologies. Her research bridges theoretical formal methods with practical security implementations in semiconductor design and testing. Her educational background includes: Ph.D. in Electrical and Computer Engineering, George Mason University (2021) Postdoctoral Research, University of Florida Dr. Azar's research spans hardware security with emphasis on system-level verification, VLSI design-for-trust, and advanced IC testing. She pioneers techniques in logic locking, secure heterogeneous integration, and IC supply chain security, developing frameworks for authenticated encryption in Systems-in-Package and runtime security monitoring. Her work integrates formal verification with innovative testing methodologies to address hardware trust challenges across the semiconductor lifecycle. Analysis of her recent publications reveals two dominant trends: (1) Application of large language models (LLMs) to hardware design tasks including high-level synthesis code generation and RTL optimization, and (2) Advancement of secure heterogeneous integration techniques for System-in-Package architectures with focus on counterfeit prevention and split-test security protocols. These directions address critical gaps in hardware trustworthiness amid increasingly complex semiconductor supply chains. Her scientific contributions have earned significant recognition: Best Paper Award at ICCAD 2019 Best Paper Award at ISVLSI 2020 Best Paper Award at ICCAD 2020 Best Paper Award at IEEE DCAS 2020 Best Paper Award at HOST 2022 Best Paper Award at DATE 2023 Dr. Azar secures substantial research funding from premier agencies including NSF, SRC, DARPA, AFRL, DoD (NG), and Microsemi. Her grants support projects spanning hardware security validation frameworks, secure heterogeneous integration, and AI-augmented verification methodologies. She actively mentors students in her research group, guiding publications in top venues like IEEE D&T, IEEE TC, and DAC while fostering industry-academic collaborations. Her work directly impacts semiconductor security standards through patented innovations and open-source verification tools. As an active IEEE and ACM member, she contributes to community advancement through conference organization (HOST, DATE), journal editorial roles, and workshop leadership on hardware security standards. Her research group collaborates with semiconductor industry leaders to translate theoretical security frameworks into practical design-for-trust methodologies for next-generation integrated circuits.

Nikos Hardavellasمشاهده پروفایل

استاد

• Computer Architecture
• Quantum Computing Systems
• Parallel Systems
• +۴ مورد دیگر

Nikos Hardavellas is a Professor of Computer Science and Electrical and Computer Engineering at Northwestern University, affiliated with the McCormick School of Engineering. He leads the Parallel Architecture Group at Northwestern (PARAG@N), focusing on energy-efficient parallel computing and quantum systems. His research spans quantum computing systems, fault-tolerant quantum error management, memory-centric architectures, and photonics-based interconnects. Education: Ph.D. Computer Science, Carnegie Mellon University (2009) M.S. Computer Science, Carnegie Mellon University (2006) M.S. Computer Science, University of Rochester (1997) B.S. Computer Science, University of Crete (1995) Research Interests: Quantum system software stack and error mitigation Memory-centric computing and programmable memory systems Energy-efficient architectures and dark silicon Photonics and optical interconnects Parallel systems and compiler-hardware co-design Key Contributions: Developed SupermarQ, a scalable quantum benchmark suite Pioneered optical cache hierarchies (Pho$) and energy-proportional photonic networks Advanced compiler-driven virtual memory systems (CARAT) and MPI autotuning (ACCLAiM) Awards & Honors: NSF CAREER Award (2015) Future CRA Leader (2024) Best Paper Awards at HPCA (2022) and ISLPED (2021 nomination) Test-of-Time Award at EDBT (2019) Grants & Service: Secured $4.8M in research funding from NSF, industry partners, and university initiatives Executive Committee member of Northwestern’s INQUIRE Institute for Quantum Research General Co-chair of IEEE/ACM MICRO 2022 Extensive service on departmental committees and thesis advisory boards Labs & Teams: Directs PARAG@N, collaborating on quantum computing, photonics, and energy-efficient architectures. Engages with industry partners like AMD, Intel, and Synopsys.

Pasquale Davide Schiavoneمشاهده پروفایل

مدرس

• Embedded Systems
• RISC-V Architecture
• Ultra-low-power Computing
• +۵ مورد دیگر

Pasquale Davide Schiavone holds multiple research and teaching positions at École Polytechnique Fédérale de Lausanne (EPFL), serving as a Lecturer at the School of Computer and Communication Sciences (IC) and as a Scientist at both the Embedded Systems Laboratory (ESL) within the School of Engineering (STI) and PAT Administration. His interdisciplinary work bridges computer architecture, embedded systems design, and biomedical applications, with office located at ELG 136 in Lausanne, Switzerland. Dr. Schiavone's research focuses on ultra-low-power computing systems, particularly RISC-V architectures and TinyML applications for edge devices. His work develops open-source hardware platforms like X-HEEP and HEEPOCRATES that enable energy-efficient AI at the edge, with applications spanning biomedical monitoring, neural interfaces, and wearable computing. He explores innovative hardware-software co-design approaches to overcome energy constraints in resource-limited environments. His recent publications reveal a consistent research trajectory centered on open, configurable computing platforms for specialized applications. The work spans from fundamental RISC-V architecture improvements (ARCANE, e-GPU) to application-specific implementations for biomedical contexts (BiomedBench, neural interfaces). A strong emphasis on energy efficiency permeates all his research, whether through novel arithmetic approaches (Posit), system architecture (near-memory computing), or specialized accelerators (Strela, Quadrilatero). Lecturer, School of Computer and Communication Sciences (IC) Scientist, Embedded Systems Laboratory (ESL), School of Engineering (STI) Scientist, PAT Administration, School of Engineering (STI) Dr. Schiavone teaches courses on hardware compilation, presenting algorithms and methods for transforming hardware description languages into optimized circuit implementations. His Embedded Systems Laboratory work places him at the forefront of developing practical, open-source solutions for next-generation computing challenges in energy-constrained environments.

Fatemeh Ganjiمشاهده پروفایل

استادیار

• Hardware Security
• Cryptography
• Machine Learning
• +۳ مورد دیگر

Fatemeh Ganji is an Assistant Professor in the Department of Electrical & Computer Engineering at Worcester Polytechnic Institute (WPI), with an affiliation to the Cybersecurity program. She holds a Ph.D. in Electrical Engineering from the Technical University of Berlin (2017), where she received the BIMoS Ph.D. Award and was nominated for the ACM Dissertation Award. Prior to WPI, she served as a Post Doctoral Associate at the University of Florida (2018–2020) and at Telecom Innovation Laboratories/Technical University of Berlin (2017–2020). Her research focuses on interdisciplinary approaches in hardware security, combining machine learning and cryptography to design and evaluate security-critical hardware systems. Key areas include physically unclonable functions (PUFs), side-channel analysis, and countermeasures against tampering and counterfeiting. Her work is funded by the European Union (Horizon 2020, FP7), German BMBF, NSF, and NIST. Ganji actively contributes to the academic community as a reviewer for IEEE and ACM journals and serves on technical program committees for CHES, FPL, DATE, and SPACE conferences. Her recent projects include developing AI-driven forensic analysis for PCB tamper detection, secure multiparty computation frameworks for chiplet systems, and open-source tools for implementation security testing. Her awards include the BIMoS Ph.D. Award 2018 and recognition from the Technical University of Berlin for her doctoral work on PUF learnability. She has also pioneered methods to detect recycled integrated circuits and enhance hardware trust through reverse engineering and machine learning.

• Computer Science
• Electrical Engineering
• Machine Learning
• +۴ مورد دیگر

Marian Verhelst is a Professor at KU Leuven's Faculty of Engineering Science, renowned for her research in hardware-efficient computing and dedication to STEM education. Her work spans hardware acceleration for machine learning, edge AI, and in-memory computing, with a focus on energy optimization and algorithm-hardware co-design. Her research interests include: Designing flexible hardware for ultra-low-power edge AI systems Optimizing sparsity-aware architectures for deep learning workloads Advancing chiplet-based and 3D memory technologies Co-designing algorithms and hardware for probabilistic AI Pioneering STEM outreach through KU Leuven InnovationLab Recent publications (2023–2025) demonstrate strong trends in: Hardware-software co-optimization for edge ML systems Efficient data movement in heterogeneous accelerators Low-precision and sparse computation techniques RISC-V based customizable SoCs Sustainable AI accelerator design Awards & Honors: Young Academy of Europe Award (2021) for science communication and STEM advocacy She leads significant educational initiatives, including the KU Leuven InnovationLab which has engaged 150 schools and 13,000 students since 2014. The program develops hands-on STEM projects (e.g., AI-powered wheelchairs, sustainable energy systems) and provides teacher training to inspire youth in engineering.