جست‌وجوی استاد و پژوهشگر

Jan Madsenمشاهده پروفایل

استاد

• Embedded Systems
• Cyber-Physical Systems
• Microfluidic Biochips
• +۵ مورد دیگر

Jan Madsen is a Professor at DTU Compute, Technical University of Denmark, and Head of the Embedded Systems Engineering section. His research focuses on system-level modeling and design of embedded computing systems, particularly cyber-physical systems, microfluidic biochips, and synthetic biology applications. Develops design automation tools and methodologies for embedded systems Supervises numerous PhD students and leads major research projects Research Interests Key areas include: Embedded systems-on-a-chip Cyber-Physical Systems (Internet-of-Things) Microfluidic Lab-on-Chip devices Synthetic biology with molecular computing Design, modeling, and optimization of complex systems Scientific Awards DATE Fellow (2019) IEEE CEDA Outstanding Recognition (2019) DTU Scientific Advise Award (2013) Best Paper Awards at MECO (2013) and CASES (2009) Jorck’s Foundation Research Award (1995) Publications His 14+ journal papers and 115+ conference papers demonstrate expertise in: SystemC-based modeling frameworks Energy-aware sensor networks Self-healing eDNA architectures Microfluidic biochip synthesis RTOS modeling and MPSoC exploration

José F. Martínezمشاهده پروفایل

استاد

• Computer Architecture
• Microprocessor Design
• Multiprocessor and Multicore Architectures
• +۵ مورد دیگر

José F. Martínez holds the Lee Teng-hui Professorship of Engineering at Cornell University's College of Engineering, where he leads research in computer architecture and systems. His roles include Vice Chair of ACM SIGARCH, IEEE Fellow, and past leadership roles in ISCA, MICRO, and IEEE Computer Society journals. He has received prestigious awards such as the NSF CAREER Award, IBM/Qualcomm Faculty Awards, and multiple teaching accolades including Tau Beta Pi Professor of the Year (2011). Education: Licenciado en Informática de Sistemas (1996), Universidad Politécnica de Valencia M.S. (1999) and Ph.D. (2002) in Computer Science, University of Illinois at Urbana-Champaign His research focuses on computer architecture , including microprocessors, multiprocessors, memory subsystems, embedded systems, and processing-in-memory (PIM) innovations. He co-leads the DARPA/SRC ACE Center for Evolvable Computing and NSF's CROPPS Center, and previously co-founded Cornell's Institute for Digital Agriculture (CIDA). His work bridges hardware-software co-design and sustainable computing. Key Contributions: Advancing energy-efficient multiprocessor architectures Developing PIM frameworks like PUMICE and Membrane Market-based resource allocation systems (e.g., XChange, ReBudget) His advising spans over 15 graduate students and has guided Merrill Presidential Scholars. Current research explores evolvable computing paradigms and AI hardware acceleration, reflecting his dual focus on foundational architecture and applied systems innovation.

Morteza Fayaziمشاهده پروفایل

استادیار

• Electronic Design Automation (EDA)
• Machine Learning (ML) in Analog Circuit Design
• System-on-Chip (SoC) Design Automation
• +۳ مورد دیگر

Morteza Fayazi is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Utah, with an adjunct position in the Kahlert School of Computing. His research focuses on Electronic Design Automation (EDA), applying machine learning to automate analog and mixed-signal circuit design, and developing high-performance computing systems. He holds a B.Sc. from Sharif University of Technology, and M.S.E./Ph.D. degrees from the University of Michigan. His research interests include AI-driven EDA, RF/circuit automation, and energy-efficient processors. Key achievements include the MEDAL lab’s work on terahertz radars, systolic-array processors (e.g., DAP and Versa), and open-source frameworks like FASCINET and Tablext. He has received awards such as the 2024 College of Engineering Dean’s ETR Fund and the 2017 Outstanding Undergraduate Thesis Award. Teaching responsibilities include multiple iterations of the Digital System Design course (ECE/CS 3700). His work spans over 15 peer-reviewed articles in IEEE Transactions, ACM, and top conferences like ICCAD and VLSI-SOC, emphasizing automation, efficiency, and AI integration in hardware design.

Ozcan Ozturkمشاهده پروفایل

استاد

• Heterogeneous Computing
• Hardware Accelerators
• GPU Computing
• +۷ مورد دیگر

Ozcan Ozturk is a Professor in the Computer Science and Engineering and Electronics Engineering programs at Sabancı University's Faculty of Engineering and Natural Sciences. Previously, he held professorships at Bilkent University and adjunct roles at North Carolina State University. His expertise spans heterogeneous computing, parallel systems, processor architecture, and compiler optimization. He earned his Ph.D. from Penn State University, with prior academic roles at the University of Florida and internships at Intel and Marvell. Education: Ph.D. in Computer Science and Engineering (2007), Pennsylvania State University M.S. in Computer Engineering (2002), University of Florida B.Sc. in Computer Engineering (2000), Bogazici University Research interests include accelerator technologies, GPU-based systems, multicore processors, and compiler optimizations. His work focuses on improving parallelization efficiency, energy optimization, and reliability in heterogeneous architectures. He leads funded projects like 'Machine Learning for Compiler Flags' and 'Graph Accelerator Design'. Notable awards include the Bilkent Teaching Award (2019), BAGEP (2018), and HiPEAC Paper Award (2016). He serves on editorial boards of IEEE and ACM journals and chairs major conferences like ASPLOS and ICS. Grants and collaborations include partnerships with Huawei, Intel, NVIDIA, and TÜBİTAK. He advises over 20 students and has supervised projects in safety-critical systems, FPGA accelerators, and compiler-directed optimizations. His lab develops domain-specific architectures, including RISC-V extensions for graph processing.

Jiang Huمشاهده پروفایل

استاد

• VLSI Design Automation
• Hardware Security
• Machine Learning Applications
• +۳ مورد دیگر

Jiang Hu is a Professor in the Department of Electrical and Computer Engineering at Texas A&M University, holding the Eric D. Rubin '06 Endowed Professorship. He also serves as Co-Director of Graduate Programs and is affiliated with the Computer Science & Engineering department. His research focuses on VLSI design automation, machine learning applications, and hardware security. He has held roles as editor for IEEE Transactions on CAD and ACM Transactions on Design Automation, and chaired the 2012 ACM International Symposium on Physical Design. Education: B.S. in Optical Engineering (Zhejiang University, 1990), M.S. in Physics (1997), and Ph.D. in Electrical Engineering (University of Minnesota, 2001). He worked at IBM Microelectronics before joining Texas A&M in 2002. Research interests include energy-efficient VLSI circuits, on-chip communication fabrics, analog layout automation, and AI-driven EDA. Recent work emphasizes machine learning for design closure, privacy-preserving frameworks, and systolic array-based architectures. Awards: IEEE Fellow (2016) Humboldt Research Fellowship (2012) Multiple best paper awards at DAC, ICCAD, and ASPDAC Advising and grants: Leads initiatives like the SLICE project, NSF workshops on ML-EDA infrastructure, and serves as Editor-in-Chief of ACM TODAES since 2024. His work bridges academic research and industry applications in EDA and semiconductor design. Labs/Teams: Active contributor to open-source tools like ALIGN for analog layout generation and collaborations on machine learning for EDA commons.

Shantanu Duttمشاهده پروفایل

استاد

• VLSI CAD
• Discrete Optimization
• FPGA Testing and Trusted Design
• +۲ مورد دیگر

Shantanu Dutt is a full Professor in the Department of Electrical and Computer Engineering at the University of Illinois at Chicago , located in Chicago, IL. His office is in 930 SEO at 851 S. Morgan St, and he can be reached at dutt@uic.edu . Education Ph.D. in Computer Science and Engineering, University of Michigan, Ann Arbor (1990) M.Tech. in Computer Engineering, Indian Institute of Technology Kharagpur (1984) B.E. in Electronics and Communication Engineering, Maharaja Sayajirao University of Baroda (1983) Research Interests Professor Dutt’s research agenda centers on VLSI Computer-Aided Design (CAD) , with particular emphasis on physical design and incremental synthesis targeting both ASICs and FPGAs. He explores discrete optimization techniques to solve placement, routing, and partitioning problems. Another major thrust is FPGA built-in self-test (BIST) and trusted design , ensuring provable diagnosability and security against hardware Trojans. He also investigates fault-tolerant computing at both chip and system levels, and develops parallel and distributed computing algorithms for scalable performance. Scientific Awards 1996 Best Paper Award , ACM/IEEE Design Automation Conference, for “A probability-based approach to VLSI circuit partitioning” 1995 Most Influential Paper Award , Fault-Tolerant Computing Symposium, for “Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architectures” Research Impact and Funding Professor Dutt has published extensively in top-tier journals (IEEE TVLSI, ACM TRETS, IEEE TCAD) and premier conferences (ICCAD, DAC, DATE, FTCS). His work has shaped incremental placement, timing-driven routing, FPGA security, and fault-tolerant multiprocessor architectures. While specific grant numbers are not listed, the breadth and longevity of his publication record indicate sustained funding from NSF, industry, and other agencies. Laboratory and Collaborations Although no formal laboratory name is provided, Professor Dutt’s research is conducted within the ECE department’s VLSI CAD and Fault-Tolerance groups, collaborating with graduate students and colleagues across the US and internationally.

Stephen W. Kecklerمشاهده پروفایل

استاد مدعو

• Computer Architecture
• Deep Learning Accelerators
• GPU Computing
• +۴ مورد دیگر

Stephen W. Keckler is an Adjunct Professor at the Department of Computer Science , The University of Texas at Austin , and serves as Vice President of Architecture Research at NVIDIA . He is an ACM Fellow , IEEE Fellow , and Sloan Foundation Research Fellow . Education: BS in Electrical Engineering, Stanford University (1990) SM in Computer Science, Massachusetts Institute of Technology (1992) PhD in Computer Science, MIT (1998) Research Interests focus on computer architecture for deep learning , GPU computing , and energy-efficient systems . His work explores memory compression , network-on-chip designs , and heterogeneous computing . Publication Trends highlight advancements in deep learning accelerators , GPU memory systems , and energy-efficient architectures . Notable themes include sparsity exploitation , multi-chip modules , and fault-tolerant GPU pipelines . Scientific Recognition : ACM Fellow IEEE Fellow Sloan Foundation Research Fellow Best Paper Awards at ASPLOS 2009 and ISPASS 2011 Laboratory Affiliations : Computer Architecture and Technology Laboratory (CART) TRIPS Project (Tera-Op Reliable Intelligently adaptive Processing System) NVIDIA Research

Hakan Aydinمشاهده پروفایل

استاد

• Real-Time Embedded Systems
• Sustainable Computing
• Fault Tolerance
• +۴ مورد دیگر

Hakan Aydin is a Professor and Director of the PhD Program in the Department of Computer Science at George Mason University's Volgenau School of Engineering. He has been teaching at George Mason University since 2001 and has established himself as a leading researcher in real-time embedded systems and energy-aware computing. Education: PhD in Computer Science from the University of Pittsburgh (2001) Hakan Aydin's research primarily focuses on sustainable computing, real-time embedded systems, fault tolerance, Internet-of-Things, and cyber-physical systems. His work bridges theoretical foundations with practical implementations, particularly in energy management for real-time systems. He has developed innovative techniques for reliability-aware power management, dynamic voltage scaling, and energy harvesting in wireless sensor networks. His research has significant implications for extending battery life in mobile devices, improving reliability in safety-critical applications, and enabling sustainable computing practices. Aydin's publications reveal a consistent research trajectory centered around energy efficiency and reliability in real-time systems. His work spans theoretical algorithm development, system-level implementation, and experimental validation. A notable trend is the evolution from single-processor systems to multicore and heterogeneous architectures, reflecting industry trends. His recent work increasingly addresses security aspects of real-time systems and the integration of IoT technologies. Scientific Awards: National Science Foundation CAREER Award (2006) George Mason University Computer Science Department Teaching Award (2006, 2009) Best Paper Award at IEEE Green and Sustainable Computing Conference (IGSC'20) Best Student Paper Award at IEEE International Conference on Embedded Software and Systems (ICESS'15) Best Paper Award at IEEE International Conference on Embedded Computing (EmbeddedCom'14) Best Paper Award at International Workshop on Highly-Reliable Power-Efficient Embedded Designs (HARSH'13) Best Paper Award at ACM International Conference on Modeling, Analysis and Simulation of Wireless and Mobile Systems (MSWIM'11) Hakan Aydin has advised seven PhD students to completion, including Vinay Devadas (2011), Baoxian Zhao (2012), Bo Zhang (2012), Mohammad Atiqul Haque (2016), Maryam Bandari (2016), Arda Gumusalan (2019), and Abhishek Roy (2021). His research has been generously supported by the National Science Foundation through multiple grants, including CSR: Small: Collaborative Research: Towards Reliability-Centric Real-time Computing on Heterogeneous Chip Multiprocessor Systems (2014-2017), CSR: Small: Energy Harvesting for Performance Sensitive Wireless Sensor Networks (2011-2015), and CSR: Small: Collaborative Research: Generalized Reliability-Aware Power Management for Real-Time Embedded Systems (2010-2014). Prof. Aydin has held significant leadership roles in the academic community, serving as the Technical Program Committee Chair of the IEEE RTAS 2011 and General Chair of IEEE RTAS 2012. He is also a member of the Editorial Board of Journal of Real-Time Systems (Springer). His work has established foundational principles in reliability-aware energy management for real-time systems, influencing both academic research and industrial practices in embedded computing.

Alaa Alameldeenمشاهده پروفایل

دانشیار

• Computer Architecture
• Memory Systems
• Hardware Security
• +۵ مورد دیگر

Alaa Alameldeen is an Associate Professor in the School of Computing Science at Simon Fraser University (SFU), part of the Faculty of Applied Sciences. Previously, he worked as a Research Scientist at Intel Labs (2006–2020) and held an Adjunct Faculty position at Portland State University (2008–2018). He earned a PhD in Computer Sciences from the University of Wisconsin-Madison (2006), and earlier degrees from Alexandria University, Egypt. His research focuses on computer architecture, including memory systems (processing-in-memory, cache/memory compression, security), energy-efficient architectures, and hardware-software co-design for machine learning. He advises PhD and MSc students in these areas and teaches advanced computing science courses. Key contributions include innovations in memory hierarchies, cache compression techniques, and mitigating hardware vulnerabilities. His work has been published in top conferences (e.g., ISCA, MICRO, HPCA) and patented in areas like near-memory processing and error correction. Alameldeen currently leads a research group exploring secure and high-performance memory architectures. He has supervised multiple graduate students, with many progressing to roles at leading tech companies and academic institutions.

Abdullah Muzahidمشاهده پروفایل

دانشیار

• Computer Architecture
• Systems
• Artificial Intelligence
• +۵ مورد دیگر

Abdullah Muzahid is an Associate Professor in the Department of Computer Science and Engineering at Texas A&M University (since August 2024), previously serving as an Assistant Professor there since August 2018. Prior, he held an Assistant Professor role at the University of Texas at San Antonio (2012-2018). He earned his Ph.D. from the University of Illinois at Urbana-Champaign (2012), focusing on architectural support for debugging concurrency bugs under Prof. Josep Torrellas. Education: Ph.D., Computer Science, University of Illinois at Urbana-Champaign (2012) M.S., Computer Science, University of Illinois at Urbana-Champaign (2009) B.S., Computer Science and Engineering, Bangladesh University of Engineering and Technology (2005) Research Interests: His work spans Computer Architecture , Systems , and Artificial Intelligence , with focus on multiprocessor architecture, parallel programming, debugging, and applying machine learning to system optimization. Recent projects include cache indexing via entropy estimation, DNN training acceleration, and hardware-software co-design for security. Awards: NSF CAREER Award (2017) Excellence in Research Award (UTSA, 2015 & 2017) W. J. Poppelbaum Award (UIUC, 2012) Intel Ph.D. Fellowship (2011) Grants & Advising: He leads NSF-funded projects on robust deep learning and stream processing systems. Advised 5 PhD graduates and currently mentors 4 PhD students. Served on program committees for ISCA, HPCA, MICRO, and as NSF panelist. Labs/Teams: Active in Texas A&M’s Computer Architecture group, collaborating on machine programming, hardware security, and AI-driven systems optimization.

Manolis G.H. Katevenisمشاهده پروفایل

استاد

• Computer Architecture
• VLSI Systems
• Interconnection Network Architecture
• +۴ مورد دیگر

Manolis G.H. Katevenis is a Professor at the Department of Computer Science, University of Crete, and Deputy Director and Head of the Computer Architecture and VLSI Systems (CARV) Laboratory at the Institute of Computer Science (ICS), Foundation for Research & Technology - Hellas (FORTH). He co-founded the European Research Center on Computer Architecture (EuReCCA) and is a founding partner of the European Network of Excellence on High-Performance and Embedded Architecture and Compilation (HiPEAC). PhD in Computer Science from University of California, Berkeley (1983) Co-founder of EuReCCA (2011) Contributed to RISC architecture (1980-1983), interconnection networks (1985-2011), and parallel computing (1993-2010) His research spans Scalable Multicore Systems , Interconnection Network Architecture , Packet Switch Design , Computer Architecture , and VLSI Systems . He has made foundational contributions to per-flow queueing, backpressure mechanisms, and wormhole IP over ATM, with applications in internet routers, data centers, and supercomputers. His publications focus on high-radix crossbar switches, flow control algorithms, and explicit interprocessor communication. Notable scientific awards include: ACM Doctoral Dissertation Award (1984) David J. Sakrison Memorial Prize (1983) IBM PhD Fellowship (1981-1983) Greek State Fellowship (1973-1978) He has supervised 40 graduate theses and participated in 22 R&D projects totaling €9M, including HiPEAC (coordinator of interconnection networks), SARC (FPGA prototype design), and ENCORE (cache-optimized remote DMA). His work has received over 2000 citations, with an h-index of 23.

John D. Kubiatowiczمشاهده پروفایل

استاد

• Computer Architecture
• Quantum Computing
• Distributed Systems
• +۷ مورد دیگر

Professor John D. Kubiatowicz is a faculty member at the University of California at Berkeley in the Department of Electrical Engineering and Computer Sciences since 1998. He holds a PhD in Electrical Engineering and Computer Science (minor in Physics) from MIT (1998), an M.S. in EECS (1993), and a double B.S. in Electrical Engineering and Physics (1987) from MIT. His research interests span Quantum Computing Architectures Distributed Systems and Storage Network Security and Peer-to-Peer Protocols Introspective and Manycore Operating Systems Edge and Fog Computing Hardware-Assisted Security He has pioneered systems like OceanStore , a global-scale distributed file system, and Tessellation , a manycore OS with continuous adaptation. The scientific awards he has received include Presidential Early Career Award (PECASE, 2000) Scientific American 50 (2002) Diane S. McEntyre Teaching Award (2003) IEEE ICRA Best Paper (2025) George M. Sprowls Award for MIT PhD thesis (1998) Okawa Research Grant (1998) Best Paper at International Conference on Supercomputing (1993) His recent publications focus on Quantum Circuit Design and Optimization Edge/Fog Computing Architectures Secure Runtime Systems Distributed Garbage Collection Manycore OS Innovations Hardware-Assisted Security Mechanisms He leads the Quantum Architecture Research Center and co-founded the SWARM Lab at Berkeley, advancing a vision of self-adapting, secure systems from the chip level to internet scale.

Peter Suttonمشاهده پروفایل

دانشیار

• Engineering Education
• Embedded Computing Systems
• Reconfigurable Computing
• +۳ مورد دیگر

Associate Professor Peter Sutton is an academic at the University of Queensland (UQ), holding roles as Deputy Head of School (Teaching and Learning) and Associate Professor in the School of Electrical Engineering and Computer Science. His research focuses on Engineering Education, Embedded Systems, Reconfigurable Computing, and Electronic Design Automation. He has contributed to curriculum design, remote lab management during the pandemic, and hardware-software co-design for embedded systems. Sutton completed his undergraduate studies at UQ and earned advanced degrees at Carnegie Mellon University, with over three decades of experience in computer systems research and education. Education Bachelor of Science, University of Queensland Bachelor (Honours) of Engineering, University of Queensland Masters of Science (Coursework), Carnegie Mellon University Doctor of Philosophy, Carnegie Mellon University Research Interests Sutton’s work spans engineering pedagogy, embedded system design, and reconfigurable computing. Recent projects include adapting hands-on labs for remote learning during the pandemic and optimizing FPGA-based architectures for data compression and encryption. His contributions to cache optimization and multiprocessor systems highlight his expertise in hardware-software integration. Publications His 50+ publications cover topics like FPGA implementations of neural networks, code compression techniques for VLIW processors, and embedded system design tools. Notable contributions include frameworks for reconfigurable system-on-chip development and methods to enhance debugging practices in post-novice students. Labs & Teams He collaborates within UQ’s School of Electrical Engineering and Computer Science, contributing to research groups focused on embedded systems and engineering education innovation.

David Andrewsمشاهده پروفایل

استاد

• Embedded Systems
• Computer Architecture
• Reconfigurable Computing
• +۵ مورد دیگر

David Andrews is a Professor in the Department of Computer Science and Computer Engineering at the University of Arkansas College of Engineering. He holds the Mullins Endowed Chair of Computer Engineering and directs research through the Computer Systems Design Laboratory (CSDL). His work bridges hardware and software systems with a focus on practical implementation. His educational background includes: Ph.D. in Computer Engineering from Syracuse University Computer Engineer Degree from Syracuse University M.S.E.E. from University of Missouri-Columbia B.S.E.E. from University of Missouri-Columbia Andrews' research centers on embedded systems architectures from a holistic systems perspective, examining interactions between programming languages, runtime systems, and hardware components. His work spans reconfigurable computing, FPGA-based acceleration, and hybrid CPU/FPGA systems. A key contribution is the HybridThreads (hthreads) platform, which abstracts hardware/software boundaries to enable thread-based programming for heterogeneous systems. Recent publications demonstrate his focus on accelerating machine learning workloads on FPGAs, particularly transformer models and attention mechanisms, while addressing resource scheduling and real-time constraints. His publication trends reveal a consistent evolution from foundational work in parallel and distributed embedded systems toward specialized hardware acceleration for modern AI workloads. The research increasingly focuses on memory-centric architectures, computational overlays, and practical implementations for real-time applications across diverse domains including cultural heritage documentation and cybersecurity. As director of the Computer Systems Design Laboratory, Andrews leads interdisciplinary research in real-time embedded systems, reconfigurable computing, multiprocessor systems on chip, and hardware/software co-design. The lab integrates knowledge into undergraduate and graduate curricula covering digital design, computer organization, embedded systems, and systems modeling. CSDL supports a collaborative environment with undergraduate, master's, and PhD students working alongside visiting researchers from global institutions.

Joshua San Miguelمشاهده پروفایل

دانشیار

• Approximate computing
• Processor microarchitecture
• Intermittent computing
• +۴ مورد دیگر

Associate Professor Joshua San Miguel leads research in computer architecture and systems at the University of Wisconsin-Madison, with an affiliate role in Computer Sciences. His work focuses on energy-efficient computing for IoT devices, microarchitecture innovations, and networks-on-chip. He holds a PhD (2017) and BASc (2012) from the University of Toronto. Education: PhD in Electrical & Computer Engineering, University of Toronto (2017) BASc in Engineering Science (ECE), University of Toronto (2012) Research Interests: Approximate computing for energy harvesting systems Branch prediction and value prediction in processors Cache architectures and networks-on-chip for many-core processors Intermittent computing resilience His recent work emphasizes value-level parallelism (Carat/uSystolic), RTL simulation acceleration (TaroRTL), and personalized neural network inference (CAP’NN). His research has been recognized with the NSF CAREER Award (2021) and multiple IEEE Micro Top Picks. Grants & Advising: Active in supervising advanced independent studies and master’s/dissertation research. Extensive grant funding includes the NSF CAREER Award and the Grainger Faculty Scholarship. Labs & Teams: Leads research groups focused on approximate computing and energy-efficient architectures within the Electrical & Computer Engineering department.