Foivos Zakkak is a Software Engineer at Red Hat’s Java platform team, focusing on Mandrel, GraalVM, and Quarkus. Previously, he held academic roles including Research Associate and Research Software Engineer at the Advanced Processor Technologies (APT) group at the University of Manchester, and Postdoctoral Researcher at the Computer Architecture and VLSI Systems Laboratory (CARV) of FORTH-ICS. He holds a PhD, MSc, and BSc in Computer Science from the University of Crete. His research interests center around Process Virtual Machines, Managed Runtime Systems, Garbage Collection, and Systems Software. Key projects include leading the Maxine VM (a metacircular Java-in-Java VM), developing DiSquawk (a JVM for non-cache-coherent architectures), and contributions to task-based runtime systems like TPC, BDDT, and PARTEE. His work spans optimizing managed applications for NUMA architectures and reducing memory pressure in big data frameworks. Publications include studies on NUMA system performance, memory analysis of Java benchmarks, and JIT compilation on ARM architectures. His technical expertise extends to system software development and performance engineering.
Freek Verbeek is an Assistant Professor at Virginia Tech, affiliated with the Systems Software Research Group led by Prof. Binoy Ravindran. He holds a PhD focused on Networks-On-Chips (NoCs) and specializes in applying formal verification methods to complex systems. Verbeek maintains additional connections to the Open University of the Netherlands through collaborative research projects. His research focuses on: Formal verification of security properties in industrial systems (PikeOS separation kernel) Deadlock/livelock prevention in Networks-on-Chips and cache coherent architectures Bottom-up binary verification and decompilation techniques Theorem proving using Isabelle/HOL and ACL2 systems Development of verification tools (DCI2, ADVOCAT, WickedXmas) His publication trend analysis reveals concentrated work in: Binary analysis and decompilation verification (2020) Formal methods for hardware verification (2016-2019) Network-on-Chip deadlock analysis (2013-2017) Security kernel verification (2014-2015) He received the Best Paper Award at SEFM 2020 for work on binary decompilation. Verbeek leads research in decompilation tools and verification frameworks, currently seeking PhD students and postdocs for formal methods and reverse engineering projects. He collaborates with both Virginia Tech and the Open University of the Netherlands on binary analysis research.
Dr. John Wickerson is a Senior Lecturer in the Department of Electrical and Electronic Engineering at Imperial College London. His research focuses on enhancing the reliability of high-performance computing through formal methods, particularly in the context of concurrent systems, weak memory models, and hardware synthesis. Imperial College London IEEE Senior Member ACM Member Research interests include: Concurrency semantics and weak memory models Formal verification of high-level synthesis tools Transactional memory and cache coherence GPU and FPGA programming Separation logic for hardware-software interfaces Recent publications analyze the interaction between transactional memory and out-of-order execution, formalize cache coherence protocols like CXL, and develop automated testing frameworks for hardware synthesis tools. His work bridges theoretical computer science and practical engineering across domains like quantum compiler validation (QuteFuzz), database isolation level verification (EuroSys 2024 Best Paper), and Verilog parser robustness (TOSEM 2025). Scientific recognition includes: Best Paper at EuroSys 2024 Distinguished Artifact at ESOP 2022 Michal Servit Best Paper Finalist at FPL 2022 Runner-up Best Paper at FCCM 2018 He advises PhD students in formal verification and hardware synthesis, including Quentin Corradi and Michalis Pardalos. His team has produced groundbreaking work on memory persistency models (ICSE-NIER 2024) and GPU workgroup progress (OOPSLA 2015-2024). The group maintains active collaborations with institutions like EPFL, Cambridge, and Edinburgh.
Mark Greenstreet is a Professor in the Department of Computer Science at the University of British Columbia. He specializes in formal verification, VLSI design, and analog/mixed-signal (AMS) circuit analysis. His research includes developing tools like PReach (a parallel model checker) and COHO (reachability analysis), with applications in cyber-physical systems and energy-efficient computation. He holds affiliations with the Institute for Computing, Information, and Cognitive Systems (ICICS). Research Focus: Formal verification of hardware/software systems, model checking, analog circuit verification, energy-time trade-offs in VLSI, and theorem-proving integration with SMT solvers. His work bridges theoretical mathematics and practical circuit design, addressing challenges in reliability, scalability, and performance. Awards & Recognition: Recipient of Best Paper Awards at ASYNC 2011 and ASYNC 2003 for contributions to synchronizer analysis and self-timed interfaces. His research is supported by NSERC, Intel, and Oracle. Supervision & Teaching: Supervised over 20 graduate students, focusing on formal methods, parallel computing, and verification. Teaches courses on parallel computation, formal verification, and computer architecture. Labs & Tools: Developed PReach and COHO as open-source verification tools. Active in research groups exploring analog circuit modeling, reachability analysis, and hybrid systems verification.
Tanvir Ahmed Khan is an Assistant Professor at Columbia University, specializing in computer architecture and systems. His research focuses on enabling efficient data center processing through hardware-software co-design, particularly in instruction and data caching, branch prediction, and profile-guided optimizations. His work has been adopted by industry leaders like Intel and ARM, and recognized with awards such as the MICRO 2022 Best Paper Award and the ACM SIGARCH/IEEE CS TCCA Outstanding Dissertation Award. He holds a PhD from the University of Michigan, where he previously conducted research on techniques like I-SPY, DMon, and Ripple. His current projects aim to address bottlenecks in data center applications by leveraging repetitive execution patterns for predictive optimizations. Khan has mentored numerous students, including Kan Zhu (first place in MICRO 2022 SRC) and Yuxuan Zhang (first author of OCOLOS). His service roles include program committee memberships for ISCA, MICRO, and CGO, reflecting his influence in the field. Key achievements include the Rackham Predoctoral Fellowship, Qualcomm Innovation Fellowship finalist status, and multiple SRC Best Paper awards.
John L. Hennessy is a renowned computer scientist and former President of Stanford University (2000–2016). As a professor of Electrical Engineering and Computer Science since 1977, he pioneered RISC architecture and co-founded MIPS Computer Systems and Atheros Communications. He currently serves as the Shriram Family Director of the Knight-Hennessy Scholars program and chairs Alphabet’s board. His leadership revitalized Stanford’s financial aid and arts programs, and his research contributions include seminal work in computer architecture and parallel processing. Education: Bachelor’s in Electrical Engineering from Villanova University (1973) Master’s and Ph.D. in Computer Science from Stony Brook University (1975–1977) Hennessy’s research interests span computer architecture, RISC technology, and high-performance computing. He co-authored landmark textbooks Computer Architecture: A Quantitative Approach and Computer Organization and Design , which are industry standards. His leadership roles include Dean of Engineering, Provost, and President at Stanford, and board memberships at Alphabet and the Gordon and Betty Moore Foundation. His articles and books focus on multiprocessor systems, cache coherence, and hardware-software co-design, reflecting his deep impact on both academia and industry. Key awards include the ACM Turing Prize (2017), IEEE Medal of Honor (2012), and the Vannevar Bush Award (2024). Grants & Leadership: Launched Knight-Hennessy Scholars, the world’s largest graduate fellowship program Directed Stanford’s growth in interdisciplinary research and accessibility initiatives Hennessy’s legacy combines technical innovation with transformative leadership in higher education.
Professor Nikitas J. Dimopoulos is a Professor and Lansdowne Chair in Computer Engineering at the University of Victoria, Department of Electrical and Computer Engineering. He joined the university in 1988 and has held academic positions at Concordia University. His research focuses on computer architecture, parallel systems, neural networks, fault detection, and power-aware systems. He received his BSc from the National and Kapodistrian University of Athens, and MSc/PhD from the University of Maryland. Research Interests: His work spans multicomputer systems, interconnection networks, neural networks applications, and grid computing. Specific areas include latency reduction in message passing, resource allocation in grids, and fault detection in communication networks. He has contributed to hardware design, VLSI optimization, and parallel processing architectures. Publications Overview: Over 100 peer-reviewed articles, focusing on topics like knapsack-based scheduling, direct-to-cache transfer techniques, and neural network applications. Key contributions include work on hypercycle-based interconnection networks and grid resource management. Advising & Grants: Supervised over 30 graduate students, with notable alumni in academia and industry. His grants include projects on cable network fault detection funded by Canadian Cable Labs. He edited volumes on embedded architectures and high-performance computing. Labs/Teams: Leads research groups in parallel computing and networked systems, collaborating with industry partners like Intel and Rogers Cable Systems.
Adria Armejach Sanosa is a Senior Lecturer in the Department of Computer Architecture at the Faculty of Computer Science of Barcelona (FIB), Universitat Politècnica de Catalunya (UPC). He is also affiliated with the Barcelona Supercomputing Center (BSC-CNS), a leading institution in high-performance computing in Europe. His research spans computer architecture, high-performance computing, memory systems, and hardware acceleration for genomics and machine learning. PhD from UPC His research interests focus on optimizing computer systems for performance and efficiency, particularly in the areas of hardware transactional memory, cache optimization, RISC-V architectures, and acceleration of bioinformatics workloads. He investigates how to improve data movement, prefetching, and parallelism in large-scale heterogeneous systems. His work combines architectural innovations with practical implementations on real-world HPC platforms. The most recent articles reflect a strong trend towards high-performance computing for genomics, sparse data handling, and efficient hardware/software co-design. Topics include genomics benchmarking on ARM processors, tensor marshaling, RTL simulation scalability, and low-precision training for deep neural networks. These works demonstrate a consistent focus on bridging architectural research with real-world applications in science and AI. HiPEAC Paper Award 2024 HiPEAC Paper Award Armejach has advised several doctoral students, including J. Pavón, G. López, and J. Osorio. He has been involved in numerous competitive R&D+i projects such as Digital Autonomy for RISC-V in Europe, Laboratorio Zettaescala de Barcelona, and Genome Analysis Acceleration on HPC Architectures. These projects are often funded by national and European programs, indicating strong recognition and support for his research. He collaborates extensively within the CAP (High-Performance Computing) research group and with key figures like Miquel Moreto, Mateo Valero, and Osman Unsal. He is a member of the CAP research group and contributes to initiatives like the Laboratory for Open Computer Architecture and systems (RISC-V Chip Development) and the Barcelona Zettascale Lab. These labs focus on open hardware, European technology sovereignty, and next-generation supercomputing. His work on Metro-MPI for RTL simulation and hardware accelerators for databases highlights his contributions to both design automation and data-intensive computing.
Andrés Goens is an Assistant Professor at the University of Amsterdam since 2023. He holds a Ph.D. (Dr.rer.nat.) in Computer Science from TU Dresden (2021) and an M.Sc. in Mathematics from RWTH Aachen University (2014). His research focuses on programming languages, formal methods, and theorem proving, with applications to compilers and heterogeneous systems. He investigates efficient execution of concurrent programs in multicore architectures and explores machine learning techniques for compiler optimization. Key research areas include concurrency, weak memory models, and bridging abstract mathematics with practical compiler design. His work often employs theorem provers like Lean to formalize program behavior. Recent publications address e-graphs for variable handling, guided equality saturation, and optimizing virtual networks in distributed systems. Publications span venues like PLDI, POPL, and ISCA, reflecting contributions to programming language theory and compiler infrastructure. His research bridges theoretical foundations with practical system design, aiming to improve both programmer productivity and computational efficiency. Contact details: a.goens@uva.nl (professional) and andres@goens.org (personal).
Ryan Stutsman is an Associate Professor at the University of Utah, leading the Scalable Software Systems Lab within the School of Computing. His research focuses on Distributed Systems, Operating Systems, and Databases, with an emphasis on high-performance storage and low-latency systems. He holds a Ph.D. from Stanford University and was a Postdoctoral Researcher at Microsoft Research. Notable accolades include the NSF CAREER Award (2018) and PECASE Award (2025). He has contributed to projects like NrOS (a multikernel OS), Splinter (multi-tenant storage), and RAMCloud (distributed key-value storage). His work frequently addresses challenges in cloud computing, in-memory databases, and system scalability. Education: Ph.D., Stanford University (2013); Postdoc, Microsoft Research Teaching: Award-winning instructor for courses like Distributed Systems, Advanced Operating Systems, and Computer Networks Labs/Teams: Scalable Software Systems Lab His recent publications explore serverless scheduling, storage functions, and persistent memory systems. He has held leadership roles in conferences such as USENIX ATC and OSDI, and serves on NSF panels.
Dr. Jakub Yaghob is a researcher at the Faculty of Mathematics and Physics , Charles University , specializing in computer science and parallel computing. He teaches advanced programming topics including Compiler Principles , Parallel Programming , and Cloud Computing . Research Interests : Parallel data stream processing, virtualization technologies, semantic web infrastructures, and performance optimization Teaching : Advanced C++ programming, virtualization administration, and computer systems architecture Technical Expertise : Design of parallelization frameworks, astrophysical data analysis, and hybrid CPU-GPU systems His publications focus on: Optimizing stream data processing across distributed architectures Developing domain-specific languages like Bobolang Performance evaluation in educational programming contexts Applications of parallel computing in astrophysics
Yufei Ding is an Associate Professor in the Computer Science & Engineering Department at the University of California, San Diego (UCSD), and founder of the PICASSO Lab. She earned a Ph.D. in Computer Science from North Carolina State University and a B.S. in Physics from the University of Science and Technology of China. Research Interests: Quantum Computing Machine Learning Domain-Specific Languages Compiler Optimization Hardware Acceleration High-Performance Computing Her recent publications focus on quantum compilation, error correction, and machine learning systems, with a particular emphasis on hardware-aware optimizations. She has received multiple prestigious awards, including the NSF CAREER Award (2020) and the IEEE TCHPC Early Career Researchers Award (2019). Scientific Awards: NSF CAREER Award (2020) IEEE Computer Society TCHPC Early Career Researchers Award (2019) Yufei actively advises Ph.D. students and postdoctoral researchers in quantum computing and machine learning systems. Her lab offers openings for both quantum computing and machine learning research.
Rodolfo Pellizzoni is a Professor in the Department of Electrical and Computer Engineering at the University of Waterloo, Canada. His research focuses on real-time systems, embedded systems, and computer architecture, with an emphasis on time-predictable computing, multicore systems, and FPGA networks. He has contributed extensively to cache management, memory resource coordination, and security-aware scheduling in critical systems. His work includes designing frameworks like HopliteRT for FPGA NoCs, optimizing memory bandwidth regulation, and addressing challenges in mixed-criticality systems. Pellizzoni is affiliated with the Faculty of Engineering and maintains a research group focused on hardware-software co-design for real-time applications. His research bridges theoretical models (e.g., Network Calculus) with practical implementations, emphasizing latency reduction and resource predictability in heterogeneous platforms. Recent publications highlight advancements in cache partitioning, dynamic memory allocation, and scheduling algorithms for multicore processors. His work often appears in top-tier conferences like Euromicro Conference on Real-Time Systems (ECRTS) and journals focusing on embedded and real-time systems.
Samira Khan is an Associate Professor in the Department of Computer Science at the University of Virginia (UVA), leading the ShiftLab research group. Her research focuses on computer architecture, high-performance computing, persistent memory systems, and processing-in-memory (PIM) technologies. Prior to UVA, she completed a postdoctoral fellowship at Carnegie Mellon University, supported by Intel Labs and an NSF GOALI award. She earned her Ph.D. in Computer Science from the University of Texas at San Antonio. Her work addresses challenges in memory and storage systems, including optimizing persistent memory reliability, enhancing PIM architectures, and mitigating security vulnerabilities in modern hardware. Notable projects include CRISP (a $29.7M initiative to tackle the 'memory wall'), and the development of tools like PiMulator and PIMProf for PIM emulation and profiling. Research trends in her articles emphasize advancing PIM efficiency, persistent memory security, and cloud-scale system optimization. She has pioneered techniques like NearPM for storage-class applications and EdgeRAG for edge device computing. Her work frequently intersects with real-world applications, such as improving data persistence in networks and enhancing fault tolerance in memory systems. Grants include NSF GOALI funding and Intel Labs support. She collaborates on multi-institutional projects and maintains an active open-source infrastructure (e.g., SoftMC for DRAM studies). Her lab focuses on bridging hardware-software gaps to deliver scalable, energy-efficient computing solutions.
Marco Caccamo is an Adjunct Professor at the University of Illinois at Urbana-Champaign (UIUC) and holds a courtesy appointment in the Coordinated Science Lab and Department of Aerospace Engineering. He earned a Ph.D. in Computer Engineering from Scuola Superiore Sant'Anna (Italy) in 2002. His research focuses on embedded systems, real-time computing, and cyber-physical systems, with applications in avionics, automotive systems, and UAVs. He is a recipient of the IEEE Fellow (2018) and Alexander von Humboldt Professorship (2018). He has chaired major conferences such as RTSS and RTAS and served as General Chair of CPSWeek 2011. His work includes contributions to real-time scheduling, multicore resource management, and reinforcement learning for autonomous systems. Current research highlights include sandboxing AI-based controllers and 6D pose estimation for robotic systems. He leads the Real-Time and Embedded System Laboratory and collaborates with industries to develop innovative software architectures for embedded systems.
