Prof. Hayden Kwok Hay SO is an Associate Professor at the University of Hong Kong (HKU), affiliated with the Department of Electrical and Electronic Engineering. He currently serves as Acting Director of the School of Innovation and previously co-directed the Computer Engineering Program. His research focuses on reconfigurable computing systems, FPGA-based architectures, and their applications in AIoT, medical imaging, and high-performance computing. He holds a B.S., M.S., and Ph.D. in Electrical Engineering and Computer Sciences from UC Berkeley (1998–2007). Prof. So has been recognized with awards such as the IEEE-HKN Teaching Award (2021), Croucher Innovation Award (2013), and multiple teaching excellence awards. He leads the Computer Architecture & System Research Lab (CASR) and co-founded the Joint Lab on Future Cities (JLFC). His work spans FPGA overlay architectures, graph processing systems, and hardware-software co-design for efficient computing. Key research contributions include advancements in FPGA-based reconfigurable systems, sparse dataflow architectures, and medical imaging accelerators. He has secured grants for projects like 'Advanced machine vision guided aquatic surface vehicles' and 'Efficient and Productive Parallel Data Processing in Hybrid FPGA-CPU Clusters.' Prof. So has advised numerous students and researchers, contributing to over 150 peer-reviewed publications. His current projects explore AI hardware acceleration, neuromorphic computing, and FPGA-driven solutions for big data challenges.
Geng Yuan is an Assistant Professor at the University of Georgia's School of Computing, specializing in AI systems, energy-efficient deep learning, and hardware-software co-design. His work bridges machine learning algorithms with emerging hardware technologies like superconducting circuits and ReRAM. He holds a Ph.D. in Computer Engineering from Northeastern University (2023) and a Master's in Electrical & Computer Engineering from Syracuse University (2016). Doctor of Philosophy (Ph.D.) in Computer Engineering, Northeastern University (2023) Master of Science (M.S.) in Electrical & Computer Engineering, Syracuse University (2016) Bachelor of Science (B.S.) in Electrical Engineering, Beijing University of Technology (2014) His research focuses on optimizing deep learning systems for edge computing and mobile platforms through techniques like model compression, sparse training, and hardware-aware neural architecture search. Recent projects include adapting large language models via hybrid-grained pruning and developing ultra-low-power AQFP circuits for binary networks. Geng Yuan's publications span top venues like NeurIPS, CVPR, ICML, ICLR, ISCA, and DAC, with notable awards including a Best Paper Award at ICLR Workshop 2021, Spotlight Papers at ICLR 2023 and NeurIPS 2021, and a Design Contest 1st Place at ISLPED 2020. Best Paper Award (ICLR Workshop'21) Spotlight Paper Award (ICLR'23, NeurIPS'21) Design Contest 1st Place (ISLPED'20) Best Paper Nomination (DATE'21, ISQED'18) He actively recruits Ph.D., Master's students, and interns to his research group, focusing on advancing AI systems through interdisciplinary approaches combining machine learning, computer architecture, and electronic design automation.
James C. Hoe is Professor of Electrical and Computer Engineering at Carnegie Mellon University (College of Engineering). He is on sabbatical at MangoBoost and directs research in computer architecture, reconfigurable computing, and high-level hardware design. Education Ph.D., Electrical Engineering and Computer Science, MIT (2000) M.S., Electrical Engineering and Computer Science, MIT (1994) B.S., Electrical Engineering and Computer Science, UC Berkeley (1992) Research Interests Professor Hoe’s work spans computer architecture , reconfigurable computing , FPGA architectures , and high-level hardware synthesis . His group created the CoRAM abstraction for virtualized FPGA computing and leads efforts in power-efficient accelerators, in-network computing, and security-oriented FPGA systems. Scientific Awards IEEE Fellow (2013) Intel Outstanding Researcher Award (2021) Research Funding & Projects Intel / VMware Crossroads 3D-FPGA Academic Research Center – co-leading exploration of FPGA roles in future datacenters. DARPA BRASS program ($2.7 M, 4 years) – ensuring long-lived software systems remain robust to resource changes. Pigasus open-source IDS – world’s fastest FPGA-accelerated intrusion-detection system (100 Gb/s on one server). Labs & Teams He heads activities within the Computer Architecture Lab at Carnegie Mellon (CALCM) , supervising graduate researchers on CoRAM++, SPIRAL autotuning, and FPGA overlays for stream processing.
Shiri Azenkot is an Associate Professor at the Jacobs Technion-Cornell Institute at Cornell Tech and Cornell University, affiliated with the Information Science Department and Technion’s Computer Science Department. Her research focuses on accessibility innovations in emerging technologies, particularly addressing needs of people with vision impairments and neurodiverse populations. She holds a PhD from the University of Washington, advised by Richard Ladner and Jacob Wobbrock, and has been recognized with prestigious awards including the NSF Graduate Research Fellowship. Education: PhD in Computer Science & Engineering from University of Washington (advisors: Richard Ladner, Jacob Wobbrock). Research interests include VR/AR accessibility, assistive technology design, inclusive education tools, and ethical AI applications. Current projects explore social VR avatars for invisible disabilities, AR navigation aids, and AI moderation systems against ableist hate speech. Her work is funded by NSF, AOL, Verizon, and Facebook. Recent publications address video accessibility for ADHD users, AI-driven scene descriptions for blind users, and tactile learning materials co-designed with educators. She leads the XR Access initiative promoting inclusive virtual/augmented reality. Awards include the UW Graduate Medal (2020), NSF CRII Award (2017), and AT&T Labs Fellowship (2014). Her research bridges academic innovation with industry impact through collaborations with tech companies and disability advocacy groups.
Affiliation & Education Scott Hauck is a Professor at the University of Washington's Department of Electrical & Computer Engineering and an Adjunct Professor in Computer Science & Engineering. He leads the Adaptive Computing Machines and Emulators (ACME) Lab . He earned his BS in EECS from UC Berkeley (1990), and MS/PhD in CSE from the University of Washington (1992/1995). Research Focus Dr. Hauck specializes in FPGA-based reconfigurable computing with applications in: Quantum Computing: FPGA controllers for trapped-ion quantum systems enabling precise laser control and quantum state readout. Medical Imaging: Portable radiation sensors for personalized cancer therapy and PET scanner enhancements. High-Energy Physics: FPGA readout systems for ATLAS pixel detectors at CERN's Large Hadron Collider. AI Acceleration: Real-time machine learning inference for scientific applications via projects like hls4ml. His work bridges hardware innovation with computational physics, emphasizing real-time processing and low-latency systems. Publication Trends Recent research focuses on FPGA-accelerated machine learning for particle physics (e.g., transformer networks for LHC trigger systems) and quantum computing instrumentation. Earlier work established foundations in reconfigurable computing architectures and medical imaging electronics. Awards & Recognition Distinguished Teaching Award, University of Washington (2010) Advising & Funding Leads the ACME Lab with extensive funding from NSF, DARPA, NIH, DOE, and industry partners including Intel, Xilinx, and Microsoft. Mentored over 30 MS/PhD students in VLSI, reconfigurable systems, and scientific computing. Collaborations & Labs Directs the ACME Lab (EE1-307), collaborating with UW Radiology (Prof. Robert Miyaoka), UW Physics (Prof. Shih-Chieh Hsu), and Drexel University (Prof. Josh Agar). Projects include quantum control systems, LHC readout electronics, and medical sensor networks.
Dr. Ismail Guvenc is a Full Professor in the Department of Electrical and Computer Engineering at North Carolina State University. He holds an IEEE Fellowship and is a Senior Member of the U.S. National Academy of Inventors. His research focuses on 5G/6G wireless systems, UAV communications, heterogeneous networks, and spectrum management. He leads the NSF AERPAW project and serves as the NC State Site Director for the NSF BWAC I/UCRC center. Dr. Guvenc has authored/co-edited four books and holds over 30 U.S. patents. Education: Ph.D. in Electrical Engineering, University of South Florida (2006) Master's in Electrical and Computer Engineering, University of New Mexico (2003) Bachelor's in Electrical Engineering, Bilkent University, Turkey (2001) Research Interests: Dr. Guvenc’s work spans UAV communication systems, 5G/6G networks, spectrum sensing, and machine learning for network optimization. He emphasizes experimental validation through platforms like AERPAW, focusing on drone-based networks, radio dynamic zones, and testbed-driven innovation. His contributions address challenges in UAV localization, interference management, and energy-efficient networks. Grants & Leadership: PI and Director of NSF AERPAW (2019–Present) NC State Site Director for NSF BWAC I/UCRC (2019–Present) Recipient of NSF CAREER Award (2015) and NC State Faculty Scholar Award (2021) Publications & Awards: He has authored over 130 peer-reviewed papers and contributed to standardization efforts. His awards include the R. Ray Bennett Faculty Fellow Award (2019) and the USF Outstanding Dissertation Award (2006). Labs & Teams: Dr. Guvenc directs research in the ECE’s wireless communications group, leveraging AERPAW’s experimental capabilities to advance UAV networks and 6G technologies. His team collaborates with industry and government on spectrum policy and autonomous systems.
Zhonghai Lu is a Professor of Electronic Systems Design (specializing in Dependable and Autonomous Systems) at KTH Royal Institute of Technology, part of the Department of Electrical Engineering in the School of Electrical Engineering and Computer Science (EECS). He serves as Program Director for KTH's Embedded Systems master's program and Director of Studies at the Division of Electronics and Embedded Systems. His research focuses on Network-on-Chip (NoC), computer architecture, embedded systems, and Prognostics and Health Management (PHM) of power electronics. He leads a research group exploring in-network processing and embedded intelligence, transforming passive networks into active computational frameworks. Lu holds a BSc from Beijing Normal University (1989), MSc and PhD from KTH (2002, 2007), and an MBA in Innovation and Growth from the University of Turku (2012). He has authored over 240 scientific papers, including journal articles and peer-reviewed conferences, with notable recognitions such as Best Paper Awards at NOCS’2015 and EU HiPEAC, and a Featured Paper in IEEE Transactions on Computers (2020). He serves as Associate Editor for ACM Transactions on Architecture and Code Optimization (TACO) and has chaired major conferences like HiPEAC’2017 and NOCS’2018. His research group’s recent work includes integrating AI into hardware acceleration, fault-tolerant neural networks, and RUL estimation for power electronics using recurrent neural networks. Lu has secured grants from the Swedish Research Council and Intel Corporation and developed courses like IL2230 (Hardware Architectures for Deep Learning) and IL2233 (Embedded Intelligence), pioneering embedded AI education at KTH. Education: BSc (Beijing Normal University), MSc/PhD (KTH), MBA (University of Turku) Awards: Best Paper Awards (NOCS, EU HiPEAC), Swedish Research Council Grants, Intel Research Gifts Labs/Teams: Research Group on In-Network Processing and Embedded Intelligence
Naresh R. Shanbhag is the Jack Kilby Professor in the Department of Electrical and Computer Engineering and the Coordinated Science Laboratory at the University of Illinois at Urbana-Champaign. He serves as Director of the Systems on Nanoscale Information fabriCs (SONIC) Center and held the D.J. Gandhi Distinguished Visiting Professorship at IIT Mumbai from 2015-2020. Previously, he was a visiting faculty member at National Taiwan University (2007) and Stanford University (2014). Dr. Shanbhag received his doctorate from the University of Minnesota (1993) in Electrical Engineering. From 1993 to 1995, he worked at AT&T Bell Laboratories as the lead chip architect for AT&T's 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and very high-speed digital subscriber line (VDSL) chip-sets. His research focuses on the design of energy-efficient machine learning, communications, and signal processing systems on resource-constrained embedded platforms. He explores fundamental trade-offs between energy efficiency, latency and accuracy of decision-making systems implemented in nanoscale technologies, with applications to computer vision, biomedicine, automatic target recognition, and imaging. His work spans four primary focus areas: Resource-efficient Machine Learning for the Edge, In-memory Computing (IMC), Energy-efficient High Data Rate Communications, and Shannon-inspired Statistical Error Compensation (SEC). Analysis of his recent publications reveals a strong emphasis on in-memory computing architectures (SRAM, MRAM, RRAM) for machine learning acceleration. His work consistently addresses energy-accuracy trade-offs, with increasing attention to security aspects of hardware implementations and applications to MIMO signal processing and edge AI systems. His research demonstrates a progression from theoretical foundations to practical silicon implementations. 2024 Semiconductor Research Corporation Innovation Award 2018 Semiconductor Industry Association/Semiconductor Research Corporation University Researcher Award 2018 IEEE International Symposium on Circuits and Systems Best Paper Award 2006 IEEE Fellow 1996 National Science Foundation CAREER Award Professor Shanbhag has mentored over 50 graduate students who now work at leading technology companies including Qualcomm, Amazon, Nvidia, Intel, and Apple. His research has been generously supported by the National Science Foundation, DARPA, AFRL, Semiconductor Research Corporation, Texas Instruments, Sandia National Laboratories, and industry partners including IBM, GlobalFoundries, and Intel Corporation. He led the Alternative Computational Models research theme (2006-2012) and was the founding Director of the SONIC Center (2013-2017), a 5-year multi-university center funded by DARPA and SRC. Currently, he leads research themes in the SRC and DARPA funded JUMP 2.0 Program's Center for Co-Design of Cognitive Systems and the Center for Ubiquitous Connectivity, and in the NSF IUCRC Center for Advanced Semiconductor Chips with Accelerated Performance (ASAP). As Director of the Systems on Nanoscale Information fabriCs (SONIC) Center, Professor Shanbhag leads a multidisciplinary team exploring novel computing paradigms for the nanoscale era. His group has benchmarked an extensive collection of in-memory computing and digital accelerator IC designs, maintaining a publicly available IMC benchmarking repository of metrics extracted from published IC prototypes. His research philosophy integrates concepts from information theory, statistical signal processing, detection and estimation, VLSI architectures, and digital and analog integrated circuits to develop energy-efficient systems from algorithms to silicon implementations.
Dr. Hiren Patel is a Professor in the Department of Electrical and Computer Engineering at the University of Waterloo. He holds a Doctorate in Computer Engineering from Virginia Tech and previously worked as a postdoctoral fellow at UC Berkeley under Edward A. Lee. His research focuses on real-time embedded systems, computer architecture, machine learning hardware, and cybersecurity. He teaches courses like ECE 150 (Programming), ECE 320/429 (Computer Architecture), and ECE 327 (Digital Systems). Research Interests: Cyber-physical systems and hybrid architectures Hardware/software co-design methodologies Predictable cache coherence protocols IoT and edge computing systems Security in embedded and real-time systems Recent work emphasizes cache coherence solutions for safety-critical systems and GPU acceleration strategies. His publications address challenges in multicore predictability, FPGA bandwidth optimization, and autonomous robotics orchestration. No specific awards are listed, though his extensive publication record indicates significant contributions to embedded systems research. He currently oversees graduate student applications focusing on his core research areas.
Yanzhi Wang is a Professor in the Department of Electrical and Computer Engineering at Northeastern University , affiliated with the Institute for Experiential AI and the Institute for the Wireless Internet of Things . He holds a PhD from the University of Southern California (2014). His research focuses on real-time AI systems, deep neural network compression, neuromorphic computing, and non-von Neumann architectures. Notable projects include NSF-funded initiatives on age-inclusive urban design, superconducting computing (DISCoVER), and edge device optimization (PatDNN). He has received prestigious awards such as the Army Research Office Young Investigator Award and the Constantinos Mavroidis Translational Research Award. His work emphasizes algorithm-hardware co-design for energy efficiency, with grants from NSF, ARO, and industry partners like Google. Recent research trends reflect his focus on accelerating vision transformers, diffusion models, and large language models for edge computing. He has pioneered methods like AutoViT and Fastcar, addressing latency and resource constraints in mobile platforms. Collaborations span academia and industry, driving innovations in superconducting circuits and neuromorphic systems.
José F. Martínez holds the Lee Teng-hui Professorship of Engineering at Cornell University's College of Engineering, where he leads research in computer architecture and systems. His roles include Vice Chair of ACM SIGARCH, IEEE Fellow, and past leadership roles in ISCA, MICRO, and IEEE Computer Society journals. He has received prestigious awards such as the NSF CAREER Award, IBM/Qualcomm Faculty Awards, and multiple teaching accolades including Tau Beta Pi Professor of the Year (2011). Education: Licenciado en Informática de Sistemas (1996), Universidad Politécnica de Valencia M.S. (1999) and Ph.D. (2002) in Computer Science, University of Illinois at Urbana-Champaign His research focuses on computer architecture , including microprocessors, multiprocessors, memory subsystems, embedded systems, and processing-in-memory (PIM) innovations. He co-leads the DARPA/SRC ACE Center for Evolvable Computing and NSF's CROPPS Center, and previously co-founded Cornell's Institute for Digital Agriculture (CIDA). His work bridges hardware-software co-design and sustainable computing. Key Contributions: Advancing energy-efficient multiprocessor architectures Developing PIM frameworks like PUMICE and Membrane Market-based resource allocation systems (e.g., XChange, ReBudget) His advising spans over 15 graduate students and has guided Merrill Presidential Scholars. Current research explores evolvable computing paradigms and AI hardware acceleration, reflecting his dual focus on foundational architecture and applied systems innovation.
Shiyu Su is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Waterloo. His research focuses on high-speed data converters, wireless transceivers, digital phase-locked loops (PLL), and AI-assisted analog/mixed-signal design automation. He holds a Ph.D. from the University of Southern California (2019) and teaches courses such as ECE 340 (Electronic Circuits 2) and ECE 432 (Radio Frequency Integrated Devices and Circuits). Education: B.S. from Beijing University of Post and Telecommunication (China) and Queen Mary, University of London (UK), 2011; M.S. and Ph.D. from USC, 2013 and 2019, all in electrical engineering. Research Interests: High-speed ADCs/DACs RF/mm-wave transceivers Time-approximation filters (TAF) Analog/mixed-signal design automation Memristor-based computing Biomedical interfaces Key Awards: IEEE SSCS Predoctoral Achievement Award (2017–2018) Best Student Paper Award at IEEE RFIC (2022) Ming Hsieh Institute Scholar (2019–2020) Lab Focus: The Shiyu Su Lab develops integrated circuits for communications, sensing, and computing, with a focus on AI-driven methodologies and digital-analog co-design. Collaborations include work with Prof. Wei Wu (USC) on memristor-based systems.
Marco Platzner is a Professor for Computer Engineering at Paderborn University , Germany. He serves as the Dean of Research for the Faculty of Computer Science, Electrical Engineering and Mathematics and heads the Department of Computer Science. Previously, he held research positions at ETH Zurich, Stanford University, GMD (now Fraunhofer IAIS), and Graz University of Technology. Education: Diploma and PhD in Telematics (Graz University of Technology, 1991 and 1996), Habilitation in Hardware-Software Co-Design (ETH Zurich, 2002) Research Interests focus on reconfigurable computing, approximate computing, self-* computing, and embedded systems. His work addresses hardware security, FPGA design, and sustainable AI in data centers. Current projects include energy-efficient AI through deep neural network approximation for FPGAs (EKI-App) and lifecycle sustainability of socio-technical systems (SAIL). Publication Trends show expertise in FPGA security, approximate circuit synthesis, robotics, and hardware acceleration. Collaborations span robotics (ROS 2 integration), AI (transformer optimization), and cybersecurity (Trojan detection). Scientific Awards: ACM SIGDA Hall of Fame (2020) Significant Paper Award (FPL 2015) Best Paper Awards at IEEE ISVLSI (2024), ARC (2018), IEEE ReConFig (2015), and others Weierstraß Prize for Teaching (2008) Leadership Roles include membership in the board of Paderborn Center for Parallel Computing (PC2) and the Jenny Aloni Centre for Early Career Researchers. He has contributed to EU FP7 FET project EPiCS and German priority programs on embedded systems and organic computing.
Ranjay Krishna is an Assistant Professor at the Paul G. Allen School of Computer Science & Engineering at the University of Washington, where he co-directs the RAIVN lab and leads the computer vision team at the Allen Institute for AI (Ai2). His research intersects computer vision , natural language processing , robotics , and human-computer interaction . PhD in Computer Science from Stanford University (2021) Bachelor's and Master's degrees from Stanford and Cornell His work has received best paper , outstanding paper , and orals at top conferences like CVPR, ACL, CSCW, NeurIPS, UIST, and ECCV. Media outlets including Science , Forbes , and PBS NOVA have covered his research. He has been supported by grants from Google , Apple , NFS , and others. Ranjay advises a diverse group of 15 PhD and postdoctoral researchers , including Jieyu Zhang, Benlin Liu, and Cheng-Yu Hsieh. His teams have developed benchmarks like MemoryBench and The Colosseum , and his PathFinder framework achieved 74% accuracy in skin melanoma diagnosis—surpassing human experts by 9%. Notable contributions include: Perception Tokens for visual reasoning in MLMs SAM2Act for robotic manipulation with memory Synthetic Visual Genome dataset with 5.6M relationships
Olga Fink is a Tenure Track Assistant Professor at the École Polytechnique Fédérale de Lausanne (EPFL), affiliated with the Department of Intelligent Maintenance and Operations Systems (IMOS) within the School of Architecture, Civil and Environmental Engineering (ENAC). She also holds roles in PhD program committees for Civil and Environmental Engineering (EDCE) and Robotics, Control, and Intelligent Systems (EDRS). Her research focuses on machine learning for infrastructure monitoring, predictive maintenance, and physics-informed AI models. She teaches courses on machine learning, data science for infrastructure, and advanced deep learning topics. Fink advises multiple PhD students and is involved in interdisciplinary projects such as ThermoNeRF (multimodal 3D thermal modeling) and physics-informed neural networks for fault diagnostics. Her work bridges AI and engineering with applications in smart infrastructure, energy systems, and industrial IoT. Education: PhD in Engineering (inferred from role) Affiliations: IMOS Lab, ENAC-SGC, EPFL PhD Committees (EDCE, EDRS) Key Research Themes: Explainable AI, Digital Twins, Structural Health Monitoring, Domain Adaptation Her publications (2023–2025) emphasize robust AI for industrial systems, including fault detection in high-voltage equipment, multimodal data fusion, and physics-consistent models. She collaborates on EU and industry-funded projects, focusing on real-world applications like predictive maintenance and energy efficiency.
