Ana Klimovic is an Assistant Professor at the Department of Computer Science, ETH Zürich, and Deputy Head of the Institute for Computing Platforms. She leads the Efficient Architectures and Systems Lab (EASL) and focuses on optimizing cloud computing performance and resource efficiency. Education: Ph.D. in Electrical Engineering (Stanford University), M.S. in Electrical Engineering (Stanford), B.A.Sc. in Engineering Science (University of Toronto) Previous Roles: Research Scientist at Google Brain Her research spans cloud computing, operating systems, distributed systems, and their intersection with machine learning. Key areas include cloud-native programming models, elastic storage, GPU sharing, and data pipeline optimization. The 2025-2024 articles highlight trends in serverless computing, large language model (LLM) serving, GPU optimization, and data-centric ML systems. Themes include elasticity, resource multiplexing, heterogeneous computing, and infrastructure for AI/ML workloads. Scientific Awards: Microsoft Research PhD Fellowship, Stanford Graduate Fellowship She has led research projects on ephemeral storage, distributed training automation, and cost-efficient ML preprocessing, with grants from Microsoft Research and Stanford.
Dr. Arkaprava Basu is an Associate Professor at the Indian Institute of Science (IISc), Bangalore. He received the ACM India Early Career Researcher (ECR) Award 2024 for his innovative contributions to efficient memory management in GPUs and CPUs through cross-stack software-hardware research. Affiliation: Indian Institute of Science (2018–present) Prior Roles: Full-time Research Staff at AMD Research (Austin, USA, 2014–2018) Education: PhD in Computer Science from University of Wisconsin-Madison (2013) His research focuses on optimizing AI hardware systems by integrating compiler, runtime, and OS design with hardware architecture. Collaborations include long-term consultancy with tech giants, emphasizing practical implementations of his theoretical work. Recognitions: ACM India ECR Award (2024) for "creative and impactful contributions toward efficient memory management for GPUs and CPUs"
Prof. Roger Wattenhofer is a Full Professor at the Department of Information Technology and Electrical Engineering, ETH Zurich, Switzerland, and Deputy head of the Computer Engineering and Networks Lab. He holds a doctorate in Computer Science from ETH Zurich (1998) and has held positions at Brown University and Microsoft Research before returning to ETH. His research focuses on distributed computing, wireless networks, and algorithmic systems design, with contributions to Byzantine agreement protocols, blockchain technologies, and neural network architectures. He teaches courses such as Distributed Systems and Computational Thinking. Education: Ph.D. in Computer Science (ETH Zurich, 1998). Research interests include distributed systems, network algorithms, and the intersection of machine learning with distributed computing. His work spans both theoretical foundations and practical implementations, addressing challenges in fault tolerance, consensus mechanisms, and algorithmic efficiency. Recent publications explore topics like adversarial robustness in voting systems, privacy in reinforcement learning, and generative music models. He actively contributes to open-source frameworks and benchmarks for neural algorithmic reasoning.
Subhasish Mitra is the William E. Ayer Professor of Electrical Engineering and Computer Science at Stanford University, holding dual appointments in both departments. He leads the Stanford Robust Systems Group and serves on the leadership team of the Microelectronics Commons AI Hardware Hub under the US CHIPS and Science Act. His research spans Robust Computing, NanoSystems, Electronic Design Automation (EDA), and Neurosciences, with breakthroughs in X-Compact test compression, carbon nanotube computing, and 3D integration. He has held international roles like the Carnot Chair at CEA-LETI and Visiting Professorships globally. Education & Honors: Recipient of over 40 awards including the IEEE Computer Society’s Harry H. Goode Memorial Award, ACM/IEEE’s A. Richard Newton Technical Impact Award, and the Intel Achievement Award. He earned top academic accolades from IIT Kharagpur and Jadavpur University, and is a Fellow of ACM and IEEE. Research Impact: Pioneered first-of-their-kind systems like the carbon nanotube computer and monolithic 3D integration. His work on robust computing techniques like QED validation and X-Compact compression has industry-wide adoption, saving billions in manufacturing costs. Collaborates with industry leaders like Intel, Google, and Samsung. Publications & Grants: Over 400 publications, including award-winning papers in DAC, ISSCC, and IEEE journals. Leads grants from NSF, DoE, and industry partnerships. His lab explores cutting-edge topics like neuromorphic computing, 3D thermal scaffolding, and AI hardware acceleration. Administration & Outreach: Serves as Associate Chair (Faculty Affairs) for Stanford’s Computer Science Department. Recognized by students for mentorship, and frequently invited to global forums like the World Economic Forum and National Academy of Engineering.
Haitong Li is an Assistant Professor in the School of Electrical and Computer Engineering at Purdue University's College of Engineering, joining the faculty in 2022. His research bridges nanoelectronic devices, integrated circuits, and nanotechnology-inspired AI hardware to address critical challenges in energy-efficient artificial intelligence systems. Education: Ph.D. in Electrical Engineering, Stanford University Research Interests: Dr. Li pioneers emerging memory technologies—particularly Resistive RAM (RRAM)—for in-memory computing and neuromorphic systems. His work focuses on 3D monolithic integration of RRAM and gain cell memory with CMOS to enable edge AI, with recent breakthroughs in hardware acceleration for large language models and sustainable computing. Key innovations include carbon footprint prediction for LLMs and zeroth-order fine-tuning techniques. Publication Trends: Dr. Li's 2023-2025 publications reveal a strategic shift toward sustainable AI hardware, emphasizing carbon-aware LLM inference and edge deployment. His research consistently targets data movement reduction through memory-centric architectures, spanning photonic accelerators, neuro-symbolic computing, and heterogeneous 3D integration. Awards: No scientific awards were documented in the provided sources. Advising and Grants: Current advisees and grant funding details were not specified in the available materials. Labs and Teams: Research group composition and laboratory facilities were not described in the source text.
Vijay Raghunathan is a Professor in the Department of Electrical and Computer Engineering at Purdue University's College of Engineering. His work focuses on hardware and software architectures for embedded systems, wireless sensors for IoT, and wearable/implantable electronics with emphasis on low power design, energy harvesting, emerging memory technologies, and secure system design. Academic Rank: Professor Department: Electrical and Computer Engineering University: Purdue University Research Focus: Energy-efficient embedded systems, IoT, wearable devices His research explores low power design at both board-level and system-on-chip scales, micro-scale energy harvesting , and reliable/secure system design for medical devices. Recent work focuses on Processing-in-Sensor/Memory for battery-free AIoT devices, state space models for neural processing units, and security coprocessor integration in autonomous systems. Analysis of his publications reveals trends in energy-efficient neural network acceleration , approximate computing for edge inference , and compute-in-memory architectures . Key subfields include collaborative edge-cloud partitioning , sparse DNN accelerators , and security frameworks for medical devices. Vijay's work also addresses energy-accuracy tradeoffs in multimodal cognitive systems and intermittent computing using non-volatile memory technologies. His contributions span from microcontroller energy management to security protocols for implantable electronics.
Rakesh Kumar is a Professor and John Bardeen Faculty Scholar in the Electrical and Computer Engineering Department at the University of Illinois at Urbana-Champaign. His work focuses on computer architecture, system-level design automation, and low-power computing. PhD in Computer Engineering from University of California, San Diego BS in Electrical Engineering from IIT Kharagpur His research spans all layers of the computing stack, with key contributions to flexible computer systems , waferscale computing , error-resilient architectures , and approximate computing . He has pioneered work on voltage-reliability tradeoffs and peak power management techniques. Recent publications highlight trends in space microdatacenters , printed microprocessors , and neural graph accelerators . His work on plastic chips was recognized as one of the three biggest semiconductor headlines of 2022 by IEEE Spectrum. IEEE Fellow (2024) ISCA Influential Paper Award MICRO Test-of-Time Award ICCAD Ten Year Retrospective Most Influential Paper Award Best Paper Awards at CASES, SELSE, HPCA He has received teaching accolades including the Stanley H. Pierce Faculty Award and Ronald W. Pratt Outstanding Teaching Award . His research group explores hardware-software co-design for emerging applications in AI, IoT, and sustainable computing.
Karthik R. Narasimhan is a Professor at Princeton University's School of Engineering and Applied Science in the Department of Computer Science. Previously, he earned his PhD from MIT under Regina Barzilay and served as a visiting research scientist at OpenAI during 2017-18. His research focuses on the intersection of language and decision-making, building autonomous agents that learn from both experience and human knowledge. His research spans multiple high-impact areas including language agents (Text-DQN, CALM, ReAct, Tree of Thoughts), reinforcement learning (h-DQN, Multi-Objective RL), and AI safety (Toxicity in ChatGPT, DataMUX). He has developed critical datasets and benchmarks such as WebShop, InterCode, SWE-bench, and SILG that have become standard evaluation tools in the field. Current work emphasizes agent capabilities, software engineering automation, and multimodal interaction. His publication trends show strong focus on practical agent deployment (SWE-agent, Tree of Thoughts), safety evaluation (Probing AI Safety), and efficiency improvements (DataMUX). Recent work increasingly addresses real-world challenges in software engineering, security, and human-AI collaboration through rigorous benchmarking. Co-author of foundational GPT (2018) paper Key developer of Text-DQN (2015), CALM (2020), ReAct (2022), Tree of Thoughts (2023) Creator of influential benchmarks: WebShop (2022), SWE-bench (2023), InterCode (2023) He actively advises students through Princeton's computer science program, with research supported by multiple grants focused on autonomous agent development and language-based decision systems. His GitHub repositories (nlp-datasets, text-world-player) demonstrate strong community engagement in open-source research tools. Current projects include advancing language agent capabilities through Reflexion (2023) and Tree of Thoughts (2023) frameworks while addressing critical safety and efficiency challenges.
Jian Huang is an Associate Professor of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign (UIUC), holding a 100% appointment since August 2024. He is also an affiliated Associate Professor in Computer Science and serves as the Y. T. Lo Faculty Fellow in ECE. Huang leads the Systems Platform Research Group and received his Ph.D. in Computer Science from Georgia Institute of Technology in August 2017, where his dissertation earned the College of Computing Dissertation Award. His research focuses on Computer Architecture, Memory and Storage Systems, AI Infrastructure, Distributed Systems, and Systems Security . Huang has pioneered work in sustainable AI infrastructures, modular data centers, neural processing unit virtualization, and ransomware-aware storage systems. His research has been featured in top-tier conferences including ISCA, MICRO, ASPLOS, OSDI, SOSP, and USENIX ATC, with over 50 publications and multiple patents issued worldwide. Huang's research has significant industry impact, with some work transferred into products and featured in popular media outlets including ACM CACM, TechXplore, and Science Daily. His work on non-volatile memory and storage systems has received extensive coverage, with some projects generating over 50 media reports. Among his notable achievements are the ACM SIGMICRO Early Career Award, NSF CAREER Award, IEEE Micro Top Picks (three times), USENIX Best Paper Award, and the MICRO Best Paper Runner Up in 2024. He has secured over $4.01M in grants ($11.12M with collaborators) from NSF, DARPA, Army Research Office, and industry partners. ACM SIGMICRO Early Career Award NSF CAREER Award IEEE Micro Top Picks (three times) USENIX Best Paper Award MICRO Best Paper Runner Up (2024) Google Faculty Research Award NetApp Faculty Fellowship Award Huang actively contributes to the academic community as program co-chair of NVMW'23 and organizer of HotInfra'23. He currently advises 12 Ph.D. students, 1 master student, and multiple undergraduates. His teaching innovations include developing ECE522: Emerging Memory/Storage System and revising ECE511: Computer Architecture with cutting-edge content.
Gustavo Alonso is Full Professor at the Department of Computer Science (D-INFK) of ETH Zurich and Head of the Institute for Computing Platforms . He has been at ETH since 1995, first as a post-doc, then as Assistant Professor from April 1998, and promoted to Full Professor in October 2001. Within the Systems Group he leads the Information and Communication Systems Research Group . Education: 1989 – Telecommunications Engineering (undergraduate), Madrid Technical University (UPM-ETSIT), Spain 1992 – M.S. Computer Science, University of California, Santa Barbara (UCSB) 1994 – Ph.D. Computer Science, University of California, Santa Barbara (UCSB) Research Interests: His work spans databases, distributed systems, cloud-computing architecture, FPGAs, hardware acceleration for data science, parallel and reconfigurable computing . The group investigates how modern heterogeneous hardware—from GPUs to SmartNICs—can be integrated into data-processing systems to achieve orders-of-magnitude performance gains, energy savings, and new functionality such as in-network computation and serverless acceleration. Scientific Awards & Honors: Fellow of the ACM (Association for Computing Machinery) Fellow of the IEEE (Institute of Electrical and Electronics Engineers) Distinguished Alumnus, Department of Computer Science, UC Santa Barbara Four Test-of-Time / Most Influential Paper Awards across databases, programming languages, cloud computing, and software engineering Labs & Projects: He directs the Information and Communication Systems Research Group within the Systems Group ( systems.ethz.ch ). The lab develops open-source platforms such as Coyote v2 for FPGA abstractions, Shuhai for HBM benchmarking, and MicroRec for micro-second recommendation serving, while collaborating with industry on SmartNICs, serverless analytics, and cloud-scale data analytics.
Muhannad S. Bakir is the Dan Fielder Professor in the School of Electrical and Computer Engineering at Georgia Institute of Technology and serves as the Director of the 3D Systems Packaging Research Center. His research focuses on heterogeneous integration of microsystems, including 2.5D and 3D ICs and packaging technologies, with significant contributions to advanced cooling systems, electrical and photonic interconnects, and biosensor integration with CMOS. Dr. Bakir's research interests span heterogeneous microsystem design and integration, advanced cooling and power delivery for emerging architectures, electrical and photonic interconnect technologies, biosensor technologies, and nanofabrication. His work addresses critical challenges in next-generation electronics, enabling polylithic integration that concatenates heterogeneous ICs of various functionalities while mimicking monolithic-like densities. His research particularly focuses on co-design of thermal technologies, power delivery networks, and signaling networks for silicon nanoelectronic systems. His recent publications demonstrate strong trends in fused-silica stitch-chip technology for heterogeneous integration, with particular emphasis on RF and mm-wave applications, power delivery for AI accelerators, and thermal management solutions. His work bridges electrical engineering, materials science, and thermal management to solve critical bottlenecks in computing performance and efficiency. 2013 Intel Early Career Faculty Honor Award 2012 DARPA Young Faculty Award 2011 IEEE CPMT Society Outstanding Young Engineer Award 2012 National Academy of Engineering Frontiers of Engineering Symposium Invited Participant 2015 IEEE CPMT Society Distinguished Lecturer 2014 Best Paper of the IEEE Transactions on Components Packaging and Manufacturing Technology More than 25 conference and student paper awards Twelve issued US Patents Dr. Bakir leads the Integrated 3D Systems Lab (I3DS) at Georgia Tech, which is actively researching advanced packaging, interconnects, electrical and thermal design, and system integration. His team has received significant recognition for their work, including multiple best paper awards from major conferences like ECTC, IITC, and CICC. The lab is currently seeking postdoctoral researchers and research faculty to advance next-generation electronics through collaborative research. His lab focuses on enabling the next phase of Moore's Law through polylithic integration, which concatenates heterogeneous ICs of various functionalities (digital, analog, photonic, and mm-wave) using advanced off-chip '2.5D' and '3D' heterogeneous interconnects and packaging. This work impacts applications in high-performance computing, machine learning, edge intelligence, autonomous vehicles, augmented/virtual reality, and healthcare.
Sumeet Kumar Gupta is an Associate Professor in the Department of Electrical and Computer Engineering at Purdue University. His academic career spans from his current role to a prior Assistant Professorship at Pennsylvania State University (2014-2017) and an engineering position at Qualcomm Inc. (2012-2014). He holds a PhD in Electrical and Computer Engineering from Purdue University (2012), an M.S. from the same institution (2008), and a B.Tech in Electrical Engineering from IIT Delhi (2006). B.Tech, Electrical Engineering, IIT Delhi (2006) M.S., Electrical and Computer Engineering, Purdue University (2008) PhD, Electrical and Computer Engineering, Purdue University (2012) Dr. Gupta's research focuses on neuromorphic computing, low power variation-aware VLSI design in emerging nanotechnologies, device-circuit co-design, and nano-scale device modeling/simulations. His work addresses challenges in ferroelectric materials, crossbar arrays for deep neural networks, and energy-efficient AI hardware. Recent publications (2025-2024) highlight trends in: Ferroelectric HfO2/HZO thin films Compute-in-memory architectures Variability/stochasticity analysis Machine learning for device optimization Interconnect resistance/temperature effects AI hardware fault tolerance Scientific Awards & Recognitions: DARPA Young Faculty Award (2016) Early Career Professorship, Penn State (2014) 6th TSMC Outstanding Student Research Bronze Award (2012) Magoon Award (Purdue) Outstanding Teaching Assistant Award (Purdue, 2007) Intel PhD Fellowship (2009) His professional journey includes academic appointments at Purdue University (2020-present, Associate Professor) and Pennsylvania State University (2014-2017, Assistant Professor) after industry experience at Qualcomm Inc. (2012-2014). He maintains IEEE and EDS membership while publishing over 100 refereed works.
Matteo Sonza Reorda is a Full Professor at the Polytechnic University of Turin, affiliated with the Department of Automatic Control and Computer Science (DAUIN). He holds roles such as Partnership Agreement Coordinator with SMAT and has served as Vice-Rector for Research (2021–2024). His research focuses on fault tolerance, hardware reliability, and AI acceleration, with contributions to GPU/CNN reliability, self-test libraries, and defect-oriented testing. Education: M.S. in Electronics Engineering, Politecnico di Torino (1986) Ph.D. in Computer Engineering, Politecnico di Torino (1990) Research Interests: His work spans automatic test equipment, circuit reliability, GPU fault tolerance, neural network hardening, and embedded systems safety . He leads the Electronic CAD & Reliability Group and collaborates with institutions like the ISI Foundation and the National Research Council (CNR). Publications & Impact: With over 180 publications, his recent work emphasizes AI accelerator reliability, fault injection techniques, and safety-critical systems. Key trends include GPU resilience for CNNs, self-test library optimization, and radiation fault modeling in neural networks. Awards & Recognition: IEEE Fellow (2016–) Multiple best-paper awards at IEEE conferences (DDECS, DATE, etc.) Grants & Collaborations: Coordinator of EU projects (RESCUE, TUTORIAL) Partnerships with EDF, Marelli Europe, and SMAT Lead on National HPC/Quantum Computing Spoke 1 (2022–2025) Labs/Teams: Leads the CAD Group and collaborates with the French-Italian LIA LAFISI lab on hardware-software integration.
Bernhard J. Berger is a Lecturer in the Department of Computer Engineering at the Institute of Embedded Systems, Hamburg University of Technology (TUHH). His research focuses on software security, static code analysis, machine learning, optimization, and research data management. He has held significant roles such as Program Committee member for ICPC 2025 and MSR 2025, and has received awards including the Best Reviewer Award (ICPC 2023) and Best Engineering Paper Award (SCAM 2019). His work spans interdisciplinary applications including maritime systems security, GPU-accelerated AI, and evolutionary algorithms. Recent studies emphasize AI-driven security tools (e.g., ML-SAST) and domain-specific language approaches to optimization (EvoAl). He has contributed to over 30 peer-reviewed publications, with notable work in IEEE Transactions on Software Engineering and Science of Computer Programming. Berger collaborates closely with industry through DAAD review committees and serves on artifact evaluation boards for ISSTA and ARES conferences. Education: Doctoral Thesis (2022), Diploma in Computer Science (2007) Key Projects: ArchSec tool suite, Threat Modeling Frameworks, Bauhaus static analysis methodology Lab Affiliation: Embedded Systems Design Group His advisory roles include Deputy of TUHH's Election Verification Committee and Session Chair at IEEE Congress on Evolutionary Computation 2023. Current research trends integrate machine learning with static analysis for automated vulnerability detection, while also exploring explainable AI techniques for neural network optimization.
Mariano Scazzariello is a Lecturer at KTH Royal Institute of Technology, Sweden, affiliated with the School of Electrical Engineering and Computer Science and the Department of Network and Systems Engineering. He teaches the course 'Network Systems with Edge or Cloud Datacenters (IK2227)'. His research focuses on advanced networking topics including machine learning in networks, high-speed packet processing, network emulation, and software-defined networking innovations. His work spans contributions to network emulation tools like Kathará and Megalos, stateful packet processing at terabit scales, and leveraging large language models (LLMs) for network configuration and vulnerability detection. Recent research emphasizes low-latency protocols (e.g., SRv6/DetNet integration) and GPU-centric networking on commodity hardware. Mariano’s publications (2020–2025) highlight expertise in network function virtualization, ASIC-based switching, and optimizing network configurations through AI-driven approaches. He has pioneered frameworks for evaluating routing protocols and virtualizing large network scenarios at scale.
