Sumeet Kumar Gupta is an Associate Professor in the Department of Electrical and Computer Engineering at Purdue University. His academic career spans from his current role to a prior Assistant Professorship at Pennsylvania State University (2014-2017) and an engineering position at Qualcomm Inc. (2012-2014). He holds a PhD in Electrical and Computer Engineering from Purdue University (2012), an M.S. from the same institution (2008), and a B.Tech in Electrical Engineering from IIT Delhi (2006). B.Tech, Electrical Engineering, IIT Delhi (2006) M.S., Electrical and Computer Engineering, Purdue University (2008) PhD, Electrical and Computer Engineering, Purdue University (2012) Dr. Gupta's research focuses on neuromorphic computing, low power variation-aware VLSI design in emerging nanotechnologies, device-circuit co-design, and nano-scale device modeling/simulations. His work addresses challenges in ferroelectric materials, crossbar arrays for deep neural networks, and energy-efficient AI hardware. Recent publications (2025-2024) highlight trends in: Ferroelectric HfO2/HZO thin films Compute-in-memory architectures Variability/stochasticity analysis Machine learning for device optimization Interconnect resistance/temperature effects AI hardware fault tolerance Scientific Awards & Recognitions: DARPA Young Faculty Award (2016) Early Career Professorship, Penn State (2014) 6th TSMC Outstanding Student Research Bronze Award (2012) Magoon Award (Purdue) Outstanding Teaching Assistant Award (Purdue, 2007) Intel PhD Fellowship (2009) His professional journey includes academic appointments at Purdue University (2020-present, Associate Professor) and Pennsylvania State University (2014-2017, Assistant Professor) after industry experience at Qualcomm Inc. (2012-2014). He maintains IEEE and EDS membership while publishing over 100 refereed works.
James C. Hoe is Professor of Electrical and Computer Engineering at Carnegie Mellon University (College of Engineering). He is on sabbatical at MangoBoost and directs research in computer architecture, reconfigurable computing, and high-level hardware design. Education Ph.D., Electrical Engineering and Computer Science, MIT (2000) M.S., Electrical Engineering and Computer Science, MIT (1994) B.S., Electrical Engineering and Computer Science, UC Berkeley (1992) Research Interests Professor Hoe’s work spans computer architecture , reconfigurable computing , FPGA architectures , and high-level hardware synthesis . His group created the CoRAM abstraction for virtualized FPGA computing and leads efforts in power-efficient accelerators, in-network computing, and security-oriented FPGA systems. Scientific Awards IEEE Fellow (2013) Intel Outstanding Researcher Award (2021) Research Funding & Projects Intel / VMware Crossroads 3D-FPGA Academic Research Center – co-leading exploration of FPGA roles in future datacenters. DARPA BRASS program ($2.7 M, 4 years) – ensuring long-lived software systems remain robust to resource changes. Pigasus open-source IDS – world’s fastest FPGA-accelerated intrusion-detection system (100 Gb/s on one server). Labs & Teams He heads activities within the Computer Architecture Lab at Carnegie Mellon (CALCM) , supervising graduate researchers on CoRAM++, SPIRAL autotuning, and FPGA overlays for stream processing.
Dr. Akhilesh Jaiswal serves as Assistant Professor of Electrical and Computer Engineering at the University of Wisconsin-Madison, where his research pioneers device-circuit co-design for next-generation computing systems. His work focuses on enabling extreme-edge intelligence through processing-in-pixel technology, in-memory computing architectures, and bio-inspired neuromorphic systems. His academic credentials include: PhD in Nano-electronics from Purdue University (2019) MS from the University of Minnesota (2014) Bachelor of Technology from Shri Guru Gobind Singhji Institute of Engineering and Technology (2011) Dr. Jaiswal's research program centers on revolutionizing edge computing through hardware innovations that integrate sensing and processing. His device-circuit co-design approach leverages alternate state variables to create energy-efficient systems for real-time applications, with particular emphasis on retina-inspired sensors and photonic memory architectures. This work bridges semiconductor physics with AI acceleration needs, targeting applications from autonomous systems to biomedical devices. Analysis of his 2023-2025 publications reveals dominant themes in photonic SRAM-based in-memory computing (40% of output), retina-inspired motion processing (30%), and secure hardware architectures (20%). His team consistently develops novel bitcell designs that enable XOR logic execution within memory arrays while maintaining compatibility with CMOS fabrication processes. Recent work shows increasing focus on biomedical applications of processing-in-pixel technology. His distinguished recognition includes: Three consecutive ISI Exploratory Research Awards (2020-2023) IEEE Brain Community Best Paper Award (2022) 27 issued US patents with multiple pending applications Nomination for USC Moore Inventor Fellowship (2022) Dr. Jaiswal actively mentors graduate researchers through ECE 790/890/990 courses while securing exploratory funding through ISI and Keston Foundation awards. His patent portfolio demonstrates exceptional translational impact, with industry game-changer classifications from USPTO. The 2022 VLSI-SoC nomination and multiple research highlights in major outlets validate his contributions to hardware security and neuromorphic vision sensors. His laboratory develops integrated hardware platforms combining magnetic tunnel junctions, photonic memory, and CMOS image sensors to create unified processing-in-sensor systems. Current projects include retina-inspired motion segmentation for event cameras and electro-optic frequency transducers for quantum computing interfaces, with strong industry collaboration through patent licensing.
Dmitri Strukov is a Professor at the University of California, Santa Barbara in the Department of Electrical and Computer Engineering. His work spans material science, electrical engineering, and computer science, focusing on novel computing paradigms using emerging memory devices. Education: PhD in Electrical and Computer Engineering from SUNY Stony Brook, MS in Applied Physics and Mathematics from Moscow Institute of Physics and Technology. Research Interests include neuromorphic computing , non-volatile memory applications , and mixed-signal circuits for machine learning and hardware security. His group develops memristive crossbar arrays and 3D NAND flash for energy-efficient systems. Scientific Leadership features Fellow of IEEE and Distinguished Lecturer roles. His work has been recognized with best paper awards at ASPLOS’19 and Computing Frontiers’13. Students: Mentored PhD graduates in neurocomputing, security, and memristor design including Z. Fahimi, S. Larimian, M.R. Mahmoodi, and X. Guo. Grants: Funded by AFOSR, ARO, DARPA, NSF, and industry leaders like Google and Samsung. Labs: Utilizes UCSB’s nanofabrication center and advanced tools for memristor characterization.
Naresh R. Shanbhag is the Jack Kilby Professor in the Department of Electrical and Computer Engineering and the Coordinated Science Laboratory at the University of Illinois at Urbana-Champaign. He serves as Director of the Systems on Nanoscale Information fabriCs (SONIC) Center and held the D.J. Gandhi Distinguished Visiting Professorship at IIT Mumbai from 2015-2020. Previously, he was a visiting faculty member at National Taiwan University (2007) and Stanford University (2014). Dr. Shanbhag received his doctorate from the University of Minnesota (1993) in Electrical Engineering. From 1993 to 1995, he worked at AT&T Bell Laboratories as the lead chip architect for AT&T's 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and very high-speed digital subscriber line (VDSL) chip-sets. His research focuses on the design of energy-efficient machine learning, communications, and signal processing systems on resource-constrained embedded platforms. He explores fundamental trade-offs between energy efficiency, latency and accuracy of decision-making systems implemented in nanoscale technologies, with applications to computer vision, biomedicine, automatic target recognition, and imaging. His work spans four primary focus areas: Resource-efficient Machine Learning for the Edge, In-memory Computing (IMC), Energy-efficient High Data Rate Communications, and Shannon-inspired Statistical Error Compensation (SEC). Analysis of his recent publications reveals a strong emphasis on in-memory computing architectures (SRAM, MRAM, RRAM) for machine learning acceleration. His work consistently addresses energy-accuracy trade-offs, with increasing attention to security aspects of hardware implementations and applications to MIMO signal processing and edge AI systems. His research demonstrates a progression from theoretical foundations to practical silicon implementations. 2024 Semiconductor Research Corporation Innovation Award 2018 Semiconductor Industry Association/Semiconductor Research Corporation University Researcher Award 2018 IEEE International Symposium on Circuits and Systems Best Paper Award 2006 IEEE Fellow 1996 National Science Foundation CAREER Award Professor Shanbhag has mentored over 50 graduate students who now work at leading technology companies including Qualcomm, Amazon, Nvidia, Intel, and Apple. His research has been generously supported by the National Science Foundation, DARPA, AFRL, Semiconductor Research Corporation, Texas Instruments, Sandia National Laboratories, and industry partners including IBM, GlobalFoundries, and Intel Corporation. He led the Alternative Computational Models research theme (2006-2012) and was the founding Director of the SONIC Center (2013-2017), a 5-year multi-university center funded by DARPA and SRC. Currently, he leads research themes in the SRC and DARPA funded JUMP 2.0 Program's Center for Co-Design of Cognitive Systems and the Center for Ubiquitous Connectivity, and in the NSF IUCRC Center for Advanced Semiconductor Chips with Accelerated Performance (ASAP). As Director of the Systems on Nanoscale Information fabriCs (SONIC) Center, Professor Shanbhag leads a multidisciplinary team exploring novel computing paradigms for the nanoscale era. His group has benchmarked an extensive collection of in-memory computing and digital accelerator IC designs, maintaining a publicly available IMC benchmarking repository of metrics extracted from published IC prototypes. His research philosophy integrates concepts from information theory, statistical signal processing, detection and estimation, VLSI architectures, and digital and analog integrated circuits to develop energy-efficient systems from algorithms to silicon implementations.
Ranjan Singh is a Professor at the Division of Physics, Nanyang Technological University (NTU) Singapore, specializing in terahertz photonics and metamaterials. He holds an elected fellowship from OPTICA (OSA) for pioneering work in ultrafast terahertz photonics, active metamaterials, and sensors. His research focuses on hybrid THz-electronic-photonic technologies for 6G communications, topological photonics, spintronics, quantum materials, and high-Tc superconductors. Education: B.Eng. in Telecommunications (Bangalore University, 2001); M.Tech in Photonics (Cochin University, 2004); Ph.D. in Photonics (Oklahoma State University, 2009). Postdoctoral research at Los Alamos National Laboratory (2009–2013). Research emphasizes on-chip THz topological photonics for next-gen communication systems, with notable achievements including a $7M grant for TERACOMM (on-chip THz topological photonics). His work integrates AI-driven beamforming, reconfigurable metasurfaces, and phase-change materials for adaptive THz systems. Key awards include the 2020 Web of Science 'Top 1% Highly Cited Researcher' distinction. His lab, TeraX Labs (founded 2013), develops cutting-edge technologies like THz brain-computer interfaces, quantum emitters, and spintronic sensors. Over $12M in competitive grants has fueled innovations in THz integrated circuits, tunable optical coatings, and ultra-sensitive biosensors. Advancing 6G/XG wireless, Singh's team designs topological beamformers, intelligent reflecting surfaces (IRS), and terahertz metamaterials for multi-link systems. His work bridges theoretical physics and applied engineering, with a focus on energy-efficient, reconfigurable photonic systems.
Aydin Babakhani is a Professor in the Department of Electrical and Computer Engineering at the University of California, Los Angeles (UCLA), affiliated with the College of Life Sciences. He directs the Integrated Sensors Laboratory (ISL), which focuses on the design and implementation of integrated sensors and systems. His research spans high-speed wireless communication, terahertz technology, medical implants, radar systems, and industrial monitoring solutions. Research Interests: Prof. Babakhani's work integrates silicon-based technologies with applications across multiple domains. Key areas include: Silicon mm-Wave/THz transceivers and on-chip antennas for communication and sensing Wirelessly powered medical implants for biopotential monitoring and neural stimulation THz radar systems for micrometer-resolution imaging and vibration detection Energy harvesting solutions for batteryless sensors in industrial and biomedical applications CMOS-based optoelectronic systems and photonic computing accelerators His recent publications (2021-2025) demonstrate a strong emphasis on terahertz systems, wireless power transfer, and miniaturized medical electronics. Over 80% of his latest articles involve silicon-integrated solutions for biomedical implants or THz sensing, with emerging focus on AI-accelerated photonic computing and multi-Gbps wireless links.
Zhonghai Lu is a Professor of Electronic Systems Design (specializing in Dependable and Autonomous Systems) at KTH Royal Institute of Technology, part of the Department of Electrical Engineering in the School of Electrical Engineering and Computer Science (EECS). He serves as Program Director for KTH's Embedded Systems master's program and Director of Studies at the Division of Electronics and Embedded Systems. His research focuses on Network-on-Chip (NoC), computer architecture, embedded systems, and Prognostics and Health Management (PHM) of power electronics. He leads a research group exploring in-network processing and embedded intelligence, transforming passive networks into active computational frameworks. Lu holds a BSc from Beijing Normal University (1989), MSc and PhD from KTH (2002, 2007), and an MBA in Innovation and Growth from the University of Turku (2012). He has authored over 240 scientific papers, including journal articles and peer-reviewed conferences, with notable recognitions such as Best Paper Awards at NOCS’2015 and EU HiPEAC, and a Featured Paper in IEEE Transactions on Computers (2020). He serves as Associate Editor for ACM Transactions on Architecture and Code Optimization (TACO) and has chaired major conferences like HiPEAC’2017 and NOCS’2018. His research group’s recent work includes integrating AI into hardware acceleration, fault-tolerant neural networks, and RUL estimation for power electronics using recurrent neural networks. Lu has secured grants from the Swedish Research Council and Intel Corporation and developed courses like IL2230 (Hardware Architectures for Deep Learning) and IL2233 (Embedded Intelligence), pioneering embedded AI education at KTH. Education: BSc (Beijing Normal University), MSc/PhD (KTH), MBA (University of Turku) Awards: Best Paper Awards (NOCS, EU HiPEAC), Swedish Research Council Grants, Intel Research Gifts Labs/Teams: Research Group on In-Network Processing and Embedded Intelligence
Dr. Hiren Patel is a Professor in the Department of Electrical and Computer Engineering at the University of Waterloo. He holds a Doctorate in Computer Engineering from Virginia Tech and previously worked as a postdoctoral fellow at UC Berkeley under Edward A. Lee. His research focuses on real-time embedded systems, computer architecture, machine learning hardware, and cybersecurity. He teaches courses like ECE 150 (Programming), ECE 320/429 (Computer Architecture), and ECE 327 (Digital Systems). Research Interests: Cyber-physical systems and hybrid architectures Hardware/software co-design methodologies Predictable cache coherence protocols IoT and edge computing systems Security in embedded and real-time systems Recent work emphasizes cache coherence solutions for safety-critical systems and GPU acceleration strategies. His publications address challenges in multicore predictability, FPGA bandwidth optimization, and autonomous robotics orchestration. No specific awards are listed, though his extensive publication record indicates significant contributions to embedded systems research. He currently oversees graduate student applications focusing on his core research areas.
Anantha Chandrakasan is the Vannevar Bush Professor of Electrical Engineering and Computer Science at MIT, serving as Dean of the MIT School of Engineering and Chief Innovation and Strategy Officer. His research focuses on energy-efficient integrated circuits, medical devices, and AI hardware security. He leads the MIT Energy-Efficient Circuits and Systems Group, developing systems for biomedical applications, wireless communication, and quantum computing. He holds appointments at MIT's Microsystems Technology Laboratories and has contributed to collaborations like the MIT-Takeda Program in AI-driven healthcare and a partnership with GlobalFoundries for energy-efficient AI chips. His work spans implantable drug delivery systems, conformable ultrasound patches, and secure edge computing architectures. Chandrakasan's innovations include ultra-low-power circuits for IoT devices, cryptographic processors for post-quantum security, and AI accelerators for edge applications. He emphasizes interdisciplinary research bridging electrical engineering with biomedical and quantum fields, supported by leadership roles in MIT's strategic initiatives. His contributions to energy-efficient computing have led to advancements in wearable health monitors, batteryless sensors, and secure communication protocols for medical devices. Ongoing projects include THz integrated systems and AI-enhanced analog circuit design optimization.
Justin A. Weibel is a Professor of Mechanical Engineering at Purdue University, affiliated with the School of Mechanical Engineering. He directs the Cooling Technologies Research Center (CTRC), a National Science Foundation Industry/University Cooperative Research Center. His research focuses on advanced electronics cooling, phase-change transport, additive manufacturing for thermal components, and machine-learning-driven design optimization. He has led projects funded by DARPA, ONR, ARPA-E, and industry partners, advancing cooling solutions for high-power electronics and energy systems. Research interests span thermal management, heat transfer, micro/nano-scale engineering, and sustainable energy. Key contributions include topology optimization for heat sinks, two-phase flow modeling, and embedded cooling systems for electric motors. His work integrates computational methods with experimental validation. Grants & Programs: DARPA TGP/ICECool, ONR NEPTUNE, ARPA-E ASCEND/COOLERCHIPS, SRC CHIRP Labs: Cooling Technologies Research Center (CTRC) Future Work: Expanding additive manufacturing applications, improving thermal efficiency in electrified transport, and advancing AI-driven thermal system design. Awards: Fellow of ASME (2023) Outstanding Faculty Mentor (2022) Multiple best paper awards from IEEE ITherm, ASME, and SEMI-THERM conferences
José F. Martínez holds the Lee Teng-hui Professorship of Engineering at Cornell University's College of Engineering, where he leads research in computer architecture and systems. His roles include Vice Chair of ACM SIGARCH, IEEE Fellow, and past leadership roles in ISCA, MICRO, and IEEE Computer Society journals. He has received prestigious awards such as the NSF CAREER Award, IBM/Qualcomm Faculty Awards, and multiple teaching accolades including Tau Beta Pi Professor of the Year (2011). Education: Licenciado en Informática de Sistemas (1996), Universidad Politécnica de Valencia M.S. (1999) and Ph.D. (2002) in Computer Science, University of Illinois at Urbana-Champaign His research focuses on computer architecture , including microprocessors, multiprocessors, memory subsystems, embedded systems, and processing-in-memory (PIM) innovations. He co-leads the DARPA/SRC ACE Center for Evolvable Computing and NSF's CROPPS Center, and previously co-founded Cornell's Institute for Digital Agriculture (CIDA). His work bridges hardware-software co-design and sustainable computing. Key Contributions: Advancing energy-efficient multiprocessor architectures Developing PIM frameworks like PUMICE and Membrane Market-based resource allocation systems (e.g., XChange, ReBudget) His advising spans over 15 graduate students and has guided Merrill Presidential Scholars. Current research explores evolvable computing paradigms and AI hardware acceleration, reflecting his dual focus on foundational architecture and applied systems innovation.
Marco Platzner is a Professor for Computer Engineering at Paderborn University , Germany. He serves as the Dean of Research for the Faculty of Computer Science, Electrical Engineering and Mathematics and heads the Department of Computer Science. Previously, he held research positions at ETH Zurich, Stanford University, GMD (now Fraunhofer IAIS), and Graz University of Technology. Education: Diploma and PhD in Telematics (Graz University of Technology, 1991 and 1996), Habilitation in Hardware-Software Co-Design (ETH Zurich, 2002) Research Interests focus on reconfigurable computing, approximate computing, self-* computing, and embedded systems. His work addresses hardware security, FPGA design, and sustainable AI in data centers. Current projects include energy-efficient AI through deep neural network approximation for FPGAs (EKI-App) and lifecycle sustainability of socio-technical systems (SAIL). Publication Trends show expertise in FPGA security, approximate circuit synthesis, robotics, and hardware acceleration. Collaborations span robotics (ROS 2 integration), AI (transformer optimization), and cybersecurity (Trojan detection). Scientific Awards: ACM SIGDA Hall of Fame (2020) Significant Paper Award (FPL 2015) Best Paper Awards at IEEE ISVLSI (2024), ARC (2018), IEEE ReConFig (2015), and others Weierstraß Prize for Teaching (2008) Leadership Roles include membership in the board of Paderborn Center for Parallel Computing (PC2) and the Jenny Aloni Centre for Early Career Researchers. He has contributed to EU FP7 FET project EPiCS and German priority programs on embedded systems and organic computing.
Morteza Fayazi is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Utah, with an adjunct position in the Kahlert School of Computing. His research focuses on Electronic Design Automation (EDA), applying machine learning to automate analog and mixed-signal circuit design, and developing high-performance computing systems. He holds a B.Sc. from Sharif University of Technology, and M.S.E./Ph.D. degrees from the University of Michigan. His research interests include AI-driven EDA, RF/circuit automation, and energy-efficient processors. Key achievements include the MEDAL lab’s work on terahertz radars, systolic-array processors (e.g., DAP and Versa), and open-source frameworks like FASCINET and Tablext. He has received awards such as the 2024 College of Engineering Dean’s ETR Fund and the 2017 Outstanding Undergraduate Thesis Award. Teaching responsibilities include multiple iterations of the Digital System Design course (ECE/CS 3700). His work spans over 15 peer-reviewed articles in IEEE Transactions, ACM, and top conferences like ICCAD and VLSI-SOC, emphasizing automation, efficiency, and AI integration in hardware design.
Dr. Yayun Du is an Assistant Professor in the Department of Electrical and Computer Engineering at Vanderbilt University School of Engineering. She holds a Ph.D. in Robotics and System Control (Minor: Solid Mechanics) from UCLA (2022) and was a postdoctoral scholar at Northwestern University's Rogers Group through 2024. Current faculty at Vanderbilt University Ph.D. from University of California, Los Angeles Postdoctoral experience at Northwestern University Her research integrates bioelectronics and robotics through three core directions: 1) Developing multimodal wearable/implantable sensors for health monitoring, 2) Creating human-in-the-loop interaction systems using brain-computer interfaces, and 3) Applying machine learning to medical environment robotics. She has deployed four sensor types across seven hospitals globally, serving users from neonates to elderly patients. Dr. Du's recent publications focus on wireless bioelectronic devices ( PNAS ), sustainable sensor materials ( ACS Sustainable Chemistry & Engineering ), and agricultural robotics ( ICRA , IROS ). She serves as Associate Editor for ICRA 2025 and has received two Best Paper Award final nominations at IROS 2021. Finalist - Best Paper Award in Agri-Robotics (IROS 2021) Finalist - Best Paper Award in Robot Mechanisms and Design (IROS 2021) As head of the Du Group, she leads interdisciplinary research with applications in both healthcare and agricultural contexts, collaborating with Vanderbilt Institute for Surgery and Engineering (VISE) and clinical partners. Her work emphasizes deployable systems that transition from academic research to real-world implementation in medical and industrial environments.
