Tsiaras Vasileios

Tsiaras Vasileios is a Teaching Professor in the Department of Electrical and Computer Engineering at the Technical University of Crete. He is currently on leave and based in the School of Electrical and Computer Engineering. His office is located at 141Α-29 in the Science/ECE Building (Λ), 1st Floor.

Education:

• Ph.D. in Computer Science, University of Crete (2009)
• M.Sc. in Mathematics, Queen Mary and Westfield College, University of London (1992)
• Undergraduate Degree in Mathematics, Aristotle University of Thessaloniki (1990)

Research Interests:

His research focuses on Machine Learning, Graph Drawing, Analysis of Brain Signals (including EEG and MEG), and Text-to-Speech Synthesis. These areas integrate computational methods with neuroscience and signal processing to advance artificial intelligence and biomedical applications.

Professional Contributions:

No specific grants or advising roles are listed in the provided information. His work primarily involves laboratory teaching and research in his stated fields.