Soner Onder

Soner Onder is a Professor in the Department of Computer Science at Michigan Technological University, with an affiliated appointment in the Electrical and Computer Engineering department. His work focuses on computer architecture, programming languages, and simulation techniques, contributing significantly to processor design and memory systems research.

Dr. Onder received his PhD in Computer Science from the University of Pittsburgh in 1999. His academic career has established him as a leading researcher in computer architecture with publications spanning two decades in top-tier conferences.

Dr. Onder's research spans multiple areas of computer architecture and compiler design, with emphasis on processor design, memory systems, and compiler optimizations. He has made significant contributions to memory disambiguation techniques, branch prediction mechanisms, and energy-efficient processor designs. His work often bridges hardware and software domains, exploring how compiler techniques can better exploit architectural features. Recent research focuses on memory dependence prediction, recovery mechanisms for mispredictions, and energy-efficient data access patterns, with his "Future Gated Single Assignment Form" representing an innovative approach to program representation that bridges compiler design and architectural support.

• US Patent 7747993: Methods and systems for ordering instructions using future values (2010)

Dr. Onder has advised numerous PhD students to completion, including Scott Pomerville (2024), Gorkem Asilioglu (2020), Omkar Javeri (2020), and Zhaoxiang Jin (2018). His research has been supported by grants including "Statically Controlled Asynchronous Lane Execution (SCALE)" and "Vectorized Instruction Space (VIS)" projects. He developed the FAST (Flexible Architecture Simulation Tool) for architectural research and continues to lead an active research program with publications appearing in top-tier venues through 2018.

Dr. Onder leads research in computer architecture with a focus on practical implementations. His FAST simulation tool provides a flexible platform for testing architectural innovations. His work often involves collaboration with both compiler researchers and hardware designers to create holistic solutions to performance bottlenecks in modern processors, demonstrating the interdisciplinary nature of his research that bridges hardware and software concerns in computer system design.