S. Ramesh

S. Ramesh serves as a Professor in the Department of Computer Science and Engineering at Indian Institute of Technology, Bombay. His research spans formal methods, verification systems, and brain-computer interfaces with notable projects including CFDVS (Center for Formal Design and Verification of Software), UML-based specification systems, and concurrent program analysis.

His research interests focus on Formal Verification, Concurrent Systems, and Reactive Applications, with significant contributions to slicing techniques for concurrent Java programs, FPGA testing, and synchronous language applications. The work demonstrates strong interdisciplinary connections between computer science and neuroscience, particularly in event-related potential analysis.

Analysis of his publication history reveals dual research trajectories: computer science projects in verification systems and neuroscience publications concerning unconscious processing, ERP analysis, and brain-computer interfaces. This unusual combination suggests cross-disciplinary collaboration between IIT Bombay's computer science department and neuroscience research groups.

Ramesh has supervised four PhD students including Ambar Gadkari (working on GALS verification), M.G. Nanda (slicing concurrent Java programs), Sridhar Iyer (reachability analysis of concurrent OO programs), and A. Sowmya (autonomous robot motion specification).

His current projects include the CFDVS initiative, Design and Verification of Distributed Applications, Slicing Concurrent Programs, UML-based Specification Systems, and FPGA Testing, demonstrating sustained research activity in formal methods and verification technologies.