Markus Ferringer

Markus Ferringer is a Lecturer in the Department of Computer Engineering at Vienna University of Technology. He specializes in asynchronous logic, real-time systems, and fault-tolerant hardware design, with a focus on VLSI implementation and distributed systems.

Research Interests: His work explores the integration of asynchronous circuits into real-time systems, emphasizing fault tolerance and reliability. Key areas include self-timed logic, time-triggered protocols, and distributed clock generation.

Publications: Markus has published extensively on asynchronous hardware design, interfacing techniques, and process variation impacts. His research spans conferences and workshops such as DSN-W, DDECS, EUROCON, and Austrochip.

Projects: He contributed to the ARTS project (2007–2011) supported by the Austrian Research Promotion Agency (FFG) and the THETA project (2004–2008).