Gerald Hempel

Dr.-Ing. Gerald Hempel is a researcher at Dresden University of Technology (TU Dresden) with active contributions to computer architecture and embedded systems from 2015–2023. His work bridges hardware/software co-design through domain-specific languages and compiler techniques, primarily within the Faculty of Electrical and Computer Engineering context.

His research spans:

• Domain-Specific Languages for hardware acceleration
• Memory optimization in high-performance computing
• Reconfigurable computing using FPGAs
• Many-core and heterogeneous system design
• Bio-inspired algorithms for robust system mapping
• Racetrack memory applications in brain-inspired cognition

Publication analysis reveals consistent focus on compiler-driven hardware acceleration, particularly for computational fluid dynamics and cognitive systems. His work emphasizes memory architecture innovations (e.g., high-bandwidth memory, caching) and bio-inspired robustness techniques, often through collaborations like the EVEREST consortium for compilation frameworks.

No scientific awards were documented in the source material.

No student advising or grant information was provided in the available texts.

Dr. Hempel collaborates within TU Dresden's research ecosystem, notably with the EVEREST consortium and chairs including Compiler Construction and Emerging Electronic Technologies. His work on tools like Mocasin demonstrates active participation in teams developing rapid prototyping frameworks for heterogeneous multi-core systems and FPGA-based accelerators.