Geoffrey Nelissen

Geoffrey Nelissen is a researcher scientist at CISTER, part of the Instituto Superior de Engenharia do Porto (ISEP) within the Polytechnic Institute of Porto (IPP). He holds a PhD in Electrical Engineering from Université Libre de Bruxelles (ULB, Belgium), awarded in 2012 under Professors Joël Goossens and Dragomir Milojevic. His research focuses on real-time scheduling theory, embedded systems, and multi-core architectures, with significant contributions to network-on-chip (NoC) design and cache contention analysis. He has been actively involved in advancing scheduling algorithms for real-time systems, particularly in partitioned and global scheduling contexts.

Education: MSc in Electrical Engineering (ULB, 2008), PhD in Real-Time Systems (ULB, 2012).

Research Interests: Real-Time Scheduling Theory, Real-Time Operating Systems, Multiprocessor/Multi-Core Architectures, Network-on-Chip (NoC), Embedded Systems, Cache Contention Analysis. His work emphasizes practical solutions for scheduling challenges in heterogeneous and real-time environments, addressing issues like memory contention, bus arbitration, and cache interference.

Publications: Recent work includes advancements in 3-Phase Task Model analysis, deflection-based NoC architectures (e.g., IPDeN), and holistic memory contention frameworks. His contributions span conferences like RTCSA, RTSS, and ECRTS, with a focus on bridging theoretical scheduling models and practical embedded system implementations.

Awards: Multiple Outstanding Paper Awards at RTCSA 2020, RTNS 2017, and ECRTS 2016, alongside Best Presentation and Open Problem Awards. His research has been recognized for its impact on real-time system reliability and performance.

Labs/Teams: Active member of the CISTER Research Centre, focusing on embedded systems and real-time computing. Collaborates with international researchers on topics like FPGA-based NoC design and mixed-criticality systems.