Daniel Müller-Gritschneder

Prof. Daniel Müller-Gritschneder is a Full Professor of Computer Architecture at TU Wien's Institute of Computer Engineering (Faculty of Informatics) since 2024. Previously, he held roles as research group leader at TU Munich's Chair of Electronic Design Automation and acting professor for Real-Time Systems at TU Munich. He earned his Dipl.-Ing. (2003), Dr.-Ing. (2009), and Habilitation (2019) from TU Munich.

His research focuses on Electronic System Level Design, RISC-V domain-specific architectures, embedded ML compiler toolchains, functional safety, and hardware security. He collaborates extensively with industry partners like Infineon, Bosch, BMW, and Mercedes. Active in the RISC-V community, he co-initiated the RISC-V Summit Europe and serves on steering committees for conferences such as DAC, ICCAD, and DATE.

Key Research Themes:

• RISC-V ISA extensions and toolchain development
• Edge AI/ML on embedded systems
• Secure and safety-critical processor design
• High-level synthesis and performance simulation

Awards:

• Best Student Paper Award (2024), IEEE Winter Conference on Computer Vision
• Habilitationspreis (2019), TU Munich Alumni Association
• Senior IEEE Member (2019)

Teaching includes courses like 'High-Level Synthesis', 'Computer Organization', and 'Embedded Systems Design'. Current projects involve lightweight software for IoT devices and pre-silicon validation of safety-critical RISC-V systems. His work bridges academic research with industrial application through collaborative projects and open-source tool development.