Find Academic Supervisors

• Neuromorphic Computing
• Memristor-Based Architectures
• Energy-Efficient AI Hardware
• +7 more

Said Hamdioui serves as a full Professor in the Department of Computer Engineering within the Faculty of Electrical Engineering, Mathematics and Computer Science at Delft University of Technology. His research focuses on cutting-edge hardware architectures for neuromorphic computing and energy-efficient AI acceleration, with particular emphasis on memristor-based systems, emerging memory technologies, and fault-tolerant designs for edge applications. His research interests span Neuromorphic Computing , Memristor-Based Architectures , and Energy-Efficient AI Hardware , addressing critical challenges in hardware security, computation-in-memory, and reliable edge AI deployment. Recent work demonstrates significant advancements in RRAM/FeFET testing methodologies, spiking neural network implementations, and spin wave computing alternatives to traditional CMOS. His publications reveal strong trends toward real-world deployment of brain-inspired hardware with practical constraints like power efficiency, testability, and security. Award highlights include: DATE'20 Best Paper Award DFT'21 Outstanding Student Paper ETS 2021 Best Paper Award LATS 2018 & 2022 Best Paper Awards Professor Hamdioui actively contributes to the research community through editorial roles at IEEE Transactions on VLSI Systems , IEEE Design & Test , and Journal of Electronic Testing from 2017-2018. His leadership in multi-partner projects like CONVOLVE and NEUROKIT2E demonstrates strong industry-academia collaboration for edge AI solutions. Current work shows increasing focus on practical deployment challenges including in-field fault monitoring, security vulnerabilities in neuromorphic systems, and realistic brain simulation frameworks.

• VLSI Testing
• Circuit Design
• Test Compaction
• +7 more

Irith Pomeranz is the Cadence Professor of Electrical and Computer Engineering at Purdue University's College of Engineering. Her research focuses on advanced testing methodologies for VLSI circuits, including functional test compaction, fault diagnosis, and built-in self-test (BIST) techniques. She is affiliated with the Department of Electrical and Computer Engineering and has contributed extensively to improving test efficiency and fault coverage in digital circuits. Her work addresses challenges such as aging effects, transition faults, and path delay faults, with a particular emphasis on practical implementations for industrial applications. Key areas of interest include modular test sequences, configuration-based compaction, and dynamic testing strategies for in-field environments. She has developed algorithms for dual-target diagnostic testing and synchronization mechanisms for online fault detection in logic blocks. Research Trends in her publications emphasize innovations like storage-based BIST schemes, adaptive test scheduling, and shared test data architectures. These advancements aim to reduce test data volume, improve fault coverage, and enhance reliability in modern integrated circuits. Her work often bridges theoretical foundations and practical hardware implementations. Grants & Advising : While specific grants or student advisees are not listed, her prolific publication record indicates active involvement in research projects and graduate supervision within Purdue's ECE department. Labs & Teams : Her contributions are likely tied to Purdue's VLSI and testing research groups, though specific lab affiliations are not detailed in the provided text.

• Testability
• Built-in Self Test (BIST)
• Digital Circuit Testing
• +3 more

Professor Jacob Savir is a distinguished academic in the Department of Electrical and Computer Engineering at the New Jersey Institute of Technology . He specializes in testability, built-in self-test (BIST), and fault detection for digital and analog circuits. His work focuses on improving integrated circuit testing methodologies, including BIST pretesting, defect level analysis, and reliability optimization in safety-critical systems. His research interests span BIST architectures, delay fault analysis, analog circuit testing, and power-constrained test synthesis . He has contributed extensively to the development of testing algorithms for embedded memories, scan designs, and fault diagnosis in complex systems. Notable contributions include studies on the impact of BIST pretesting on IC defect levels and yield optimization. His work bridges theoretical advancements with practical applications in aerospace and industrial electronics. Despite no awards listed, his substantial citation count (1,897) and h-index (22) reflect his influential contributions to the field. Prof. Savir has collaborated on 114 research outputs since 1977, with a focus on enhancing circuit testability and reliability across domains like FPGA-based systems and embedded memory diagnostics. His research emphasizes both academic rigor and industrial relevance, addressing challenges in modern VLSI design and testing.

• VLSI Design
• Built-In Self-Test (BIST)
• Test Data Compression
• +7 more

Chr. Kavousianos is an Assistant Professor in the Department of Informatics at the University of Ioannina, Greece. He is actively engaged in research and teaching in the fields of VLSI design, testability, and low-power testing. He has been involved in major national and international research programs such as Heracleitus II, Pythagoras, and NSF-SRC (USA). Research Interests: His research focuses on advanced techniques in built-in self-test (BIST), test data compression, scan-based testing, fault tolerance, and embedded control architectures. He explores methods to reduce test data volume, power consumption during testing, and improve defect coverage in integrated circuits. Publication Trends: His recent publications (2004–2011) show a strong trend toward defect-aware testing, power-efficient test compression, and multicore SoC testing. He frequently collaborates with leading researchers, including Prof. Krishnendu Chakrabarty (Duke University). His work on multilevel Huffman coding and reseeding techniques has been highly influential, with one paper among the most accessed in 2004. Special Distinction for Excellent Academic Performance from TEE, 1996 Doctoral Scholarship 'In Memory of Professor Maritsa', 1999 Postdoctoral Scholarship from IKY, 2002 Advising and Grants: He has supervised multiple postdoctoral researchers, PhD candidates (e.g., Vasilis Tenentes, Emmanouil Kalligeros), and master’s students. He has led research projects such as 'Embedded Control Architectures' (Heracleitus II) and 'Design Techniques for Embedded Self-Control Circuits' (Pythagoras II). His international collaboration with Duke University included a postdoctoral research role in 2009. Labs and Teams: He leads a research group at the University of Ioannina with postdocs, PhD students, and visiting professors, including Prof. Krishnendu Chakrabarty. His team works on cutting-edge VLSI testing and design methodologies.

Krishnendu ChakrabartyView profile

Professor

• Testing and Design-for-Testability of Integrated Circuits
• Digital Microfluidics
• Biochips
• +3 more

Krishnendu Chakrabarty is the John Cocke Distinguished Professor of Engineering and Professor of Computer Science at Duke University, chairing the Department of Electrical and Computer Engineering. His research focuses on integrated circuits testing, microfluidics, biochips, and cyberphysical systems. He holds honorary titles from institutions globally and has received over a dozen best-paper awards. Education: B.Tech from IIT Kharagpur (1990), M.S.E. and Ph.D. from University of Michigan (1992, 1995). Awards include Humboldt Research Award (2013), IEEE Computer Society Technical Achievement Award (2015), and AAAS Fellowship (2018). Research explores fault diagnosis in hardware, smart manufacturing, and biochip automation. His cyberphysical systems work includes hybrid microfluidic platforms for single-cell analysis and droplet-based bioassays. Collaborations with TUM-IAS focus on Microfluidic Design Automation (MDA). Editor-in-Chief of IEEE Transactions on VLSI Systems and former Editor of ACM Journal on Emerging Technologies. Active in academic leadership and interdisciplinary projects, emphasizing sustainability and advanced manufacturing.

• Reliable Hardware Design
• Electronic Design Automation
• Edge Computing
• +4 more

Dr. Abusaleh Jabir is a University Reader at the School of Engineering, Computing and Mathematics, Oxford Brookes University. He holds a DPhil in Computing from the University of Oxford and leads the Advanced Reliable Computer Systems (ARCoS) group. His research focuses on reliable hardware design, memristive nanotechnology, edge computing, and secure authentication systems. He has over 80 peer-reviewed publications and multiple patents, including innovations in error-tolerant circuits and memristive architectures. **Education**: DPhil in Computing (University of Oxford). **Research Interests**: Reliable hardware design, electronic design automation, sensing at the edge, physical uncloneable authentication, and emerging memristor technologies. His work addresses challenges in IoT, edge computing, and cybersecurity through innovative electronic systems. **Funding & Projects**: Current projects include the Leverhulme Trust-funded MONITOR gas sensor array initiative. His research has been supported by the UK Ministry of Defence, EPSRC, and Finance South East. **Awards & Patents**: Multiple patents granted, including EU 17706875.6 (memristive logic) and GB 1914221.5 (reconfigurable memristive logic). Recognized with best paper awards. **Advising & Impact**: Supervised PhD students now leading semiconductor and automotive industries (e.g., Infineon Technologies, Continental Teves AG). Collaborates with academic and industrial partners globally. **Labs & Teams**: Leads the ARCoS group within the Artificial Intelligence, Data Analysis and Systems (AIDAS) Institute, fostering interdisciplinary innovation in secure and reliable electronics.

Lei WangView profile

Associate Professor

• Cyber-Physical Systems
• Aquatic Systems
• Embedded Computing with Renewable Energy
• +3 more

Lei Wang is the F. L. Castleman Associate Professor in Engineering Innovation at the University of Connecticut's School of Engineering, Department of Electrical and Computer Engineering. He holds a PhD from the University of Illinois at Urbana-Champaign (2001), an MS (1996) and BS (1992) from Tsinghua University, China. His research focuses on cyber-physical systems , embedded computing with renewable energy , and nanoscale integrated circuit design . Key areas include microbial fuel cells , memristor-based hardware security , and low-power signal processing architectures . Recent work trends involve Quantum-dot transistor applications for in-memory computing Adaptive LDPC decoder optimization Hardware security leveraging memristor properties Energy-efficient power management systems for underwater sensors Scientific recognition includes National Science Foundation CAREER Award (2010) F. L. Castleman Term Professorship in Engineering Innovation Professional roles encompass editorial and committee positions at IEEE and ACM journals. His work spans interdisciplinary domains in renewable energy integration , VLSI design , and bio-inspired computing systems .

Wen-Ben JoneView profile

Associate Professor

• VLSI system design
• low-power VLSI systems
• many-core micro-processor design
• +3 more

Wen-Ben Jone is an Associate Professor at the University of Cincinnati 's Department of Electrical Engineering & Computing Systems. He previously held positions as Assistant/Associate Professor at New Mexico Institute of Mining and Technology and Visiting Associate/Full Professor at National Chung-Cheng University, Taiwan. His research focuses on VLSI system design, low-power circuits, and fault-tolerant testing methodologies. He has advised over 70 graduate students and authored/co-authored numerous papers in top-tier journals and conferences. Education : PhD: Case Western Reserve University (Computer Engineering, 1987) MS: National Chao-Tung University (Computer Engineering, 1981) BS: National Chao-Tung University (Computer Science, 1979) Research Interests : Reliable VLSI design and testing Low-power and fault-tolerant circuits Many-core processor architectures Parallel computing and debugging tools Awards : 2003 IEEE Donald G. Fink Prize Paper Award 2008 Best Paper Award (International Symposium on Low-Power Electronics) 2012 Best Paper Award (VLSI Design, Automation & Test) Grants : $390k NSF Grant (CCF-0541103) for cache optimization techniques His work emphasizes practical solutions in VLSI testing and reliability, with a focus on low-power strategies and resilient system design.

• Trustworthy computing
• Energy harvesting
• Intelligent system design
• +7 more

Youhua Shi is a full Professor in the Faculty of Science and Engineering at Waseda University, Japan. He obtained his Doctor of Engineering from Waseda in 2005 and is an active member of IEICE, IPSJ, IEEE, and two Japanese academic societies. His research portfolio integrates trustworthy computing, hardware security of AI accelerators, energy-harvesting interface circuits for triboelectric nanogenerators, and low-power VLSI design-for-test methodologies. Education: Doctor of Engineering, Waseda University (2005) Graduate studies, Waseda University, Division of Engineering (completed 2005) Research Interests: Prof. Shi pursues trustworthy and secure silicon systems, spanning hardware Trojans in automated AI-accelerator flows, radiation-hardened latch design for soft-error resilience, and power-efficient CNN accelerators exploiting zero-gating and data-reuse techniques. Parallel work targets energy-autonomous IoT through advanced interface circuits for triboelectric nanogenerators, achieving record energy-per-cycle beyond the classical CMEO limit. Publication Trends: Recent articles (2024-2025) emphasize two thrusts: (i) security of AI/FPGA accelerators—proposing stealthy hardware-Trojan frameworks embedded within design-space-exploration flows that can misclassify up to 97% of inputs—and (ii) power electronics for triboelectric harvesters—introducing dual-output rectifiers and Bennet-doubler biasing that multiply output power >150× over conventional full-wave rectifiers, enabling battery-free IoT nodes. Scientific Awards: APCCAS Best Student Paper Award – 2020 IEEK Best Paper Award – 2012 Students & Collaboration: He has mentored numerous doctoral and master’s scholars, including Yirui Su, Chao Guo, Jinghao Ye, Lin Ye, Saki Tajima, and Masaru Oya, many of whom serve as first authors on his high-impact publications, indicating an active and productive advising role. Labs & Teams: While the text does not name a specific laboratory, his continued affiliation with Waseda University’s Faculty of Science and Engineering and his extensive project output imply he leads a research group focused on secure & energy-efficient VLSI systems, collaborating closely with colleagues such as Prof. Masao Yanagisawa and Prof. Nozomu Togawa.

Naghmeh KarimiView profile

Associate Professor

• Hardware Security
• Design-for-Trust
• Fault Tolerance
• +9 more

Naghmeh Karimi is an Associate Professor in the Department of Computer Science and Electrical Engineering at the University of Maryland Baltimore County (UMBC), where she has held this position since 2023, after serving as an Assistant Professor from 2017 to 2023. She is a recipient of the NSF CAREER Award (2020) and the Best Paper Award (2019). Her research focuses on hardware security, trustworthiness, and reliability of integrated circuits, with a particular emphasis on cryptographic devices, PUF-based authentication, and aging-related vulnerabilities. She directs the SECure, REliable and Trusted Systems (SECRETS) Lab at UMBC, which explores topics including hardware security countermeasures, fault tolerance, and AI-driven security solutions. Prior to UMBC, she was affiliated with Rutgers University, New York University, Duke University, and Yale University. Her research interests span hardware security, design-for-trust, fault tolerance, AI for security, and VLSI design. Recent work emphasizes aging effects on cryptographic circuits, PUF resilience, and digital sensor-based failure detection. Her publications address challenges in side-channel attacks, fault injection, and secure IoT frameworks. Dr. Karimi’s work is supported by sponsors, and she actively mentors Ph.D. students in hardware security and reliability. Her lab offers openings for self-motivated researchers in these areas.

Melvin A. BreuerView profile

Professor

• Computer-Aided Design of Digital Systems
• Design-for-Test
• Built-In Self-Test
• +4 more

Melvin A. Breuer is a Professor of Electrical Engineering and Computer Science at the University of Southern California (USC), holding the Charles Lee Powell Professorship. He has served as Chairman of the Department of Electrical Engineering-Systems (1991–1994) and later returned to the role, while also chairing the Faculty of USC’s School of Engineering in 1997–1998. His research focuses on computer-aided design of digital systems, design-for-test, built-in self-test, and VLSI circuits. Ph.D. in Electrical Engineering from UC Berkeley He has authored or co-authored multiple books, including Design Automation of Digital Systems: Theory and Techniques (Prentice-Hall) and Digital System Testing and Testable Design (IEEE Press). His editorial roles include Editor-in-Chief of the Journal of Design Automation and Fault Tolerant Computing and positions on the editorial boards of several journals. He has been recognized with awards such as the IEEE Computer Society’s Taylor L. Booth Education Award and USC’s Associates Award for Creativity in Research. Dr. Breuer has also delivered keynotes at international symposia and contributed to over 200 technical papers. Scientific Awards IEEE Fellow Fulbright-Hays Scholar (1972) 1991 Associates Award for Creativity in Research and Scholarship (USC) 1991 USC School of Engineering Exceptional Service Award IEEE Computer Society’s 1993 Taylor L. Booth Education Award 2000 Engineering Faculty Council Outstanding Meritorious Service Award (USC School of Engineering) Honorable Mention Paper (1997 International Test Conference) Best Paper (2000 Asian Test Symposium)

Ian DearView profile

Senior Lecturer

• Digital Systems
• Test Technology
• Optical Strain Measurement
• +3 more

Dr. Ian Dear is a Senior Lecturer in the Department of Electronic and Electrical Engineering at Brunel University's College of Engineering, Design and Physical Sciences. His research focuses on digital systems and test technology, with a strong emphasis on economic analysis and optical strain monitoring techniques for industrial applications. Position: Senior Lecturer Institution: Brunel University Department: Electronic and Electrical Engineering Contact: ian.dear@brunel.ac.uk Dr. Dear's research bridges economic modeling with electronic testing and optical strain measurement. His work targets power plant components, VLSI boards, and industrial diagnostics, prioritizing cost-effective strategies and structural health monitoring. Recent publications highlight trends in optical strain monitoring for energy systems and economic frameworks for electronic testing. These studies span power generation plants, VLSI diagnostics, and material stress analysis. Dr. Dear contributes to doctoral education modernization in Kyrgyzstan and maintains active research collaborations through Brunel University's engineering faculty.

Yadi ZhongView profile

Assistant Professor

• Applied Cryptography
• Cryptology
• Algebraic Cryptanalysis
• +7 more

Yadi Zhong is an Assistant Professor in the Department of Electrical and Computer Engineering at Auburn University, part of the College of Engineering. He holds both a Ph.D. and a Bachelor of Engineering from the same institution, reflecting a strong academic foundation in electrical and computer engineering disciplines. His research focuses on critical areas in modern cybersecurity and computational logic, including: Applied Cryptography and Cryptology Algebraic Cryptanalysis Privacy-Enhancing Cryptography Boolean Satisfiability (SAT) Solving VLSI Testing and Design for Testability These interests position his work at the intersection of hardware security, formal methods, and cryptographic protocol analysis, contributing to secure and reliable computing systems. While no recent publications are listed in the provided text, the research areas suggest a focus on both theoretical underpinnings and practical applications in secure integrated circuits and privacy-preserving technologies. There are no scientific awards mentioned in the available information. Dr. Zhong advises students within the Electrical and Computer Engineering graduate program, though specific advisees are not listed. There is no mention of externally funded grants or sponsored research projects in the current profile. He is likely involved in research labs related to cybersecurity, hardware security, or VLSI design, though specific lab affiliations are not stated.

• Design for Testability
• Automatic Test Pattern Generation
• Electronic Design Automation
• +3 more

Haluk Konuk is a Visiting Professor at the Faculty of Engineering, Özyeğin University. With a PhD in Electrical Engineering from the University of California, Santa Cruz (1996), he specializes in VLSI testing, Design for Testability, and Electronic Design Automation. He worked at Hewlett-Packard/Agilent Technologies and Broadcom Corporation for over 25 years, contributing to the development of critical internet infrastructure ASICs and processors. Since 2021, he has founded Palo Alto Test Technologies, focusing on advanced testing solutions. PhD in Electrical Engineering, University of California, Santa Cruz (1996) MS in Electrical Engineering, Case Western Reserve University (1989) BS in Electrical & Electronics Engineering, Boğaziçi University (1986) His research focuses on Design for Testability (DFT), Automatic Test Pattern Generation (ATPG), and Electronic Design Automation (EDA), addressing challenges in VLSI and CMOS circuit testing. His work includes modeling open-defects, fault simulation, and optimizing test efficiency for digital circuits. Haluk Konuk's publications span test compression, delay fault testing, and fault modeling, reflecting his long-term contributions to VLSI test methodologies. He holds 9 U.S. patents and has served on IEEE conference program committees. Fulbright Scholarship 9 U.S. Patents in VLSI Test Technology

Pinaki MazumderView profile

Professor

• CMOS VLSI design
• Semiconductor memory systems
• Quantum tunneling circuits
• +3 more

Pinaki Mazumder is Professor of Electrical Engineering and Computer Science at the University of Michigan College of Engineering. He earned his PhD from University of Illinois at Urbana-Champaign and has 25+ years of teaching experience. His research develops CMOS VLSI systems, semiconductor memories, CAD tools for quantum devices, and bio-inspired computing architectures. Innovations include testable DRAM circuits and self-healing memory compilers used industrially. He has authored books on VLSI routing, neuromorphic computing, and genetic algorithms in circuit design. His work spans quantum MOS, spintronics, and plasmonic devices. Recognition: Fellow of IEEE Fellow of American Association for Advancement of Science Dr. Mazumder has secured research funding from NSF, DARPA, DoD, and industry partners. He developed the Quantum SPICE simulator for quantum tunneling circuits and teaches courses on VLSI design, parallel architectures, and nanoelectronics.