Saghi Forouhi is an Assistant Professor at Linköping University, affiliated with the Division of Electronics and Computer Engineering (ELDA) and the Department of Electrical Engineering (ISY). Her research focuses on analog circuits, biochips, and signal processing technologies. Primary Affiliation: Linköping University School: Division of Electronics and Computer Engineering Department: Department of Electrical Engineering In 2025, she co-authored the publication Advanced CMOS Biochips , which explores intersections between CMOS technology and biomedical applications.
Alan H. Barr is a Professor of Computer Science at the California Institute of Technology (Caltech), affiliated with the Division of Engineering and Applied Science and the Computation & Neural Systems (CNS) department. He is a founding member of the Caltech Computer Graphics Group and a leader in developing mathematically rigorous methods for computer graphics and predictive modeling. His research focuses on enhancing computational modeling accuracy through approaches like interval analysis and constraint-based systems. Notable contributions include deformable models, quaternion interpolation, and cellular simulation frameworks. He has advised over 20 graduate students, many of whom became industry leaders at Pixar, Microsoft Research, and academic institutions like NYU and Brown University. Awards include the ACM SIGGRAPH Achievement Award (1988) and ACM Fellow (1995). Research Interests: Predictive modeling with error bounds Scientific visualization and MRI data analysis Biophysical systems simulation (e.g., cellular organelles) Self-assembling robotic structures for space colonization Mathematically robust computer graphics techniques Key Collaborations: Caltech Biological Imaging Center (Beckman Institute) JPL (Jet Propulsion Laboratory) New computational substrates research (quantum/DNA computing) Recent Work: Expanding into computational biology, medical imaging optimization, and high-confidence systems for managing complex computational interactions. Active in interdisciplinary projects across Caltech divisions.
Fabrizio Lombardi is the ITC Endowed Professor at Northeastern University's Department of Electrical and Computer Engineering, part of the College of Engineering. He previously held faculty positions at Texas Tech University, University of Colorado-Boulder, and Texas A&M University. He earned his B.Sc. from the University of Essex (1977), M.Sc. and Ph.D. from the University of London (1982). His research focuses on fault-tolerant computing, VLSI CAD, quantum computing, and configurable computing systems. He has led major projects like the NSF-funded Neural-Network-based Stochastic Computing Architectures for Machine Learning . He holds leadership roles including President of the IEEE Nanotechnology Council (2022-2023), IEEE Computer Society Vice President (2021), and IEEE PSPB member. His 200+ publications span IEEE Transactions on Computers, Nanotechnology, and Design & Test. Awards include IEEE Fellow, Søren Buus Outstanding Research Award, and multiple research fellowships. His work bridges theory and application, emphasizing defect-tolerant nanosystems and energy-efficient computing hardware. Recent innovations include approximate computing methodologies and secure PUF-based hardware designs.
Xuming He is an Associate Professor at the School of Information Science and Technology (SIST), ShanghaiTech University, where he leads the PLUS Lab. His research spans computer vision and machine learning with a focus on developing algorithms that operate effectively under limited supervision and evolving data conditions. His core research interests include weakly-supervised and few-shot learning for scenarios with sparse annotations, continual learning frameworks for knowledge retention during sequential task acquisition, semantic segmentation techniques for scene understanding, and multimodal vision-language representations. He emphasizes interpretable machine learning to build transparent AI systems capable of human-understandable reasoning, addressing critical challenges in model trustworthiness and deployment reliability. Recent publications reveal strong trends toward novel class discovery in long-tailed recognition scenarios, physics-informed generative modeling for scientific applications, and robust segmentation under distribution shifts. His work increasingly integrates large language models for multimodal reasoning while maintaining focus on efficiency in resource-constrained environments like robotic grasping and medical imaging analysis. He actively mentors students, having supervised Qian He to PhD completion and Chuanyang Hu to Master's degree in 2023. He welcomes prospective graduate students through ShanghaiTech's Computer Science & Technology program and offers undergraduate research projects requiring minimum six-month commitments. The PLUS Lab under his direction drives innovation in learning under supervision constraints, with recent work spanning medical tumor analysis, cross-view geolocation, photonic computing, and semiconductor design verification. The lab's research bridges theoretical advances with practical applications across healthcare, robotics, and scientific discovery domains.
Carl-Mikael Zetterling is a Professor and Head of Department at Kungliga Tekniska Högskolan (KTH) in Stockholm, Sweden, affiliated with the School of Electrical Engineering and Computer Science (ICT) and the Electronics and Embedded Systems department. His research focuses on process technology and device design for high-temperature, high-power silicon carbide (SiC) electronics, expanding into SiC-based analog and integrated circuits. He has authored over 300 publications, including books on SiC process technology and plagiarism prevention. Dr. Zetterling has held leadership roles such as Vice Dean of the School of ICT (2013–2017) and teacher representative on KTH's faculty board. He has collaborated internationally at Stanford University, Kyoto University, and Kyoto Institute of Technology. His work addresses applications in extreme environments, including Venus exploration and fusion reactor monitoring, with a focus on radiation tolerance and thermal resilience. The 15 most recent publications highlight trends in wide bandgap semiconductors, gamma irradiation effects on SiC devices, and high-temperature integrated circuits. His articles span structural health monitoring with machine learning, novel SiC diode designs, and radiation-hardened electronics. Key contributions include advancements in self-aligned contacts, trench MOSFETs, and compact modeling for extreme conditions. While no formal awards are listed, his roles in technical program committees (TMS Electronic Materials Conference, IEEE SISC Conference) and editorial work demonstrate significant academic service. He teaches courses ranging from digital design to high-temperature electronics, overseeing degree projects in embedded systems, communication, and nanotechnology.
Sule Ozev is a Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University (ASU). She holds a Ph.D. in Computer Science and Engineering from the University of California, San Diego (2002), and has been a faculty member since 2008. Her research focuses on analog and mixed-signal circuit testing, fault-tolerant systems, and RF circuit reliability. She has published over 100 papers and holds a U.S. patent. Notable awards include the NSF CAREER Award (2006) and the ASU Joseph Palais Distinguished Faculty Scholar Award (2023-2024). Her education includes: Ph.D., Computer Science and Engineering, UC San Diego (2002) M.S., Computer Science and Engineering, UC San Diego (1998) B.S., Electrical Engineering, Bogazici University, Turkey (1995) Research Interests: Self-test and calibration techniques for analog/RF circuits, fault simulation, and reliability enhancement. Recent work includes BIST solutions for power management units, MEMS sensor calibration, and IoT security. Publications span RF impedance measurement, low-power systems, and marine sensor applications. Awards also include best paper recognitions at IEEE VLSI Test Symposium (2022) and European Test Symposium (2019). Grants include NSF-funded projects on adaptive test strategies and collaborative research on sensor networks. Service roles include associate editor for IEEE Transactions on VLSI Systems and program chairs for major conferences.
Dr. Patrick W. C. Ho is a Lecturer in the Department of Electrical & Computer Systems Engineering (ECSE) at Monash University Malaysia School of Engineering. He holds a PhD in Electronics Engineering from the University of Nottingham Malaysia Campus (2016), with research focusing on non-volatile FPGA architectures using memristors. His academic journey includes roles as a Scholarly Teaching Fellow and unit coordinator for courses like ECE2131 Electrical Circuits and ECE4063 Large Scale Digital Design. He has industry experience with Intel Microelectronics and Altera Corporation, alongside teaching A-level Physics at Methodist College Kuala Lumpur. Education: BEng (First Class Honours) in Engineering (2009) MSc in Science (2012) PhD in Electronics Engineering (2016) Research Interests: Dr. Ho specializes in memristor-based non-volatile memory systems, VLSI design, and FPGA architectures. His work bridges hardware design with emerging materials, as seen in his Q1 journal article on memristive LUTs. Collaborations with CAD-IT expand his focus into AI, image processing, and object recognition. Recent projects include studies on memristor substrate performance (2023–2026) and UAV communication reliability (2021–2024). Teaching and Industry Engagement: As ECSE’s Industrial Training Advisor and IAP representative, he actively connects academic curricula with industry needs. His teaching spans foundational engineering courses and advanced digital design modules. Labs and Collaborations: Active in CAD-IT partnerships for student FYP co-sponsorship. Research groups focus on nanotechnology, machine learning integration in UAV systems, and memristor material analysis.
Yung-Hsiang Lu is a Professor of Electrical and Computer Engineering at Purdue University's Elmore Family School of Electrical and Computer Engineering. His research focuses on mobile/cloud computing, energy-efficient computing, and image/video processing. He holds a BSEE from National Taiwan University (1992), an MSEE (1996), and a PhD (2002) from Stanford University. Dr. Lu's academic background includes significant contributions to VLSI and circuit design, with primary emphasis on computer engineering. His work spans theoretical and applied domains, including optimizing neural networks for edge devices, securing deep learning models, and leveraging large language models for software development. Recent research trends in his articles emphasize energy efficiency in AI systems, interdisciplinary applications of transformers (e.g., music analysis), and challenges in model interoperability and security. His publications also highlight innovations in global camera networks and real-time visual data analysis. While no specific grants or awards are explicitly mentioned, his extensive list of publications reflects sustained academic engagement. His educational contributions include developing C programming resources and teaching large-scale image processing using global camera networks. Dr. Lu's professional address is at Purdue's Materials and Electrical Engineering Building in West Lafayette, Indiana, where he maintains an active research lab focused on embedded systems and low-power computing innovations.
Prof. Dr.-Ing. H. Siegfried Stiehl is a retired Senior Professor (until Sept 2021) at the Department of Informatics, University of Hamburg. He previously held roles including Dean of the Faculty of Mathematics, Computer Science, and Natural Sciences (2001–2006), Vice President for Research (2007–2013), and Head of the Image Processing Research Group. His academic journey includes a PhD from TU Berlin (1980) and a Habilitation in Computer Vision (1987). Education: 1973: Ing. Degree in Ingenieur-Informatik, Fachhochschule Furtwangen 1976: Diploma in Computer Science, TU Berlin 1980: Dr.-Ing. Dissertation on medical image processing, TU Berlin Research focuses on Computer Vision , Computational Neuroscience , and Cognitive Science , with contributions to medical image registration, 3D landmark detection, and biomechanical modeling. Key projects include the EU-funded 'COVIRA' consortium (1989–1995) and leadership in the SFB 950 'Manuscript Cultures' project (2015–2019). His 110+ publications span biomedical image registration, elastic deformation algorithms, and real-time signal processing. Notable collaborations include work with institutions like the University of Pennsylvania, University of Birmingham, and Philips Research. Leadership roles include organizing scientific events, serving on editorial boards (e.g., Biological Cybernetics), and founding the Interdisciplinary Nanoscience Center Hamburg (INCH) in 2001. His research has addressed challenges in neurosurgical interventions, VLSI implementation of neural networks, and interdisciplinary education.
Professor Ahmed Hemani is a faculty member at the Division of Electronics and Embedded Systems, KTH Royal Institute of Technology, affiliated with the Digital Futures Faculty. He holds the role of PI for the project 'New Chip Architectures for Industrial Vision' and leads research in reconfigurable computing, memristor-based systems, and hardware acceleration for AI and edge computing. His work bridges theoretical computer science with practical VLSI design and embedded systems development. He actively contributes to cross-disciplinary initiatives at Digital Futures, a joint center with Stockholm University and RISE Research Institutes of Sweden focused on digital innovation. His research emphasizes scalable FPGA/HPC architectures, low-power neuromorphic systems, and optimization techniques for custom silicon solutions. Current projects include a Lego-inspired edge AI framework and memristor-driven MIMO acceleration. Teaching responsibilities span advanced courses in SOC design, digital system verification, and embedded systems. He supervises advanced-level degree projects across computer engineering and ICT innovation specializations, emphasizing hands-on hardware-software co-design methodologies. Recent publications highlight innovations in memristor applications, FPGA-based acceleration, and reconfigurable architectures for neural networks and bioinformatics. His work addresses challenges in dark silicon utilization, energy-efficient computation, and high-performance embedded systems.
Yong-Bin Kim is a Professor in the Department of Electrical and Computer Engineering at Northeastern University, part of the College of Engineering. He has held prior positions at Intel Corp., Hewlett Packard Co., Sun Microsystems, and the University of Utah. His research focuses on integrated circuit design, nanoelectronics, bio-chip interfaces, and low-power VLSI systems. He has contributed to initiatives like the HPVLSI Lab and Microsystems and Electron Devices Lab. Education includes a B.S. in Electronic Engineering from Sogang University (Seoul, South Korea), an M.S. from the New Jersey Institute of Technology, and a Ph.D. in Computer Engineering from Colorado State University (1996). Research interests encompass high-speed low-power VLSI design, system-on-chip (SoC), physical VLSI CAD, and nanoelectronics. Specific areas include bio-sensor interface circuits, electronic neuron design, and adaptive robot controllers. Key projects involve compact power-efficient integrated circuits and high-speed transceiver design. Outstanding Paper Award, 2020 IEEE ISOCC South Korean Patent for Autonomous Impedance Calibration (2021) Best Paper Award, 2016 International SoC Design Conference Patent for Improved Receiver Circuit (2020) Patent for Method to Detect Trojan Circuits (2018) Advisees include graduate student Yixuan He. He has led research projects funded by Winchester Technology and Hynix Semiconductor, focusing on semi-self-calibration transceivers and tunable RF inductors. Labs include the HPVLSI Lab and Microsystems and Electron Devices Lab at Northeastern University, which focus on high-speed/low-power IC design and microfabrication technologies.
Jae S. Lim is a Professor of Electrical Engineering at the Massachusetts Institute of Technology (MIT), affiliated with the Department of Electrical Engineering and Computer Science (EECS). He has been a faculty member since 1978 and serves as Director of the Advanced Telecommunications Research Program. Research Interests: Dr. Lim specializes in Digital Signal Processing Image and Video Processing Speech Enhancement Telecommunications Applications Scientific Awards: He has received numerous honors, including HO-AM Laureate in Engineering Harold E. Edgerton Faculty Achievement Award Fellow of the IEEE Inductee of the Consumer Technology Hall of Fame 1997 Emmy Engineering Award
Professor Ahmet Bindal is a faculty member in the Department of Computer Engineering at San José State University . He earned his B.S. in Electrical Engineering from Bogazici University, Turkey, followed by M.S. and Ph.D. degrees from the University of California, Los Angeles. Industry Experience : 20 years at IBM, Intel, Philips, and Cadence Design Systems. Current Research : Nano-scale electron devices, silicon nanowire transistors, robotics, and VLSI architecture. Research Trends : His work focuses on silicon nanowire transistors for VLSI, FPGA, and robotics. Key themes include low-power/high-speed integrated circuits , dynamic logic design , neuromorphic engineering , and advanced semiconductor processing . Patents and Publications : He holds four U.S. patents (three with IBM, one with Intel). His 30+ journal and conference publications span nanowire transistors, FPGA architecture, robotics, and semiconductor process modeling. Teaching Contributions : Developed an undergraduate System-on-Chip (SoC) course and a MOSFET design laboratory at SJSU. Books Authored : Fundamentals of Computer Architecture and Design (Springer, 2017). Electronics for Embedded Systems (Springer, 2017). Silicon Nanowire Transistors (Springer, 2017).
Shawki M. Areibi is a Professor and Area Head of Engineering Systems and Computing in the School of Engineering at the University of Guelph. His research focuses on VLSI Physical Design Automation, Reconfigurable Computing Systems, and Hardware/Software Co-design for Embedded Systems. He leads efforts in developing advanced algorithms for CAD tools, FPGA design, and machine learning applications. His work addresses challenges in VLSI layout optimization, parallel processing, and embedded systems design. Affiliations: AI Affiliated Faculty, Area Heads, Computer Engineering, Engineering Systems and Computing Research. Research Interests: VLSI Circuit Layout, Reconfigurable Computing, Machine Learning, and FPGA-based Accelerators. His research integrates meta-heuristics like Genetic Algorithms and Tabu Search to solve complex optimization problems. He has contributed to hardware acceleration frameworks for machine learning algorithms and embedded systems, with applications in domains like signal processing and data mining. His recent work includes congestion-estimation models for modern FPGAs and analytic placement tools for ultra-scale architectures. Publications span VLSI design, reconfigurable computing, and machine learning, emphasizing algorithmic innovation and hardware-software co-design. His students have explored topics ranging from FPGA placement to domain adaptation in remote sensing. Grants and Advising: Advises graduate and undergraduate students on projects involving FPGA acceleration, machine learning, and embedded systems. His labs focus on developing next-generation CAD tools and hardware accelerators.
Professor Jacob Savir is a distinguished academic in the Department of Electrical and Computer Engineering at the New Jersey Institute of Technology . He specializes in testability, built-in self-test (BIST), and fault detection for digital and analog circuits. His work focuses on improving integrated circuit testing methodologies, including BIST pretesting, defect level analysis, and reliability optimization in safety-critical systems. His research interests span BIST architectures, delay fault analysis, analog circuit testing, and power-constrained test synthesis . He has contributed extensively to the development of testing algorithms for embedded memories, scan designs, and fault diagnosis in complex systems. Notable contributions include studies on the impact of BIST pretesting on IC defect levels and yield optimization. His work bridges theoretical advancements with practical applications in aerospace and industrial electronics. Despite no awards listed, his substantial citation count (1,897) and h-index (22) reflect his influential contributions to the field. Prof. Savir has collaborated on 114 research outputs since 1977, with a focus on enhancing circuit testability and reliability across domains like FPGA-based systems and embedded memory diagnostics. His research emphasizes both academic rigor and industrial relevance, addressing challenges in modern VLSI design and testing.
