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Ambrose Adebayo AdegbegeView profile

Professor

• Constrained Control
• Model Predictive Control
• Embedded Systems
• +3 more

Ambrose Adegbege serves as Professor of Electrical and Computer Engineering and Coordinator for Engineering Science at The College of New Jersey (TCNJ), where he directs the Laboratory for Embedded Control and Optimization (LECO). A Professional Engineer and IEEE member, he holds leadership roles including Faculty Advisor for the National Society for Black Engineers since 2013. Education: Ph.D. in Electrical and Electronic Engineering, The University of Manchester (2011) M.Sc. in Electrical and Electronics Engineering, The University of Manchester (2006) B.Sc. in Electronic and Electrical Engineering, Obafemi Awolowo University (2004) Professor Adegbege's research centers on constrained control systems , fast optimization algorithms , and analog VLSI circuits for embedded implementations . His work bridges theoretical control theory with hardware design, focusing on real-time model predictive control (MPC) for input-constrained systems. Key innovations include analog solvers for MPC, inexact optimization methods, and anti-windup techniques that maintain stability under physical limitations. Analysis of his 15 most recent publications (2018-2026) reveals a dominant focus on hardware-accelerated MPC implementations, with 70% addressing analog/digital architectures for real-time control. His work consistently tackles computational bottlenecks through novel primal-dual dynamics (40% of publications) and constrained optimization (60%), demonstrating strong industry relevance in robotics and renewable energy systems. Scientific Awards: Fulbright Fellowship (2023) Carnegie African Diaspora Fellowship (2021) Excellence in Student Mentoring Award (2023) SOSA Award (2023) Four consecutive Engineering Research Prizes (2018-2021) Secured $432,235 in external funding including an NSF grant for ultra-fast embedded control architectures ($196,380) and a DOD instrumentation grant ($235,855). His mentoring excellence is evidenced by sustained NSBE leadership and student co-authorship on 12 publications since 2018. Current research in LECO integrates FPGA and analog VLSI to overcome computational barriers in safety-critical control systems. LECO advances embedded control through three core thrusts: analog optimization circuits, constrained primal-dual dynamics, and hardware/software co-design. Recent projects include quadruple-tank system implementations and renewable energy grid controllers developed with MIT collaborators during his Masdar Institute postdoc.

• Integrated Circuits
• Mixed-Signal Computing
• Neural Recording Systems
• +1 more

Boris Murmann is Professor at Stanford University, specializing in integrated circuit design, mixed-signal computing, and energy-efficient AI hardware. His research advances neural interface technologies, analog design automation, and tinyML systems. Recent work develops ultra-low-power neural recording ICs for brain-computer interfaces, RRAM-based memory systems, and open-source semiconductor design frameworks. Publications demonstrate innovations in compressive sensing for neural data, hardware-algorithm co-design, and reinforcement learning for analog circuit synthesis. Significant contributions include Medusa (TinyML processor), EMBER (RRAM macro), and methodologies for coarsely-quantized computer vision and analog design automation.

Austin RovinskiView profile

Assistant Professor

• Computer Architecture
• VLSI
• Electronic Design Automation (EDA)
• +5 more

Austin Rovinski is an Assistant Professor in the Department of Electrical and Computer Engineering at New York University’s Tandon School of Engineering. He specializes in chip design, electronic design automation (EDA), and open-source hardware methodologies. His research focuses on VLSI design, domain-specific accelerators, and chiplet-based systems. Prior to NYU, he held a postdoctoral position at Cornell University and earned all his degrees (Ph.D., M.S., and B.S.) from the University of Michigan. Education: Ph.D., Electrical Engineering, University of Michigan - Ann Arbor Master’s, Electrical Engineering, University of Michigan - Ann Arbor Bachelor’s, Electrical Engineering, University of Michigan - Ann Arbor Research Focus: Developing open-source EDA frameworks like OpenROAD Optoelectronic interconnect systems for 2.5D packaging Agile hardware design methodologies Reconfigurable sparse matrix accelerators RISC-V-based manycore processors (e.g., Celerity project) Key Contributions: Austin led the development of the OpenROAD RTL-to-GDS flow and contributed to the Sirius and Celerity projects. His work emphasizes reproducibility, democratizing chip design through open-source tools. Awards: IEEE Micro Top Picks (2015) Michigan EECS Outstanding Research Award (2016) NSF Graduate Research Fellowship Honorable Mention (2017, 2018) Advising & Grants: Actively mentors graduate students in chip design and EDA. His research is supported by NYU’s Tandon School of Engineering and collaborations with industry partners. Labs & Teams: Core contributor to the OpenROAD project, part of NYU’s hardware design and EDA initiatives, and collaborator on the Celerity manycore processor project.

Ameer AbdelhadiView profile

Assistant Professor

• Hardware Acceleration
• Neurotechnology
• Reconfigurable Computing
• +4 more

Dr. Ameer Abdelhadi is an Assistant Professor in the Department of Electrical and Computer Engineering at McMaster University. His research focuses on application-specific custom-tailored computer architectures, hardware-efficient deep learning, neurotechnology, and reconfigurable computing. He holds a PhD from the University of British Columbia and has held academic positions at the University of Toronto, Imperial College London, and Simon Fraser University, alongside industry experience in semiconductor design. Education: PhD in Computer Engineering (University of British Columbia, 2016). Research Interests: Hardware acceleration for machine learning and neurotechnology Reconfigurable computing and FPGAs/ASICs Asynchronous circuits and synchronization protocols VLSI physical design and CAD algorithms Publications span high-impact venues such as IEEE Journal of Solid-State Circuits, IEEE Hot Chips, and IEEE Micro. Notable achievements include the 2017 Best Paper Award at ASYNC for work on synchronization FIFOs. Teaching includes COMPENG 4DV4 (VLSI System Design) and ELECENG 4OI6B (Engineering Design). His lab focuses on advancing hardware systems for next-generation applications in AI and biomedical engineering.

• Computer Science
• Artificial Intelligence
• Machine Learning
• +9 more

Jim Torresen is a Professor at the Norwegian University of Science and Technology (NTNU), specializing in Computer Science, Artificial Intelligence, and Robotics. He earned his M.Sc. and Dr.ing. (Ph.D.) in computer architecture and design from NTNU in 1991 and 1996 respectively, followed by industry experience in hardware design before transitioning to academia in 1999. Research Interests: His work spans Machine Learning, Evolvable Hardware, and Ethical AI, with notable contributions to music technology, facial expression recognition, and healthcare monitoring systems. He actively explores interdisciplinary applications of AI in creative domains and clinical environments. Publications & Editorial Roles: Torresen has published extensively in journals like Frontiers in Artificial Intelligence and Genetic Programming and Evolvable Machines . He serves as a Topic Editor for Frontiers in Explainable AI and has editorial roles in robotics and biomedical AI domains.

Eby G. FriedmanView profile

Professor

• VLSI Design
• Integrated Circuit Design
• Low Power CMOS
• +4 more

Eby G. Friedman is a Professor in the Department of Electrical and Computer Engineering at the University of Rochester, where he has served since 1991 as director of the High Performance VLSI/IC Design and Analysis Laboratory. He concurrently holds a visiting professor position at the Technion - Israel Institute of Technology, directing the Technion Advanced Circuits Research Center (ACRC). His research specializes in high performance synchronous digital and mixed-signal microelectronic design with applications in high-speed portable processors and low-power wireless communications. Core focus areas include CMOS circuit design, clock/power distribution networks, interconnect synthesis, substrate noise mitigation, pipelining techniques, and 3-D integration methodologies. His work bridges theoretical frameworks with practical implementations in VLSI systems. Scientific Awards and Honors IEEE Fellow Distinguished Lecturer of the IEEE CAS Society Dr. Friedman has authored or edited 16 books and nearly 500 publications, establishing foundational contributions in clock distribution and power delivery networks. He maintains significant editorial leadership as Editor-in-Chief of the Microelectronics Journal, past Editor-in-Chief of IEEE Transactions on VLSI Systems, and serves on the editorial boards of the Journal of Low Power Electronics, Journal of VLSI Signal Processing, Journal of Low Power Application and Circuits, and Proceedings of the IEEE. His laboratory directs cutting-edge research in high-speed circuit design and 3-D integration architectures.

• Microelectronics
• Analog/Digital Circuit Design
• Ultra Low Power Circuits
• +1 more

Snorre Aunet is a Professor at the Department of Electronic Systems at the Norwegian University of Science and Technology (NTNU), with additional roles as an Adjunct Professor at the Department of Informatics, University of Oslo. His academic career spans institutions in Norway, Germany, and the USA, including sabbaticals at Bielefeld University and University of California, San Diego. Education: Electronics Engineering (Trondheim Technical College, 1987), Informatics (UiO, 1993), and Physical Electronics (NTNU, 2002) Research Focus Dr. Aunet specializes in ultra-low-power mixed-signal integrated circuits and nanoscale CMOS technologies . His work includes innovative MEMS transducer designs for energy harvesting, digital IC development, and robust circuit solutions for emerging semiconductor challenges. Recent Publications His recent contributions include advancements in MEMS technology for sustainable energy systems, editorial leadership at NorCAS conferences, and policy discussions on the European Chips Act. These reflect expertise in both cutting-edge design and strategic technology development. Scientific Recognition 2019: Elected to Norwegian Academy of Technical Sciences (NTVA) 2015: Best Paper Award at Asia Symposium on Quality Electronic Design 2006: IEEE Senior Member (Electron Devices Society) 2003: Best Poster Award at Int'l Conf. on Evolvable Systems Leadership & Grants He has chaired multiple IEEE conferences and contributed to projects like Robust Ultra-Low-Power Circuits for Nano-Scale CMOS (NTNU/University of Paderborn). His career combines academic leadership with industry collaboration through Nordic Semiconductor and international research councils.

• Neuromorphic Computing
• Memristor-Based Architectures
• Energy-Efficient AI Hardware
• +7 more

Said Hamdioui serves as a full Professor in the Department of Computer Engineering within the Faculty of Electrical Engineering, Mathematics and Computer Science at Delft University of Technology. His research focuses on cutting-edge hardware architectures for neuromorphic computing and energy-efficient AI acceleration, with particular emphasis on memristor-based systems, emerging memory technologies, and fault-tolerant designs for edge applications. His research interests span Neuromorphic Computing , Memristor-Based Architectures , and Energy-Efficient AI Hardware , addressing critical challenges in hardware security, computation-in-memory, and reliable edge AI deployment. Recent work demonstrates significant advancements in RRAM/FeFET testing methodologies, spiking neural network implementations, and spin wave computing alternatives to traditional CMOS. His publications reveal strong trends toward real-world deployment of brain-inspired hardware with practical constraints like power efficiency, testability, and security. Award highlights include: DATE'20 Best Paper Award DFT'21 Outstanding Student Paper ETS 2021 Best Paper Award LATS 2018 & 2022 Best Paper Awards Professor Hamdioui actively contributes to the research community through editorial roles at IEEE Transactions on VLSI Systems , IEEE Design & Test , and Journal of Electronic Testing from 2017-2018. His leadership in multi-partner projects like CONVOLVE and NEUROKIT2E demonstrates strong industry-academia collaboration for edge AI solutions. Current work shows increasing focus on practical deployment challenges including in-field fault monitoring, security vulnerabilities in neuromorphic systems, and realistic brain simulation frameworks.

Nicola NicoliciView profile

Professor

• Digital Integrated Circuit Design
• Hardware Testing
• Post-Silicon Validation
• +7 more

Nicola Nicolici is a Professor in the Department of Electrical and Computer Engineering at McMaster University. His research focuses on methods and algorithms for the design of digital integrated circuits and systems, with significant contributions in manufacturing test, post-silicon validation and debug. His work has expanded to include embedded systems, low-energy computing, and custom hardware-accelerated computing systems. Professor Nicolici's research interests span multiple areas of digital system design and validation. His early work focused on manufacturing test methodologies and power-aware testing strategies for integrated circuits. More recently, he has made significant contributions to post-silicon validation techniques, including constrained-random stimuli generation, trace signal selection, and bit-flip detection. His research has evolved to address emerging challenges in embedded computing systems, low-energy design, and specialized hardware acceleration for various applications including deep neural networks and signal processing. His recent publications reveal a strong trend toward hardware acceleration for specialized computing tasks. The research spans matrix multiplication algorithms (Strassen and Karatsuba), memory system optimization (DDR5 calibration), FPGA-based radar processing, and neural network acceleration. His work consistently bridges theoretical algorithm development with practical hardware implementation considerations, particularly focusing on precision analysis, fault tolerance, and energy efficiency. The research demonstrates a clear progression from traditional digital circuit testing to more complex system-level validation and acceleration techniques. Professor Nicolici has been actively involved in teaching courses related to system-on-chip design and test, digital systems, and embedded systems. His teaching portfolio includes advanced courses such as System-on-Chip (SOC) Design and Test and Digital Systems Design , reflecting his expertise in the field. While specific grant information isn't detailed in the provided text, his extensive publication record suggests ongoing research funding support. His research has contributed significantly to the fields of digital circuit testing, post-silicon validation, and hardware acceleration. The work has practical applications in semiconductor manufacturing, embedded systems design, and specialized computing architectures. His recent focus on neural network acceleration and memory system optimization reflects the evolving landscape of computer architecture research.

Ava HedayatipourView profile

Assistant Professor

• Analog Integrated Circuit Design
• Bio-implantable and Biomedical Devices
• Low-Power and Low-Noise Designs
• +3 more

Dr. Ava Hedayatipour is an Assistant Professor of Electrical Engineering at California State University at Long Beach (CSULB), where she joined in Fall 2020. She holds a Ph.D. from the University of Tennessee, Knoxville (2020), and degrees from Iran University of Science and Technology (B.S., 2012) and Shahid Rajaee Teacher Training University (M.S., 2015). Her research focuses on analog/mixed-signal circuit design, bio-implantable devices, low-power systems, and hardware security. Notable contributions include a first-of-its-kind integrated secure multimodal sensor and a flexible paper electrode for remote electrochemical experiments. Education: Ph.D., Electrical Engineering, University of Tennessee, Knoxville, 2020 M.S., Electrical Engineering, Shahid Rajaee Teacher Training University, Iran, 2015 B.S., Electrical Engineering, Iran University of Science and Technology, 2012 Research Interests: Analog and mixed-signal circuit design Biomedical devices and lab-on-chip applications Low-power, low-noise microelectronics Hardware security for IoT and biomedical sensors Flexible electrodes for wearable systems Awards: University of Tennessee Fellowship Award (2019) Outstanding Teaching Assistant Award (2018) BEST PAPER AWARD at IEEE DCAS 2025 2nd Place Winner at IEEE BIOCAS 2023 Innovation Challenge Advising & Grants: Lead CSULB LEAP program project on medical imaging braces Funded NSF project on chaotic analog security (2018–present) Collaborated with industry partners like Applied Medical and Synaptics Labs & Teams: Next Generation Wearable Lab at CSULB Focus on sensor design, hardware security, and biomedical applications

Vincent John Mooney IIIView profile

Associate Professor

• Hardware-Software Co-Design
• Cyber Physical Systems Security
• System Level Design
• +7 more

Vincent John Mooney III is an Associate Professor at the School of Electrical and Computer Engineering and an Adjunct Associate Professor at the School of Computer Science, Georgia Institute of Technology. His research focuses on Hardware-Software Co-Design , Cyber Physical Systems Security , and Low-Power Architectures . He has authored numerous publications on topics such as probabilistic computing, hardware security, and embedded systems design. Dr. Mooney has received prestigious awards including the NSF Career Award , National Semiconductor Fellowship , and ARCS Best Paper Award . Education: Ph.D. in Electrical Engineering (1998), Stanford University MA in Philosophy (1997), Stanford University MS in Electrical Engineering (1994), Stanford University Certificate of Graduate Study (1992), University of Navarra BS in Electrical Engineering and Computer Science (1991), Yale University Research interests span hardware/software codesign, cybersecurity in embedded systems, and synthesis of reconfigurable architectures. His recent work includes Gridtrust for decentralized supply chain cybersecurity and COPPER for computation obfuscation. Dr. Mooney has supervised numerous Ph.D. students and held leadership roles in conferences such as HOST and CASES . Scientific awards include NSF Career Award (2000) National Semiconductor Fellowship (1997-1998) AT&T Engineering Scholarship Program (1987-1991) NCAA Postgraduate Scholar (1991) Senior Member, IEEE (2003) ARCS 2012 Best Paper Award Advising and grants highlight his mentorship of students like Jun Cheol Park and Yudong Tan , along with grants such as the U.S. Air Force Summer Faculty Fellowship (2007). He leads the Hardware/Software Codesign for Security Group at Georgia Tech and has contributed to advancements in real-time operating systems and deadlock detection algorithms.

Wenjing RaoView profile

Associate Professor

• VLSI Test
• Fault-Tolerance
• Reliability
• +3 more

Wenjing Rao is an Associate Professor at the Department of Electrical and Computer Engineering, College of Engineering, University of Illinois at Chicago (UIC). Her research focuses on VLSI test, fault-tolerance, reliability, and hardware security in emerging nanoelectronic systems. Education: Ph.D. in Computer Science from University of California, San Diego (2008) B.S. in Computer Science from Peking University (2001) Her work explores novel computation paradigms through physical unclonable functions (PUFs), defect-tolerant logic implementation, and scalable fault tolerance in many-processor arrays. Publications emphasize hardware security, reconfiguration strategies, and reliability challenges in nanoscale architectures. Notable honors include the 2017 Harold A. Simon Award for Excellence in Teaching and the 2012 NSF CAREER Award. She has contributed to key journals like IEEE Transactions on Computer-Aided Design and conferences including DATE, ASPDAC, and NANOARCH.

Lisa WillsView profile

Assistant Professor

• Computer Architecture
• Hardware Acceleration
• Hardware-Software Co-Design
• +5 more

Lisa Wills serves as Assistant Professor of Computer Science at Duke University's Trinity College of Arts & Sciences and holds a joint appointment in Electrical and Computer Engineering at the Pratt School of Engineering since 2019. Her research bridges computer architecture and domain-specific applications, with a focus on hardware acceleration for computationally intensive fields. Dr. Wills earned her Ph.D. from Columbia University in 2014. Her academic journey reflects a deep commitment to advancing hardware-software co-design methodologies for real-world computational challenges. Her research centers on developing efficient hardware accelerators for big data analytics, particularly in genomics, graph processing, and database systems. She pioneers frameworks that simplify accelerator deployment while tackling critical bottlenecks in genomic data analysis, protein structure prediction, and privacy-preserving computing. Current work focuses on hardware-aware machine learning systems and energy-efficient architectures for emerging AI applications. Analysis of her publication record reveals a clear trajectory: from foundational work in database processing units (2014-2016) to specialized genomic accelerators (2019-2021), then evolving toward ML-enhanced design automation (2022-2023) and cutting-edge architectural abstractions (2024-2025). Her research consistently targets the intersection of hardware efficiency and domain-specific computational demands, with increasing emphasis on AI/ML workloads. Google ML and Systems Junior Faculty Award (2025) Dr. Wills actively mentors doctoral students including Chris Kjellqvist (lead architect of Beethoven accelerator framework), Mason Ma (PyTFHE FHE framework), and Mansi Choudhary (COCOSSim accelerator simulator). Her research is supported by significant grants including the NSF AI Institute: Athena ($20M, 2021-2027), Meta-funded ProSE accelerator project (2023-2026), and NSF CAREER award (2021-2026), totaling over $25M in active funding. She directs the APEX Lab (Application-driven Programmable Efficient Accelerated Systems), which develops open-source frameworks like Beethoven for FPGA/ASIC accelerator deployment and focuses on lowering barriers for non-hardware researchers to leverage custom acceleration in genomics, AI, and big data applications.

Jeff ZhangView profile

Assistant Professor

• Deep learning
• Computer architecture
• Embedded systems
• +5 more

Jeff Zhang is an Assistant Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University. He joined ASU in January 2023 after completing a postdoctoral fellowship at Harvard University. His research spans deep learning, computer architecture, embedded systems, and EDA, with particular emphasis on energy-efficient and fault-tolerant design for AI/ML systems and hardware accelerators. Education: Ph.D., New York University M.Eng., B.Eng., Hunan University Dr. Zhang's research bridges theoretical machine learning with practical hardware implementation, developing novel architectures that optimize performance, power consumption, and reliability. He has pioneered approaches for hardware acceleration of large language models, efficient sparse matrix operations, and novel memory technologies for AI workloads. His work has received multiple awards including IEEE Top Picks in Test and Reliability (2023) and IEEE Micro Best Paper Award (2022). His recent publications demonstrate a strong trend toward heterogeneous computing, with significant work in chiplet-based AI accelerators, photonic computing for AI, and 2.5D/3D integration techniques. The research spans from high-level compiler frameworks to circuit-level innovations, with a consistent theme of co-designing algorithms and hardware for optimal AI performance. His work on the SODA toolchain has been particularly influential in bridging Python to silicon. Scientific Awards: IEEE Top Picks in Test and Reliability, IEEE ITC, 2023 Best Paper Award, IEEE Micro, 2022 Best Paper Award Candidate, IEEE DATE, 2022 Best Presentation Award Nomination, ACM SIGDA DATE PhD Forum, 2020 Best Paper Award Nomination, IEEE VLSI Test Symposium, 2018 Ernst Weber Ph.D. Fellowship, New York University, 2015, 2016 Dr. Zhang actively mentors a diverse group of graduate and undergraduate students, with several alumni now working at leading technology companies including Apple, TSMC, and Ansys. His research is supported by prestigious grants from NSF, Sandia National Labs, and industry partners. He serves on technical program committees of numerous top conferences and has organized special sessions on emerging topics like Gen AI for Chip Design and LLM-Aided Design. Dr. Zhang leads a vibrant research group that collaborates extensively with industry partners and national laboratories. Current projects focus on next-generation AI hardware, including chiplet-based systems, photonic accelerators, and novel memory technologies for large language models. His group has developed several open-source tools and frameworks, including the SODA toolchain for bridging Python to silicon.

• Reconfigurable Computing
• FPGA Accelerators
• Parallel and Distributed Computing
• +3 more

Viktor Prasanna is the Charles Lee Powell Chair in Engineering and Professor of Electrical and Computer Engineering and Computer Science at the University of Southern California. He holds courtesy appointments in Computer Science and leads the Center for Energy Informatics, focusing on interdisciplinary research linking energy technologies, computer science, and engineering. Education: BE in Electronics (Bangalore University), ME (Indian Institute of Science), PhD in Computer Science (Pennsylvania State University) His research spans reconfigurable computing, FPGA accelerators, parallel and distributed systems, and big data applications. He has pioneered high-performance architectures and algorithms using FPGAs, impacting domains like networking, security, HPC, and machine learning. Prasanna has published over 600 papers, received 22 best paper awards, and secured >$50M in grants. His work emphasizes energy-efficient computing, with recent grants totaling $12.9M (2016–2021). His h-index is 73, with 23,454 total citations. Scientific Awards: IEEE Fellow, ACM Fellow, AAAS Fellow, W. Wallace McDowell Award, multiple Distinguished Alumnus Awards He has advised over 70 doctoral students and led major centers including CiSoft (Big Data in oilfield tech) and CAST. His editorial roles include Editor-in-Chief of IEEE Transactions on Computers and Journal of Parallel and Distributed Computing.