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Serdar ÖzoğuzView profile

Professor

• Active RC Filters
• Nonlinear Electronic Circuits
• Analog IC Design
• +3 more

Professor Serdar Özoğuz is a full faculty member at the Department of Electronics and Communication Engineering , Istanbul Technical University . Holding a Ph.D. from ITU (2000) and a M.Sc. from ITU (1993) , he has taught courses like Active Network Synthesis , Basics of Electrical Circuits , and Scientific Research Ethics since 2014. His research focuses on Active RC filters Nonlinear electronic circuits Analog integrated circuit design Network synthesis . His recent publications emphasize machine learning applications in RF/microwave design , quantum computing for CAD tools , and emerging memory devices . The department's Devreler ve Sistemler Laboratuvarı Çok Geniş Ölçekli Tümdevre (VLSI) Tasarımı Laboratuvarı likely support his work. Despite no explicit awards listed, his 15+ recent articles in high-impact journals underscore his technical contributions.

• CAD tools
• Digital architectures
• Emerging technologies
• +9 more

Giovanna Turvani is an Associate Professor at the Department of Electronics and Telecommunications (DET) at Politecnico di Torino, with affiliations in both the College of Electronic, Telecommunications and Physics Engineering and the College of Computer, Film, and Mechatronics Engineering. Scientific Branch: IINF-01/A - Electronics ERC Sectors: PE7_4, PE7_11, PE6_1, PE6_14, PE7_3 SDG Goals: Quality Education, Gender Equality, Affordable Energy, Industry Innovation Her research focuses on advanced electronics and quantum technologies, including: Logic-in-memory computing Quantum computing architectures Microwave imaging for medical and agricultural applications CAD tools for emerging nanotechnologies Embedded systems for bee health monitoring IoT solutions for bio-waste valorization Publications show strong expertise in quantum computing, nanocomputing, and microwave imaging, with recent trends emphasizing quantum optimization frameworks, in-memory architectures, and IoT-based agricultural technologies. She supervises PhD students in areas like quantum machine learning algorithms, predictive on-board systems, and quantum hardware design. Collaborations span multiple disciplines, including medical device development and agricultural electronics. Patents include innovations in microwave imaging, racetrack memory logic functions, and in-memory computing devices.

Forrest BrewerView profile

Professor

• VLSI Design
• Computer Engineering
• Electronic Design Automation
• +7 more

Professor Forrest Brewer is a faculty member in the Department of Electrical and Computer Engineering at the University of California, Santa Barbara (UCSB), affiliated with the College of Engineering. His research spans VLSI design, computer-aided design tools, and low-power computing, with a focus on unconventional engineering solutions. Education: PhD in Computer Science, University of Illinois BS in Physics (with honors), California Institute of Technology His work includes CMOS pulse-gate asynchronous logic for high-performance systems, sigma-delta modulation for signal processing, and formal verification strategies for asynchronous circuits. Applications range from radiation-hardened communication links for the Large Hadron Collider (LHC) to spiking neural networks for low-power computing in LIDAR/RADAR systems. Affiliations: California Nanosystems Institute Allosphere Steering Committee (Media Technology) With over 100 publications and 40 years of systems design experience, Brewer has contributed to defense programs, founded UCSB's Computer Engineering program, and served as Intel Faculty Fellow (1997). His lab, the Systems Synthesis Lab, explores collective dynamics and high-resolution, low-latency computation.

Anuj PathaniaView profile

Assistant Professor

• Low Power Design
• Sustainable Systems
• Electronic Design Automation
• +4 more

Anuj Pathania serves as an Assistant Professor in the Parallel Computing Systems (PCS) group within the Informatics Institute at the University of Amsterdam's Faculty of Science. His research pioneers sustainable computing systems operating under severe power, thermal, and reliability constraints, with significant contributions to energy-efficient hardware design and embedded systems. Education: PhD in Computer Science (2018), Karlsruhe Institute of Technology MSc in Computer Science (2012), National University of Singapore B.Tech in Computer Science (2009), Maharaja Agrasen Institute of Technology Pathania's research centers on low-power design and sustainable systems for constrained environments, with particular expertise in thermal management of 3D-stacked architectures and energy-efficient machine learning inference . His work bridges electronic design automation with real-world reliability challenges, developing novel power budgeting techniques like T-TSP that incorporate transient temperature effects ignored by conventional methods. Current projects include EU-funded initiatives on energy labeling for digital services, addressing ecological impacts through technological, behavioral, and legal frameworks. His publication trajectory reveals a strategic evolution toward zero-waste computing , with recent work (2023-2025) focusing on hardware-software co-design for edge AI, energy modeling across computing continua, and parameter-efficient neural adaptation. Key themes include thermal-aware scheduling for S-NUCA many-cores, cooperative processor utilization in heterogeneous systems, and sustainability metrics for digital services. Scientific Recognition: Best Paper Award Nomination at IEEE Computer Society Annual Symposium on VLSI 2023 for 3D-TTP power budgeting technique Pathania actively mentors 4 PhD students (Ehsan Aghapour, Saeedeh Baneshi, Sudam Wasala, Yixian Shen) and has successfully supervised 5 Master's theses (including Cum Laude defenses by Joris op ten Berg and Jurre Wolff). His research is supported by major grants including Energy Labels for Ecologically Sustainable Digital Services (2023-2024) and Towards Zero-Waste Computing (2021-2025), developing simulation frameworks like HotSniper and CoMeT for thermal analysis. The PCS group maintains strong industry collaborations with ARM and NVIDIA, particularly through tools like ARM-CO-UP for heterogeneous processor utilization.

Graeme BraggView profile

Teaching Professor

• Parallel Computing
• Event-driven Systems
• Bioinformatics
• +5 more

Dr Graeme Bragg is a Senior Teaching Fellow at the University of Southampton within the Department of Electronics and Computer Science . His work spans teaching, research, and technical development with a focus on event-driven computing, bioinformatics, and computational modeling. He actively supervises PhD students and collaborates on interdisciplinary projects. Research Interests: Parallel computing, event-driven systems, genotype imputation, Petri net simulations, subglacial hydrology modeling Teaching: Specializes in hardware description languages and computational methods for engineering students Technical Expertise: RISC-V architecture, FPGA acceleration, bespoke compute fabric development His recent publications demonstrate expertise in applying event-driven computing to diverse problems including: 2025: Automated marking systems for SystemVerilog labs 2025: Seasonal dynamics in subglacial hydrology 2023: Genotype imputation using custom hardware 2022: Optimization algorithms and graph analysis Current research explores: Custom RISC-V FPGA clusters for bioinformatics Event-triggered systems for scientific simulations Parallel computing solutions for molecular modeling Contact: gmb@ecs.soton.ac.uk | +44 23 8059 2784

• Logic Synthesis
• Digital Circuit Design
• Machine Learning
• +3 more

Andrea Costamagna is a researcher affiliated with the École Polytechnique Fédérale de Lausanne (EPFL), working within the School of Computer and Communication Sciences and the Department of Communication Systems. His research focuses on logic synthesis, digital circuit design, and the intersection of machine learning with hardware implementation. His work includes optimizing digital circuits using techniques like resynthesis, resubstitution, and decomposition, with applications in FPGA design and low-power systems. Recent publications explore symmetry-based synthesis, glitch-aware power minimization, and the use of resistive switching devices in machine learning hardware. His research also extends to quantum physics modeling with deep learning.

Luca SterponeView profile

Professor

• Reconfigurable computing
• Computer-aided design algorithms
• Fault tolerance and reliability
• +7 more

Luca Sterpone is a Full Professor at the Department of Control and Computer Science (DAUIN), Politecnico di Torino. He serves as Head of the Control and Computer Engineering Department (2023-2027), coordinates the Aerospace and Safety Computing Lab, and is a member of the Academic Senate and Power Electronics Innovation Center (PEIC). His research spans reconfigurable computing, fault tolerance, and radiation effects analysis in electronic systems. Professor since 2021 Department Head (DAUIN) since 2023 Coordinates international collaborations with ESA, AMD Xilinx, NVIDIA, and Thales Alenia Space Develops radiation-hardened FPGA tools (SETA, VERI-Place, PyXEL) 2007 EDAA Outstanding Dissertation Award and 2005 IEEE Best Paper Award Research Focus : Designing radiation-tolerant systems for aerospace, including fault-tolerant AI accelerators, FPGA reliability, and software-based error mitigation. He investigates soft error propagation in nanoscale circuits and develops tools for radiation sensitivity analysis in VLSI. His work integrates hardware-software co-design for mission-critical applications. Awards : EDAA Outstanding Dissertation Award (2007) IEEE European Test Symposium Best Paper (2005) SMACD Best EDA Tool Award (2018) ARC Best Paper candidate (2018) Teaching : He leads courses in Reconfigurable Computing (PhD level), GPU Programming , and Operating Systems . He has formal responsibility for teaching roles across 9 bachelor's and 7 master's years, and mentors multiple PhD students. Collaborations : Coordinates with the European Space Agency (ESA), University of Bielefeld, Universidad de Sevilla, and industrial partners like AMD Xilinx, NVIDIA, and General Motors. He leads projects such as RESCHIP4EU, VEGAS, and TERRAC for radiation-hardened computing solutions.

Xuming HeView profile

Associate Professor

• Computer Vision
• Machine Learning
• Artificial Intelligence
• +9 more

Xuming He is an Associate Professor at the School of Information Science and Technology (SIST), ShanghaiTech University, where he leads the PLUS Lab. His research spans computer vision and machine learning with a focus on developing algorithms that operate effectively under limited supervision and evolving data conditions. His core research interests include weakly-supervised and few-shot learning for scenarios with sparse annotations, continual learning frameworks for knowledge retention during sequential task acquisition, semantic segmentation techniques for scene understanding, and multimodal vision-language representations. He emphasizes interpretable machine learning to build transparent AI systems capable of human-understandable reasoning, addressing critical challenges in model trustworthiness and deployment reliability. Recent publications reveal strong trends toward novel class discovery in long-tailed recognition scenarios, physics-informed generative modeling for scientific applications, and robust segmentation under distribution shifts. His work increasingly integrates large language models for multimodal reasoning while maintaining focus on efficiency in resource-constrained environments like robotic grasping and medical imaging analysis. He actively mentors students, having supervised Qian He to PhD completion and Chuanyang Hu to Master's degree in 2023. He welcomes prospective graduate students through ShanghaiTech's Computer Science & Technology program and offers undergraduate research projects requiring minimum six-month commitments. The PLUS Lab under his direction drives innovation in learning under supervision constraints, with recent work spanning medical tumor analysis, cross-view geolocation, photonic computing, and semiconductor design verification. The lab's research bridges theoretical advances with practical applications across healthcare, robotics, and scientific discovery domains.

Ahmed HemaniView profile

Professor

• Computer Engineering
• Embedded Systems
• Hardware Acceleration
• +5 more

Professor Ahmed Hemani is a faculty member at the Division of Electronics and Embedded Systems, KTH Royal Institute of Technology, affiliated with the Digital Futures Faculty. He holds the role of PI for the project 'New Chip Architectures for Industrial Vision' and leads research in reconfigurable computing, memristor-based systems, and hardware acceleration for AI and edge computing. His work bridges theoretical computer science with practical VLSI design and embedded systems development. He actively contributes to cross-disciplinary initiatives at Digital Futures, a joint center with Stockholm University and RISE Research Institutes of Sweden focused on digital innovation. His research emphasizes scalable FPGA/HPC architectures, low-power neuromorphic systems, and optimization techniques for custom silicon solutions. Current projects include a Lego-inspired edge AI framework and memristor-driven MIMO acceleration. Teaching responsibilities span advanced courses in SOC design, digital system verification, and embedded systems. He supervises advanced-level degree projects across computer engineering and ICT innovation specializations, emphasizing hands-on hardware-software co-design methodologies. Recent publications highlight innovations in memristor applications, FPGA-based acceleration, and reconfigurable architectures for neural networks and bioinformatics. His work addresses challenges in dark silicon utilization, energy-efficient computation, and high-performance embedded systems.

Shimeng YuView profile

Professor

• Semiconductor Devices
• Non-Volatile Memories
• 3D Integration
• +5 more

Shimeng Yu is a full professor at the Georgia Institute of Technology's School of Electrical and Computer Engineering, holding the Dean’s Professorship. He earned his B.S. from Peking University (2009) and M.S./Ph.D. from Stanford University (2011/2013). His research focuses on semiconductor devices, non-volatile memories, 3D integration, and AI hardware accelerators. Yu leads SRC/DARPA JUMP 2.0 centers on memory/storage and 3D integration, with over 400 publications and 30,000+ citations (H-index 82). He serves on flagship conference committees (e.g., IEDM, VLSI) and editorial boards (IEEE EDL, JETCAS). Education: B.S., Microelectronics, Peking University (2009) M.S./Ph.D., Electrical Engineering, Stanford University (2011/2013) Research Themes: Emerging non-volatile memories for AI Monolithic 3D integration Energy-efficient computing systems His work spans device fabrication, circuit design, and system-level co-optimization. Recent projects are funded by NSF, DARPA, DOE, and industry partners (TSMC, Intel, Samsung), totaling >$17M. His lab, located at the Pettit Microelectronics Research Center, develops prototypes with cleanroom access. Awards: IEEE Fellow (2024) ACM/IEEE DAC Under-40 Innovators Award (2020) NSF CAREER Award (2016) Multiple editorship roles and distinguished lecturer appointments (IEEE EDS/CASS) Grants & Funding: Lead of two SRC/DARPA JUMP 2.0 centers Total research funding exceeds $17M

Kenneth KentView profile

Professor

• Hardware/Software Co-Design
• Virtual Machines
• Reconfigurable Computing
• +5 more

Dr. Kenneth Kent is a Professor in the Department of Computer Science at the University of New Brunswick (UNB), where he has served for 14 years. He is the Director of the Information Technology Centre (ITC) and heads the Reconfigurable Computing Group. He also serves as Director of the IBM Centre for Advanced Studies - Atlantic and holds an Honorary Professorship at Hochschule Bonn-Rhein-Sieg. His research focuses on hardware/software co-design, reconfigurable computing, virtual machines, and embedded systems. Dr. Kent earned his PhD and Master of Science in Computer Science from the University of Victoria. His work has led to over 100 refereed publications and the supervision of 70+ graduate students. He co-founded WEnTech Solutions Inc., a software firm addressing waste-to-energy optimization. His awards include the IBM Faculty Fellow of the Year and Project of the Year (as Principal Investigator) for contributions to the J9 Java Virtual Machine. His articles span FPGA acceleration, compiler optimization, cloud storage security, and IoT intrusion detection. Recent work emphasizes energy-efficient Node.js systems and advancements in CAD tools like VTR 9 for FPGA architecture. Dr. Kent’s advising and grants include leading the IBM CAS Atlantic and directing industry-academia collaborations. He has pioneered technologies such as the Eclipse OpenJ9 JVM and the CephArmor storage interface, balancing academic research with commercial innovation. He leads the Reconfigurable Computing Group at UNB and collaborates with the Institute for Visual Computing in Germany. His research bridges theoretical computing and practical applications, with a focus on scalable systems and embedded technologies.

Shawki M. AreibiView profile

Professor

• VLSI Physical Design Automation
• Reconfigurable Computing Systems
• Hardware/Software Co-Design for Embedded Systems
• +7 more

Shawki M. Areibi is a Professor and Area Head of Engineering Systems and Computing in the School of Engineering at the University of Guelph. His research focuses on VLSI Physical Design Automation, Reconfigurable Computing Systems, and Hardware/Software Co-design for Embedded Systems. He leads efforts in developing advanced algorithms for CAD tools, FPGA design, and machine learning applications. His work addresses challenges in VLSI layout optimization, parallel processing, and embedded systems design. Affiliations: AI Affiliated Faculty, Area Heads, Computer Engineering, Engineering Systems and Computing Research. Research Interests: VLSI Circuit Layout, Reconfigurable Computing, Machine Learning, and FPGA-based Accelerators. His research integrates meta-heuristics like Genetic Algorithms and Tabu Search to solve complex optimization problems. He has contributed to hardware acceleration frameworks for machine learning algorithms and embedded systems, with applications in domains like signal processing and data mining. His recent work includes congestion-estimation models for modern FPGAs and analytic placement tools for ultra-scale architectures. Publications span VLSI design, reconfigurable computing, and machine learning, emphasizing algorithmic innovation and hardware-software co-design. His students have explored topics ranging from FPGA placement to domain adaptation in remote sensing. Grants and Advising: Advises graduate and undergraduate students on projects involving FPGA acceleration, machine learning, and embedded systems. His labs focus on developing next-generation CAD tools and hardware accelerators.

• Electronic Design Automation (EDA)
• VLSI Circuit Design
• Algorithmic Aspects of Chip Design
• +5 more

Martin D. F. Wong is the Edward C. Jordan Professor of Electrical and Computer Engineering and Executive Associate Dean of the College of Engineering at the University of Illinois. A pioneer in Electronic Design Automation (EDA) and VLSI circuit design, his work has significantly advanced chip design methodologies through algorithmic innovations. He holds over 450 publications and has been recognized with prestigious awards, including the ASP-DAC Most Frequent Author Award and the inaugural EDA Research Award from Synopsys. Wong’s research focuses on EDA, computational lithography, and 3D integrated circuits. He has mentored 48 PhD students, many of whom have excelled in academia and industry. His contributions include foundational frameworks like OpenILT (Inverse Lithography Technique) and Xplace (global placement). He is an IEEE Fellow and has served as a Distinguished Lecturer for the IEEE Circuits and Systems Society. Key Achievements: Recipient of six best-paper awards in chip design and routing optimization Developed GPU-accelerated tools for static timing analysis and global routing Advances in machine learning applications for EDA, including congestion prediction and hotspot detection Wong’s legacy combines technical innovation with mentorship, shaping the future of semiconductor design and manufacturing.

Azadeh DavoodiView profile

Professor

• Electronic Design Automation (EDA)
• Integrated Circuit Design
• Machine Learning in Hardware
• +5 more

Azadeh Davoodi is a Vilas Distinguished Achievement Professor and Associate Chair of Undergraduate Studies in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. Her research focuses on Electronic Design Automation (EDA), integrated circuit debug, and machine learning applications in VLSI design. She holds editorial roles in journals like IEEE TCAD and ACM TRETS, and has chaired major conferences such as ISPD 2015 and served on technical program committees for DAC, ICCAD, and others. Education: PhD in Electrical Engineering, University of Maryland-College Park (2006) Research Interests: Machine learning for VLSI chip design VLSI design automation for machine learning IC-CAD for emerging nanotechnologies Hardware security Recent Research Trends: Her work bridges machine learning and hardware design, with publications on neural network optimization, distributed inference, and explainable AI for circuit design. She emphasizes energy-efficient CNNs, latency reduction in edge computing, and security in split manufacturing. Awards: 2025 DATE Best Paper Candidate 2024 Vilas Distinguished Achievement Professor 2015 ACM Best Paper Award 2011 NSF CAREER Award Service and Grants: Leads NSF-funded projects on explainable ML for CAD and holds grants for distributed neural network synthesis. Her service includes roles as IEEE HKN member and editorial board positions. Labs/Teams: Engages in interdisciplinary research teams at UW-Madison, focusing on EDA innovation and hardware-software co-design.

• FPGA Design
• VLSI Systems
• Logic Synthesis
• +7 more

Pierre-Emmanuel Gaillardon is a Professor in the Department of Electrical & Computer Engineering and Adjunct Professor in the School of Computing at the University of Utah. He holds a joint appointment since July 2024, having previously served as Assistant Professor (2016–2019) and Adjunct Assistant Professor in Computing (2016–2019). His research focuses on FPGA design, VLSI systems, nanoelectronics, and hardware security. He leads projects in emerging devices like TIGFETs, compute-in-memory architectures, and radiation-hardened FPGA fabrics. Teaching includes courses on Digital VLSI Design, Embedded Systems Design, and thesis supervision. He has secured grants from NSF, DARPA, and industry partners totaling over $10M, addressing topics like FPGA redaction, neuromorphic systems, and environmental sensors. Notable awards include the NSF CAREER Award (2018) and IEEE Senior Member elevation (2016). He actively serves on IEEE committees for nanoelectronics and EDA tools, contributing to standards like OpenFPGA.