Find Academic Supervisors

Benjamin Carrison-SchaferView profile

Associate Professor

• Reconfigurable Computing
• FPGAs
• Electronic Design Automation
• +7 more

Benjamin Carrison-Schafer is an Associate Professor and Assistant Dean for Graduate Student Success at the Department of Electrical and Computer Engineering, Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas. He leads the Design Automation and Reconfigurable Computing Laboratory (DARClab), focusing on systems, high-level design, and programming methodologies for VLSI computing systems and FPGAs. Education: MBA from McGill University, Canada (2012) PhD in Electrical and Electronic Engineering from University of Birmingham, UK (2003) Research Interests: His work spans modeling, analysis, synthesis, optimization, and implementation of VLSI systems. Current projects include: Approximate Computing, High-Level Synthesis Design Space Exploration, Hardware Security, Behavioral MPSoC Optimization, and Automatic Fault-Tolerant System Generation. His research blends theory and practice, using analytical and experimental techniques to solve real-world problems. Publication Trends: Recent publications demonstrate strong focus on hardware security, FPGA optimization, and automated design methodologies. Key themes include High-Level Synthesis innovations, hardware acceleration techniques, and cross-disciplinary applications of reconfigurable computing. His work frequently addresses challenges in hardware trustworthiness, energy efficiency, and design automation scalability. Professional Activities: Associate Editor: IEEE Transactions on Sustainable Computing (2022-present) Conference Chair: ICCD 2024, DCAS 2024 Program Committee: ASP-DAC, DATE, FCCM, GLSVLSI Advising & Labs: Supervises multiple PhD and Master's students at DARClab. Current research includes domain-specific architecture design, hardware security, sustainable computing, and ML for VLSI design. The lab collaborates with industry partners like Renesas Electronics and develops commercial tools through spin-off company highX Technologies.

Giovanni De MicheliView profile

Professor

• Integrated Circuit Design
• Hardware Synthesis
• Logic Optimization
• +5 more

Giovanni De Micheli is a Full Professor at École Polytechnique Fédérale de Lausanne (EPFL), holding appointments in both the School of Computer and Communication Sciences (IC) and the School of Engineering (STI). He is affiliated with the Integrated Systems Laboratory (LSI) and serves as Scientific Director of EcoCloud. His primary office is located in INF 341 building at EPFL's Lausanne campus where he conducts research and teaching activities. Professor De Micheli's research spans multiple domains in electronic design automation and integrated circuit design. His primary interests include: Integrated Circuit Design and Hardware Synthesis Logic Optimization and Boolean Methods Nanoelectronics and 2D Electronics Quantum Computing and Emerging Technologies Low-Power Electronics and Energy-Efficient Systems Electronic Design Automation for Novel Computing Paradigms His recent publications demonstrate a strong focus on advancing logic synthesis techniques for both conventional and emerging technologies. Professor De Micheli's work bridges theoretical foundations with practical applications, particularly in adapting traditional EDA methods to novel computing paradigms like quantum computing and superconducting electronics. His research group has made significant contributions to the development of efficient algorithms for circuit optimization across multiple technology domains, with particular emphasis on area, power, and delay optimization while maintaining functional correctness. Professor De Micheli has supervised numerous doctoral students throughout his career at EPFL, mentoring over 40 PhD candidates whose research spans various aspects of electronic design automation, circuit design, and emerging technologies. His students have gone on to make significant contributions in both academia and industry. As Scientific Director of EcoCloud, Professor De Micheli leads research initiatives focused on energy-efficient computing systems and sustainable cloud infrastructure. His laboratory, the Integrated Systems Laboratory, serves as a hub for interdisciplinary research connecting computer science, electrical engineering, and materials science, with particular focus on next-generation computing technologies.

Sung-Kyu LimView profile

Professor

• Physical design automation for VLSI circuits
• 3D circuit/packaging layout automation
• Quantum circuit layout automation
• +3 more

Sung-Kyu Lim is a Professor and the Motorola Solutions Foundation Professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology, where he serves as director of the GTCAD Laboratory. His educational background includes: B.S. in Computer Science from the University of California, Los Angeles (UCLA) in 1994 M.S. in Computer Science from UCLA in 1997 Ph.D. in Computer Science from UCLA in 2000 Professor Lim's research focuses on advancing VLSI design automation through physical design methodologies, 3D circuit integration, quantum circuit layout, micro-architecture exploration, and reconfigurable circuit optimization. His work bridges theoretical graph theory with practical electronic design automation challenges to improve circuit performance and scalability. His notable scientific distinctions include: NSF CAREER Award (2006) Advisory Board Member of ACM SIGDA (since 2003) Technical Program Committee roles for ICCD, ISPD, ISCAS, ASPDAC, and GLSVLSI conferences He leads the GTCAD Laboratory at Georgia Tech, driving innovation in computer-aided design tools for next-generation integrated circuits and systems.

Andre DeHonView profile

Professor

• Reconfigurable Computing
• FPGA Architecture
• Interconnect Design
• +6 more

André DeHon is the Oliver C. Boileau Jr. and Nan Eleze Boileau Professor of Electrical Engineering at the University of Pennsylvania, with affiliations in the Electrical and Systems Engineering (ESE) and Computer and Information Science (CIS) departments. He founded the Penn Computer Engineering (CMPE) program and directs the DARPA-sponsored CyberSavvy Security Center. His research spans reconfigurable computing, FPGA architecture, interconnect design, hardware security, and energy efficiency, with a focus on adapting to fabrication imperfections and runtime variability. His work explores programmable substrates (e.g., CMOS VLSI, molecular electronics) and algorithmic mappings to create resilient, efficient systems. Current projects include runtime feedback mechanisms (REFINE), partial reconfiguration (ExHiPR), and security frameworks like SCALPEL and μSCOPE. Recent publications highlight advancements in FPGA compilation (PLD, HiPR), security (SCALPEL, μSCOPE), and interconnect optimization (Asymmetry in NoC). These studies intersect computer architecture, security, and embedded systems. Scientific awards and recognitions: 2023 IEEE Fellow 2020 IEEE Mary Kenneth Keller Teaching Award 2018 ACM Fellow TCFPGA Hall of Fame (2019) Best Paper at ICFPT 2015 Academic leadership: He chairs the ACM/SIGDA Technical Committee on FPGAs and Reconfigurable Computing, previously held faculty roles at Caltech (1999–2006), and was a postdoc at UC Berkeley (1996–1999). Education includes MIT SB (1990), SM (1993), and PhD (1996) in Electrical Engineering and Computer Science.

Morteza FayaziView profile

Assistant Professor

• Electronic Design Automation (EDA)
• Machine Learning (ML) in Analog Circuit Design
• System-on-Chip (SoC) Design Automation
• +3 more

Morteza Fayazi is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Utah, with an adjunct position in the Kahlert School of Computing. His research focuses on Electronic Design Automation (EDA), applying machine learning to automate analog and mixed-signal circuit design, and developing high-performance computing systems. He holds a B.Sc. from Sharif University of Technology, and M.S.E./Ph.D. degrees from the University of Michigan. His research interests include AI-driven EDA, RF/circuit automation, and energy-efficient processors. Key achievements include the MEDAL lab’s work on terahertz radars, systolic-array processors (e.g., DAP and Versa), and open-source frameworks like FASCINET and Tablext. He has received awards such as the 2024 College of Engineering Dean’s ETR Fund and the 2017 Outstanding Undergraduate Thesis Award. Teaching responsibilities include multiple iterations of the Digital System Design course (ECE/CS 3700). His work spans over 15 peer-reviewed articles in IEEE Transactions, ACM, and top conferences like ICCAD and VLSI-SOC, emphasizing automation, efficiency, and AI integration in hardware design.

Supratik ChakrabortyView profile

Professor

• Formal Methods
• Formal Verification
• Automated Synthesis
• +7 more

Supratik Chakraborty serves as the Bajaj Group Chair Professor in the Department of Computer Science and Engineering at Indian Institute of Technology Bombay. He maintains dual affiliations with the Centre for Formal Design and Verification of Software and the Centre for Liberal Education at IIT Bombay, demonstrating his cross-disciplinary engagement. Professor Chakraborty's research spans formal methods with focus on formal verification, rigorous analysis of system models, and automated synthesis of systems from specifications. His work bridges theoretical foundations with practical applications, particularly in developing mathematically provable guarantees for increasingly complex hardware, software, and intelligent systems. Current research interests include constrained counting and sampling, scalable formal verification of software and hardware systems, automated synthesis of programs and circuits, and applications of automata, logic and finite model theory to practical verification challenges. His publication trajectory shows a significant evolution from traditional hardware and software verification toward addressing verification challenges in machine learning and AI systems. Recent work increasingly focuses on interpretability of black-box models, verification of neural networks, and synthesis techniques applicable to intelligent systems. The research demonstrates strong interdisciplinary connections between formal methods, programming languages, and artificial intelligence. IIT Bombay Excellence in Thesis (CSE) Award 2011 (for Bhargav Gulavani's thesis) IIT Bombay Excellence in Thesis (CSE) Award 2017 (for Abhisekh Sankaran's thesis) Best Paper in Algorithms and Architecture track at IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1998 Professor Chakraborty has successfully supervised 11 doctoral students, with research spanning formal verification techniques, Boolean functional synthesis, constrained counting, and applications to hardware and software systems. His students have gone on to positions at major institutions including Microsoft Research, TCS Research, Georgia Tech, and BARC, reflecting the strong industry and academic impact of his mentorship. Current research directions show increasing emphasis on verification challenges posed by machine learning systems and AI. His research group at IIT Bombay, while not explicitly named in the materials, appears to focus on formal methods with strong connections to the Centre for Formal Design and Verification of Software. The group maintains active collaborations with international researchers including Moshe Y. Vardi at Rice University, and has made significant contributions to verification tools like VeriAbs that bridge theoretical advances with practical applications.

Soheil SalehiView profile

Assistant Professor

• Hardware Security
• AI-Enabled Security
• Internet of Things (IoT) Security
• +15 more

Soheil Salehi is a tenure-track Assistant Professor in the Department of Electrical and Computer Engineering at the University of Arizona, with a joint appointment in Systems and Industrial Engineering. He is the Director of the Privacy-preserving, Intelligent, and Secure Computing (PRISM) Lab, established in August 2022. Prior to this, he was an NSF-Sponsored Computing Innovation Fellow and Postdoctoral Research Fellow at the University of California, Davis. Ph.D., Electrical and Computer Engineering, University of Central Florida, 2020 M.S., Electrical and Computer Engineering, University of Central Florida, 2016 B.S., Isfahan University of Technology, Iran, 2014 Dr. Salehi's research focuses on the intersection of hardware, AI, and security. His work spans hardware and AI-enabled security in IoT , Generative AI for hardware design and security , neuromorphic and biologically-inspired AI hardware , emerging spin-based devices , reconfigurable architectures , low-power VLSI circuits , and digital twins and mixed reality for semiconductor workforce development . He also explores the application of Generative AI in personalized education . His recent publications, spanning 2023–2025, reveal a strong trend toward integrating AI and machine learning into hardware security and design. Key themes include automated secure IC design flows , AI-driven hardware obfuscation , firmware and side-channel attack analysis , security in neuromorphic and spiking neural networks , and educational frameworks using digital twins and generative models . His work appears in top venues like DAC, ICCAD, USENIX Security, IEEE TCAS-I, and ISCAS. Outstanding Reviewer Award, IEEE/ACM Design Automation Conference (DAC), 2023 Best Presentation of the Symposium Award, UC Davis Postdoctoral Research Symposium, 2021 UCF Excellence by a Graduate Teaching Assistant (University-Level), 2016 Nominated for 30-under-30 Award, UCF, 2020 Nominated for Postdoctoral Research Excellence Award, UC Davis, 2022 Dr. Salehi has secured significant research funding as PI and Co-PI, including a $300K NSF SaTC EAGER grant on Generative AI-based Personalized Cybersecurity Tutor, a $174,000 University of Arizona PIF Award, and multiple RII grants totaling over $198K. He has also received industry funding from CHEST. He actively mentors students and leads the PRISM Lab, which focuses on privacy-preserving and intelligent secure computing. His service includes roles as Technical Program Committee (TPC) Member and Session Chair at premier conferences such as DAC, ICCAD, CCS, NDSS, and GLSVLSI. The PRISM Lab, under his direction, conducts cutting-edge research in secure and intelligent hardware systems, with applications in IoT, edge computing, and workforce development. The lab emphasizes interdisciplinary collaboration and innovation in both research and education.

Conor RyanView profile

Professor

• Genetic Programming
• Genetic Algorithms
• Grammatical Evolution
• +7 more

Conor Ryan is a Professor in the Department of Computer Science & Information Systems at the University of Limerick. He is a Science Foundation Ireland-funded Investigator since 2002 and a member of multiple research centres including Lero – the Irish Software Research Centre and the Limerick Digital Cancer Research Centre. His research focuses on Genetic Programming, Grammatical Evolution, and their applications in domains like healthcare analytics, digital circuit design, and financial modeling. He has authored over 250 publications, with recent work emphasizing automated feature selection in medical diagnostics, neural architecture search, and blockchain ecosystems. Teaching includes courses on Foundations of Computer Science and Computer Games Programming. Research interests span evolutionary computation, machine learning, and interdisciplinary applications. Collaborations involve global institutions, reflecting his work's impact across computer science, engineering, and healthcare. His research has addressed challenges in breast cancer diagnosis via genetic algorithms, cryptocurrency volatility prediction using random forests, and automated generation of digital circuits. Ongoing projects explore interpretability in AI, energy-efficient computing, and sustainable transport systems through predictive analytics. Professional memberships include roles in the Centre for Research Training in Foundations of Data Science and the Data-Driven Computer Engineering Research Centre, underscoring his commitment to interdisciplinary innovation.

Debjit PalView profile

Research Fellow

• Machine Learning for Electronic Design Automation (EDA)
• System-on-Chip (SoC) Verification
• Hardware Verification
• +6 more

Debjit Pal is a Post-Doctoral Associate at the School of Electrical and Computer Engineering, Cornell University, and a member of the Computer Systems Laboratory. His research focuses on machine learning techniques for hardware verification, SoC validation, and FPGA optimization. Education: Ph.D. in Computer Engineering (University of Illinois at Urbana-Champaign, 2019) M.S. in Computer Science (IIT Kharagpur, 2012) B.E. in Electronics Engineering (Jadavpur University, 2008) Research Interests: Machine Learning for Electronic Design Automation (EDA) System-on-Chip (SoC) Verification Edge Intelligence as a Service Compiler Optimizations for Reconfigurable and High-Performance Computing Scientific Awards: IEEE CEDA Student Research Award (2016) Best Paper Nomination (ICCAD 2015, DAC 2018, ASP-DAC 2019) E. J. McCluskey Best Doctoral Thesis Competition Semi-Finalist (2020) Travel Grants for ICCAD/DAC/ASPDAC (2018-2019) Professional Roles: Technical Program Committee Member (DAC, VLSID), Reviewer (IEEE TVLSI, DATE, ICCAD). Collaborates with researchers like Zhiru Zhang and Shobha Vasudevan.

• Network Security
• Android Security
• Malware Analysis
• +6 more

Vijay Laxmi is a Professor in the Department of Computer Science and Engineering at Malaviya National Institute of Technology (MNIT) Jaipur, India. With over a decade of active research publication from 2014-2024, Dr. Laxmi has established themselves as a prominent researcher in network security, Android security systems, and Network-on-Chip architectures. Their work demonstrates consistent collaboration with Manoj Singh Gaur and numerous doctoral students at MNIT Jaipur. Dr. Laxmi's research interests span Network Security, Android Security, Malware Analysis, Network-on-Chip Architectures, Routing Protocols, Side-Channel Attacks, Wireless Networks, and Mobile Security. Their work bridges theoretical security frameworks with practical implementations, particularly in mobile and embedded systems. Recent publications indicate a growing focus on AI-based security approaches including GAN applications for fuzzing and deep learning for image dehazing. The research trajectory shows increasing sophistication in security analysis techniques, evolving from basic malware detection to advanced side-channel attack analysis and sophisticated network security protocols. Recent publications demonstrate expertise in both theoretical frameworks and practical implementations with applications in real-world security challenges. Dr. Laxmi has mentored numerous graduate students including Vineeta Jain, Anugrah Jain, Sonal Yadav, Mohit Singh, and Gaurav Singal, who appear as co-authors across multiple publications. Their collaborative network extends to researchers at international institutions, indicating strong academic connections beyond their home institution.

Callie HaoView profile

Assistant Professor

• Software/Hardware Co-design
• Reconfigurable Computing
• Graph Computing
• +5 more

Callie Hao is an Assistant Professor in the Department of Electrical and Computer Engineering at the Georgia Institute of Technology since 2021, holding the ON Semiconductor Junior Professorship. Her research bridges hardware efficiency and algorithmic innovation with significant industry and federal recognition. Education: Ph.D. in Electrical Engineering, Waseda University (2017) M.S. and B.S. in Computer Science and Engineering, Shanghai Jiao Tong University Research Focus: Dr. Hao pioneers software/hardware co-design for edge AI, specializing in hardware-efficient machine learning algorithms, FPGA-based reconfigurable computing, graph neural networks, and electronic design automation (EDA). Her work emphasizes neural architecture search, high-level synthesis optimization, and memory-efficient systems for embedded and IoT applications, driven by the philosophy that "1 + 1 > 2" for transformative efficiency gains. Publication Impact: Her 15 most recent publications (2023-2026) reveal a strategic shift toward machine learning-driven EDA tools, with 60% focused on high-level synthesis frameworks and 40% on graph neural network acceleration. Key trends include simulation speed breakthroughs (LightningSim), automated accelerator generation (GNNBuilder), and cryptographic hardware innovations (Cryptonite), predominantly published in top-tier venues like MICRO, ICCAD, and DAC. Awards & Recognition: NSF CAREER Award (2024) and Intel Rising Star Faculty Award (2023) Best Paper Awards at MLCAD 2024 and GLSVLSI 2021 ON Semiconductor Junior Professorship (2025) and Sutterfield Family Early Career Professorship (2022) DAC-SDC competition championships (2018-2020) Mentorship & Funding: Dr. Hao advises 8+ Ph.D. students in the Sharc Lab, with Rishov Sarkar winning the Oscar P. Cleaver Award and Qualcomm Innovation Fellowship. Her research is funded by DARPA (2021) for ultra-light video intelligence systems and supported by industry awards from Amazon and Sony. She actively serves on program committees for DAC, ICCAD, and DATE conferences. Lab Leadership: As director of the Sharc Lab (Software/Hardware Co-design lab), she cultivates interdisciplinary research at the intersection of FPGA design, machine learning, and EDA, requiring expertise in Verilog/HLS, GNNs, and compiler technologies while maintaining strict focus on real-world hardware implementation.

• integrated system design
• quantum computation
• information security
• +4 more

Nozomu Togawa is a Professor at Waseda University's Faculty of Science and Engineering, School of Fundamental Science and Engineering, specializing in Computer Science. He has held this position since 2009 and also serves as Chief Scientific Officer (CSO) of Quanmatic Inc. since 2022. With a PhD in Engineering from Waseda University (1997), his academic journey includes positions at Waseda University and the University of Kitakyushu before his current professorship. His research interests focus on integrated system design , quantum computation , and information security . Togawa has published extensively with over 368 papers and significant citation metrics (Scopus h-index: 23, Google Scholar h-index: 28). His work bridges theoretical quantum computing with practical security applications, particularly in hardware security and IoT systems. Togawa's research demonstrates a clear progression from traditional hardware security toward quantum-inspired computing solutions. His recent publications focus on Ising machines, quantum annealing, and hardware Trojan detection, showing how quantum approaches can solve complex optimization problems in security contexts. He has made significant contributions to applying quantum computing techniques to practical problems like course selection optimization, travel planning, and hardware security verification. Among his notable recognitions are the Minister of Education, Culture, Sports, Science and Technology Award for Science and Technology (2018), SCOPE Results Development Promotion Award (2022), and multiple Best Paper Awards. He serves on important committees including the Ministry of Internal Affairs and Communications Cyber Security Task Force and the Institute of Electronics, Information and Communication Engineers' VLSI Design Technology Research Committee. Togawa actively mentors students who frequently appear as co-authors on his publications. His research group produces high-impact work in quantum computing applications and hardware security, with strong industry connections through his CSO role at Quanmatic Inc. He has received substantial research funding supporting his innovative work at the intersection of quantum computing and security.

Jiang HuView profile

Professor

• VLSI Design Automation
• Hardware Security
• Machine Learning Applications
• +3 more

Jiang Hu is a Professor in the Department of Electrical and Computer Engineering at Texas A&M University, holding the Eric D. Rubin '06 Endowed Professorship. He also serves as Co-Director of Graduate Programs and is affiliated with the Computer Science & Engineering department. His research focuses on VLSI design automation, machine learning applications, and hardware security. He has held roles as editor for IEEE Transactions on CAD and ACM Transactions on Design Automation, and chaired the 2012 ACM International Symposium on Physical Design. Education: B.S. in Optical Engineering (Zhejiang University, 1990), M.S. in Physics (1997), and Ph.D. in Electrical Engineering (University of Minnesota, 2001). He worked at IBM Microelectronics before joining Texas A&M in 2002. Research interests include energy-efficient VLSI circuits, on-chip communication fabrics, analog layout automation, and AI-driven EDA. Recent work emphasizes machine learning for design closure, privacy-preserving frameworks, and systolic array-based architectures. Awards: IEEE Fellow (2016) Humboldt Research Fellowship (2012) Multiple best paper awards at DAC, ICCAD, and ASPDAC Advising and grants: Leads initiatives like the SLICE project, NSF workshops on ML-EDA infrastructure, and serves as Editor-in-Chief of ACM TODAES since 2024. His work bridges academic research and industry applications in EDA and semiconductor design. Labs/Teams: Active contributor to open-source tools like ALIGN for analog layout generation and collaborations on machine learning for EDA commons.

Jason CongView profile

Professor

• Electronic Design Automation
• VLSI CAD
• FPGA Synthesis
• +6 more

Jason Cong is the Volgenau Chair for Engineering Excellence and Distinguished Chancellor's Professor in the Computer Science Department at UCLA's Samueli School of Engineering. He directs the Center for Domain-Specific Computing (CDSC) and the VLSI Architecture, Synthesis, and Technology (VAST) Laboratory, and serves as Associate Vice Provost for Internationalization and Co-Director of UCLA/PKU Student and Scholar Program. Dr. Cong's research spans electronic design automation, customizable computing for machine learning and big-data applications, quantum computing, and highly scalable algorithms. His work has produced over 500 publications with more than 41,000 citations and an H-index of 106. His recent work focuses on quantum computing compilation, domain-specific acceleration for AI workloads, and high-level synthesis optimization techniques that leverage machine learning. His publication trend shows a strong emphasis on quantum computing and machine learning acceleration in recent years, with numerous papers on quantum layout synthesis, LLM acceleration, and high-performance FPGA implementations. His team has developed frameworks like TAPA for task-parallel dataflow programming and RapidStream for automated parallel implementation of FPGA designs. Member of National Academy of Engineering (2017) IEEE Robert N. Noyce Medal recipient (2022) Phil Kaufman Award recipient (2024) ACM Chuck Thacker Breakthrough Award recipient (2024) 18 Best Paper Awards across major conferences Multiple 10-Year Retrospective Most Influential Paper Awards Dr. Cong has graduated 50 PhD students, many of whom are now faculty at major research universities or hold key positions at leading tech companies. He has led over 100 research projects funded by DARPA, NSF, SRC, and industry sponsors. His entrepreneurial activities include founding three successful companies (Aplus Design Technologies, AutoESL, and Falcon Computing Solutions), all acquired by major EDA players. His VAST Laboratory continues to push boundaries in domain-specific computing, with active research in quantum computing, AI acceleration, and high-performance FPGA implementations.

• Combinatorial optimization
• Design and analysis of algorithms
• Field-programmable systems
• +7 more

Martin D F Wong serves as the Edward C. Jordan Professor of Electrical and Computer Engineering and Executive Associate Dean for the College of Engineering at the University of Illinois at Urbana-Champaign. He is affiliated with the Coordinated Science Laboratory and has been instrumental in advancing electronic design automation research. His educational background includes: B.Sc. in Mathematics, University of Toronto (1979) MS in Mathematics, University of Illinois at Urbana-Champaign (1981) Ph.D. in Computer Science, University of Illinois at Urbana-Champaign (1987) Wong's research centers on combinatorial optimization and algorithm design for VLSI systems, with particular expertise in lithography-aware physical design, field-programmable systems, and electronic packaging. His work bridges theoretical algorithms with practical semiconductor manufacturing challenges as feature sizes shrink below 20 nanometers. Current research focuses on integrating chip design with next-generation lithography technologies including triple-patterning, self-aligned double patterning, directed self-assembly, and extreme ultraviolet processes. His publication record shows consistent contributions to electronic design automation, with emphasis on manufacturing-aware physical design algorithms and circuit optimization techniques. Recent work addresses the critical interface between circuit layout and lithography processes as semiconductor technology advances to 14nm and beyond. Scientific recognition includes: Fellow of IEEE and ACM 2000 IEEE Donald O. Peterson Best Paper Award Multiple Best Paper Awards at DAC, ICCD, and ICCAD conferences IBM Faculty Awards (2000, 2004) NSF Research Initiation Award Wong has secured significant research funding including a $450,000 NSF grant for lithography-aware physical design and has supervised over 49 PhD students. His work continues the legacy of integrated circuit innovation at Illinois, building on foundational contributions like Jack Kilby's integrated circuit invention. Current research initiatives focus on optimizing chip design for next-generation manufacturing processes where optical interference challenges require co-design of layout and fabrication. He leads research within the Coordinated Science Laboratory, focusing on electronic design automation algorithms that address the growing complexity of semiconductor manufacturing at nanometer scales.