Find Academic Supervisors

Shreyas Sen is the Elmore Associate Professor of Electrical and Computer Engineering at Purdue University, jointly affiliated with the School of Biomedical Engineering. He directs the Center for Internet of Bodies (C-IoB) and leads the SPARC Lab, focusing on circuits/systems for secure, energy-efficient body-centric communication and biomedical applications. Education: B.E. (Jadavpur University, 2006), M.S. & Ph.D. (Georgia Tech, 2009-2011). His research spans Human Body Communication (HBC), hardware security, IoT/IoB systems, and low-power sensing. Notable innovations include Electro-Quasistatic HBC (EQS-HBC) technology, which enables covert body-wire communication with 100x lower energy than conventional methods. Research Themes: Secure communication for medical wearables Physical layer security in IoT Ultra-low-power biosensors Side-channel attack mitigation in cryptographic ICs Publications: Over 200 papers in top venues (ISSCC, DAC, CICC, HOST) with focus on HBC systems, electromagnetic security, and biomedical circuits. Recent work explores EQS-HBC privacy properties (Nature Scientific Reports, 2019) and 350x current-domain signature attenuation for AES security (ISSCC 2020). Awards: NSF CAREER Award (2020) AFOSR Young Investigator (2016) MIT TR35 India (2018) 9 Best Paper Awards Intel Outstanding Researcher (2020) He advises over 20 students and leads industry collaborations through Ixana Inc. (founded 2020), commercializing EQS-HBC technology. Current efforts include EQS-based authentication systems and radiation dosimetry wearables.

• VLSI and Circuit Design
• Human Body Communication (HBC)
• Hardware Security
• +5 more

Priyanka Raina is an Assistant Professor of Electrical Engineering at Stanford University, with a courtesy appointment in Computer Science. She leads the Stanford Accelerate research group, focusing on domain-specific hardware architectures and agile hardware-software co-design. Her work emphasizes high-performance, energy-efficient accelerators for emerging technologies. Education: B.Tech. from IIT Delhi (2011), M.S. and Ph.D. from MIT (2013/2018). Postdoctoral experience includes NVIDIA Research (2018) and Amazon Visiting Academic (2023–present). Awards include the Sloan Research Fellowship (2024), NSF CAREER Award (2023), and Terman Faculty Fellowship (2018). Research Interests: Domain-specific architectures, near-memory computing, design productivity, and machine learning acceleration. Her group develops frameworks like AHA (Agile Hardware) for efficient accelerator design and compilers. Awards: Over 10 major awards, including best paper recognitions at VLSI, MICRO, and JSSC. Active roles as Associate Editor for IEEE JSSC and Program Chair for IEEE Hot Chips (2020). Advising & Teaching: Supervises multiple PhD and MS students in hardware design, CGRAs, and ML accelerators. Teaches VLSI design courses (EE271/272/372) and oversees independent studies in embedded systems and chip design. Labs & Collaborations: Affiliated with Stanford PORTAL Center, AHA Center, and SystemX Alliance. Projects include MINOTAUR (edge AI accelerator), Amber (CGRA-based SoC), and EMBER (RRAM macros).

• Domain-Specific Architectures
• Hardware/Software Co-design
• Energy-Efficient Computing
• +3 more

Giovanni De Micheli is a Full Professor at École Polytechnique Fédérale de Lausanne (EPFL), holding appointments in both the School of Computer and Communication Sciences (IC) and the School of Engineering (STI). He is affiliated with the Integrated Systems Laboratory (LSI) and serves as Scientific Director of EcoCloud. His primary office is located in INF 341 building at EPFL's Lausanne campus where he conducts research and teaching activities. Professor De Micheli's research spans multiple domains in electronic design automation and integrated circuit design. His primary interests include: Integrated Circuit Design and Hardware Synthesis Logic Optimization and Boolean Methods Nanoelectronics and 2D Electronics Quantum Computing and Emerging Technologies Low-Power Electronics and Energy-Efficient Systems Electronic Design Automation for Novel Computing Paradigms His recent publications demonstrate a strong focus on advancing logic synthesis techniques for both conventional and emerging technologies. Professor De Micheli's work bridges theoretical foundations with practical applications, particularly in adapting traditional EDA methods to novel computing paradigms like quantum computing and superconducting electronics. His research group has made significant contributions to the development of efficient algorithms for circuit optimization across multiple technology domains, with particular emphasis on area, power, and delay optimization while maintaining functional correctness. Professor De Micheli has supervised numerous doctoral students throughout his career at EPFL, mentoring over 40 PhD candidates whose research spans various aspects of electronic design automation, circuit design, and emerging technologies. His students have gone on to make significant contributions in both academia and industry. As Scientific Director of EcoCloud, Professor De Micheli leads research initiatives focused on energy-efficient computing systems and sustainable cloud infrastructure. His laboratory, the Integrated Systems Laboratory, serves as a hub for interdisciplinary research connecting computer science, electrical engineering, and materials science, with particular focus on next-generation computing technologies.

• Integrated Circuit Design
• Hardware Synthesis
• Logic Optimization
• +5 more

Sung-Kyu Lim is a Professor and the Motorola Solutions Foundation Professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology, where he serves as director of the GTCAD Laboratory. His educational background includes: B.S. in Computer Science from the University of California, Los Angeles (UCLA) in 1994 M.S. in Computer Science from UCLA in 1997 Ph.D. in Computer Science from UCLA in 2000 Professor Lim's research focuses on advancing VLSI design automation through physical design methodologies, 3D circuit integration, quantum circuit layout, micro-architecture exploration, and reconfigurable circuit optimization. His work bridges theoretical graph theory with practical electronic design automation challenges to improve circuit performance and scalability. His notable scientific distinctions include: NSF CAREER Award (2006) Advisory Board Member of ACM SIGDA (since 2003) Technical Program Committee roles for ICCD, ISPD, ISCAS, ASPDAC, and GLSVLSI conferences He leads the GTCAD Laboratory at Georgia Tech, driving innovation in computer-aided design tools for next-generation integrated circuits and systems.

• Physical design automation for VLSI circuits
• 3D circuit/packaging layout automation
• Quantum circuit layout automation
• +3 more

Sumeet Kumar Gupta is an Associate Professor in the Department of Electrical and Computer Engineering at Purdue University. His academic career spans from his current role to a prior Assistant Professorship at Pennsylvania State University (2014-2017) and an engineering position at Qualcomm Inc. (2012-2014). He holds a PhD in Electrical and Computer Engineering from Purdue University (2012), an M.S. from the same institution (2008), and a B.Tech in Electrical Engineering from IIT Delhi (2006). B.Tech, Electrical Engineering, IIT Delhi (2006) M.S., Electrical and Computer Engineering, Purdue University (2008) PhD, Electrical and Computer Engineering, Purdue University (2012) Dr. Gupta's research focuses on neuromorphic computing, low power variation-aware VLSI design in emerging nanotechnologies, device-circuit co-design, and nano-scale device modeling/simulations. His work addresses challenges in ferroelectric materials, crossbar arrays for deep neural networks, and energy-efficient AI hardware. Recent publications (2025-2024) highlight trends in: Ferroelectric HfO2/HZO thin films Compute-in-memory architectures Variability/stochasticity analysis Machine learning for device optimization Interconnect resistance/temperature effects AI hardware fault tolerance Scientific Awards & Recognitions: DARPA Young Faculty Award (2016) Early Career Professorship, Penn State (2014) 6th TSMC Outstanding Student Research Bronze Award (2012) Magoon Award (Purdue) Outstanding Teaching Assistant Award (Purdue, 2007) Intel PhD Fellowship (2009) His professional journey includes academic appointments at Purdue University (2020-present, Associate Professor) and Pennsylvania State University (2014-2017, Assistant Professor) after industry experience at Qualcomm Inc. (2012-2014). He maintains IEEE and EDS membership while publishing over 100 refereed works.

• Neuromorphic Computing
• Low Power VLSI Design
• Emerging Nanotechnologies
• +3 more

Dr. Akhilesh Jaiswal serves as Assistant Professor of Electrical and Computer Engineering at the University of Wisconsin-Madison, where his research pioneers device-circuit co-design for next-generation computing systems. His work focuses on enabling extreme-edge intelligence through processing-in-pixel technology, in-memory computing architectures, and bio-inspired neuromorphic systems. His academic credentials include: PhD in Nano-electronics from Purdue University (2019) MS from the University of Minnesota (2014) Bachelor of Technology from Shri Guru Gobind Singhji Institute of Engineering and Technology (2011) Dr. Jaiswal's research program centers on revolutionizing edge computing through hardware innovations that integrate sensing and processing. His device-circuit co-design approach leverages alternate state variables to create energy-efficient systems for real-time applications, with particular emphasis on retina-inspired sensors and photonic memory architectures. This work bridges semiconductor physics with AI acceleration needs, targeting applications from autonomous systems to biomedical devices. Analysis of his 2023-2025 publications reveals dominant themes in photonic SRAM-based in-memory computing (40% of output), retina-inspired motion processing (30%), and secure hardware architectures (20%). His team consistently develops novel bitcell designs that enable XOR logic execution within memory arrays while maintaining compatibility with CMOS fabrication processes. Recent work shows increasing focus on biomedical applications of processing-in-pixel technology. His distinguished recognition includes: Three consecutive ISI Exploratory Research Awards (2020-2023) IEEE Brain Community Best Paper Award (2022) 27 issued US patents with multiple pending applications Nomination for USC Moore Inventor Fellowship (2022) Dr. Jaiswal actively mentors graduate researchers through ECE 790/890/990 courses while securing exploratory funding through ISI and Keston Foundation awards. His patent portfolio demonstrates exceptional translational impact, with industry game-changer classifications from USPTO. The 2022 VLSI-SoC nomination and multiple research highlights in major outlets validate his contributions to hardware security and neuromorphic vision sensors. His laboratory develops integrated hardware platforms combining magnetic tunnel junctions, photonic memory, and CMOS image sensors to create unified processing-in-sensor systems. Current projects include retina-inspired motion segmentation for event cameras and electro-optic frequency transducers for quantum computing interfaces, with strong industry collaboration through patent licensing.

• Device-Circuit Co-design
• Processing-in-Pixel
• In-Memory Computing
• +4 more

Affiliation & Education Scott Hauck is a Professor at the University of Washington's Department of Electrical & Computer Engineering and an Adjunct Professor in Computer Science & Engineering. He leads the Adaptive Computing Machines and Emulators (ACME) Lab . He earned his BS in EECS from UC Berkeley (1990), and MS/PhD in CSE from the University of Washington (1992/1995). Research Focus Dr. Hauck specializes in FPGA-based reconfigurable computing with applications in: Quantum Computing: FPGA controllers for trapped-ion quantum systems enabling precise laser control and quantum state readout. Medical Imaging: Portable radiation sensors for personalized cancer therapy and PET scanner enhancements. High-Energy Physics: FPGA readout systems for ATLAS pixel detectors at CERN's Large Hadron Collider. AI Acceleration: Real-time machine learning inference for scientific applications via projects like hls4ml. His work bridges hardware innovation with computational physics, emphasizing real-time processing and low-latency systems. Publication Trends Recent research focuses on FPGA-accelerated machine learning for particle physics (e.g., transformer networks for LHC trigger systems) and quantum computing instrumentation. Earlier work established foundations in reconfigurable computing architectures and medical imaging electronics. Awards & Recognition Distinguished Teaching Award, University of Washington (2010) Advising & Funding Leads the ACME Lab with extensive funding from NSF, DARPA, NIH, DOE, and industry partners including Intel, Xilinx, and Microsoft. Mentored over 30 MS/PhD students in VLSI, reconfigurable systems, and scientific computing. Collaborations & Labs Directs the ACME Lab (EE1-307), collaborating with UW Radiology (Prof. Robert Miyaoka), UW Physics (Prof. Shih-Chieh Hsu), and Drexel University (Prof. Josh Agar). Projects include quantum control systems, LHC readout electronics, and medical sensor networks.

• Reconfigurable Computing
• FPGA Architecture
• Quantum Computing Control
• +5 more

Naresh R. Shanbhag is the Jack Kilby Professor in the Department of Electrical and Computer Engineering and the Coordinated Science Laboratory at the University of Illinois at Urbana-Champaign. He serves as Director of the Systems on Nanoscale Information fabriCs (SONIC) Center and held the D.J. Gandhi Distinguished Visiting Professorship at IIT Mumbai from 2015-2020. Previously, he was a visiting faculty member at National Taiwan University (2007) and Stanford University (2014). Dr. Shanbhag received his doctorate from the University of Minnesota (1993) in Electrical Engineering. From 1993 to 1995, he worked at AT&T Bell Laboratories as the lead chip architect for AT&T's 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and very high-speed digital subscriber line (VDSL) chip-sets. His research focuses on the design of energy-efficient machine learning, communications, and signal processing systems on resource-constrained embedded platforms. He explores fundamental trade-offs between energy efficiency, latency and accuracy of decision-making systems implemented in nanoscale technologies, with applications to computer vision, biomedicine, automatic target recognition, and imaging. His work spans four primary focus areas: Resource-efficient Machine Learning for the Edge, In-memory Computing (IMC), Energy-efficient High Data Rate Communications, and Shannon-inspired Statistical Error Compensation (SEC). Analysis of his recent publications reveals a strong emphasis on in-memory computing architectures (SRAM, MRAM, RRAM) for machine learning acceleration. His work consistently addresses energy-accuracy trade-offs, with increasing attention to security aspects of hardware implementations and applications to MIMO signal processing and edge AI systems. His research demonstrates a progression from theoretical foundations to practical silicon implementations. 2024 Semiconductor Research Corporation Innovation Award 2018 Semiconductor Industry Association/Semiconductor Research Corporation University Researcher Award 2018 IEEE International Symposium on Circuits and Systems Best Paper Award 2006 IEEE Fellow 1996 National Science Foundation CAREER Award Professor Shanbhag has mentored over 50 graduate students who now work at leading technology companies including Qualcomm, Amazon, Nvidia, Intel, and Apple. His research has been generously supported by the National Science Foundation, DARPA, AFRL, Semiconductor Research Corporation, Texas Instruments, Sandia National Laboratories, and industry partners including IBM, GlobalFoundries, and Intel Corporation. He led the Alternative Computational Models research theme (2006-2012) and was the founding Director of the SONIC Center (2013-2017), a 5-year multi-university center funded by DARPA and SRC. Currently, he leads research themes in the SRC and DARPA funded JUMP 2.0 Program's Center for Co-Design of Cognitive Systems and the Center for Ubiquitous Connectivity, and in the NSF IUCRC Center for Advanced Semiconductor Chips with Accelerated Performance (ASAP). As Director of the Systems on Nanoscale Information fabriCs (SONIC) Center, Professor Shanbhag leads a multidisciplinary team exploring novel computing paradigms for the nanoscale era. His group has benchmarked an extensive collection of in-memory computing and digital accelerator IC designs, maintaining a publicly available IMC benchmarking repository of metrics extracted from published IC prototypes. His research philosophy integrates concepts from information theory, statistical signal processing, detection and estimation, VLSI architectures, and digital and analog integrated circuits to develop energy-efficient systems from algorithms to silicon implementations.

• Energy-efficient computing
• Machine learning hardware
• In-memory computing
• +7 more

Edoardo Charbon is a Full Professor at École Polytechnique Fédérale de Lausanne (EPFL) in the School of Engineering, where he leads the Advanced Quantum Architecture Lab (AQUA). He also serves on the School Council STI and is Co-Director of STI-SSIQ Administration. Previously, he was a full professor and chair at Delft University of Technology from 2008 to 2016. Charbon received his Elektrotechnik Diploma from ETH Zurich, M.S. from UC San Diego, and Ph.D. from UC Berkeley, all in electrical engineering. His career spans industry experience at Cadence Design Systems and Canesta Inc. before joining EPFL in 2002. His research focuses on ultra high-speed and 3D optical sensors, with applications in LiDAR, FLIM (Fluorescence Lifetime Imaging Microscopy), PET (Positron Emission Tomography), FCS (Fluorescence Correlation Spectroscopy), and NIROT (Near-Infrared Optical Tomography). He has pioneered deep-submicron CMOS SPAD technology, which is now mass-produced and used in smartphones, telemeters, and medical diagnostics. His recent work bridges cryo-CMOS circuits for quantum computing with advanced optical sensing techniques. Analysis of his recent publications reveals a strong trend toward integrating quantum technologies with practical imaging applications. His work spans from fundamental device development (SPAD sensors, cryo-CMOS circuits) to applied systems (LiDAR engines, medical imaging devices), with increasing integration of machine learning techniques for real-time processing. 2023 IISS Pioneering Achievement Award Fellow of the IEEE Distinguished visiting scholar, W. M. Keck Institute for Space at Caltech Fellow, Kavli Institute of Nanoscience Delft Distinguished lecturer, IEEE Photonics Society Professor Charbon has authored or co-authored over 500 papers and two books, and holds 27 patents. His research has been supported by collaborations with organizations including Bosch, X-Fab, Texas Instruments, Maxim, Sony, Agilent, and the Carlyle Group. He has driven significant innovation in CMOS SPAD technology, which is now commercially deployed in various applications. He leads the Advanced Quantum Architecture Lab (AQUA) at EPFL, which focuses on the development of advanced sensor systems combining quantum technologies with conventional electronics. The lab has been instrumental in creating SPAD-based imaging systems that push the boundaries of time-resolved optical detection.

• Ultra High-Speed Optical Sensors
• 3D Optical Sensors
• LiDAR
• +10 more

Morteza Fayazi is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Utah, with an adjunct position in the Kahlert School of Computing. His research focuses on Electronic Design Automation (EDA), applying machine learning to automate analog and mixed-signal circuit design, and developing high-performance computing systems. He holds a B.Sc. from Sharif University of Technology, and M.S.E./Ph.D. degrees from the University of Michigan. His research interests include AI-driven EDA, RF/circuit automation, and energy-efficient processors. Key achievements include the MEDAL lab’s work on terahertz radars, systolic-array processors (e.g., DAP and Versa), and open-source frameworks like FASCINET and Tablext. He has received awards such as the 2024 College of Engineering Dean’s ETR Fund and the 2017 Outstanding Undergraduate Thesis Award. Teaching responsibilities include multiple iterations of the Digital System Design course (ECE/CS 3700). His work spans over 15 peer-reviewed articles in IEEE Transactions, ACM, and top conferences like ICCAD and VLSI-SOC, emphasizing automation, efficiency, and AI integration in hardware design.

• Electronic Design Automation (EDA)
• Machine Learning (ML) in Analog Circuit Design
• System-on-Chip (SoC) Design Automation
• +3 more

Alan Stocker is a Professor in the Department of Psychology at the University of Pennsylvania, affiliated with the Neuroscience Graduate Group, Bioengineering Graduate Group, and Computational Neuroscience Initiative. His research focuses on understanding how prior beliefs and expectations shape visual perception, combining theoretical models with psychophysical and physiological experiments. Key areas include optimal inference frameworks, neural coding efficiency, and decision-making under uncertainty. Education: PhD in Physics (ETH Zurich, 2002); MSc in Biomedical Engineering and Materials Science (ETH Zurich, 1995). Prior appointments include postdoctoral work at New York University and ETH Zurich. Research Interests: Behavioral Neuroscience, Cognitive Neuroscience, Sensation and Perception. Specific projects explore statistical properties of visual environments, subjective expectations from past decisions, and neural computations underlying perception. Advising: Current advisees include Cheng Qiu (Postdoc), Ansh Soni, and Mengting Fang (Graduate Students). Courses taught: Perception, Visual Neuroscience, and Probabilistic Models in Perception and Cognition. Labs/Teams: Leads the Computational Perception and Cognition (CPC) Laboratory, emphasizing theory-driven experimentation. Collaborates widely across disciplines including bioengineering and electrical systems engineering.

• Behavioral Neuroscience
• Cognitive Neuroscience
• Sensation and Perception
• +4 more

Manoj Sachdev is a Professor in the Department of Electrical and Computer Engineering at the University of Waterloo, Faculty of Engineering. His research focuses on semiconductor devices, low-power electronics, and secure hardware systems. He leads projects in flexible electronics, nanotechnology, and radiation-hardened circuits, with applications in displays, memory technologies, and biomedical sensors. His work integrates advanced materials science with circuit design to address challenges in energy efficiency and security. Education: Not explicitly stated in provided text. Research interests span thin-film transistors (TFTs), resistive switching memories, neuromorphic computing, and physically unclonable functions (PUFs). Recent efforts include developing low-power circuits for flexible substrates and secure microprocessors. His contributions to semiconductor device physics and integration techniques have advanced applications in wearable electronics and medical diagnostics. Publications highlight innovations in low-power flip-flops, energy-efficient display drivers, and memristor-based systems. He collaborates on interdisciplinary projects combining photonics, nanoelectronics, and biomedical engineering. Awards: None explicitly listed in provided text. Grants and advising: Advises on semiconductor fabrication, secure hardware design, and radiation effects in electronics. Leads research groups focused on next-generation memory technologies and flexible integrated systems. Labs/Teams: Active in the University of Waterloo's semiconductor and flexible electronics research clusters, contributing to both academic and industry partnerships.

• Semiconductor Devices
• Low-Power Electronics
• VLSI Design
• +7 more

Supratik Chakraborty serves as the Bajaj Group Chair Professor in the Department of Computer Science and Engineering at Indian Institute of Technology Bombay. He maintains dual affiliations with the Centre for Formal Design and Verification of Software and the Centre for Liberal Education at IIT Bombay, demonstrating his cross-disciplinary engagement. Professor Chakraborty's research spans formal methods with focus on formal verification, rigorous analysis of system models, and automated synthesis of systems from specifications. His work bridges theoretical foundations with practical applications, particularly in developing mathematically provable guarantees for increasingly complex hardware, software, and intelligent systems. Current research interests include constrained counting and sampling, scalable formal verification of software and hardware systems, automated synthesis of programs and circuits, and applications of automata, logic and finite model theory to practical verification challenges. His publication trajectory shows a significant evolution from traditional hardware and software verification toward addressing verification challenges in machine learning and AI systems. Recent work increasingly focuses on interpretability of black-box models, verification of neural networks, and synthesis techniques applicable to intelligent systems. The research demonstrates strong interdisciplinary connections between formal methods, programming languages, and artificial intelligence. IIT Bombay Excellence in Thesis (CSE) Award 2011 (for Bhargav Gulavani's thesis) IIT Bombay Excellence in Thesis (CSE) Award 2017 (for Abhisekh Sankaran's thesis) Best Paper in Algorithms and Architecture track at IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1998 Professor Chakraborty has successfully supervised 11 doctoral students, with research spanning formal verification techniques, Boolean functional synthesis, constrained counting, and applications to hardware and software systems. His students have gone on to positions at major institutions including Microsoft Research, TCS Research, Georgia Tech, and BARC, reflecting the strong industry and academic impact of his mentorship. Current research directions show increasing emphasis on verification challenges posed by machine learning systems and AI. His research group at IIT Bombay, while not explicitly named in the materials, appears to focus on formal methods with strong connections to the Centre for Formal Design and Verification of Software. The group maintains active collaborations with international researchers including Moshe Y. Vardi at Rice University, and has made significant contributions to verification tools like VeriAbs that bridge theoretical advances with practical applications.

• Formal Methods
• Formal Verification
• Automated Synthesis
• +7 more

Soheil Salehi is a tenure-track Assistant Professor in the Department of Electrical and Computer Engineering at the University of Arizona, with a joint appointment in Systems and Industrial Engineering. He is the Director of the Privacy-preserving, Intelligent, and Secure Computing (PRISM) Lab, established in August 2022. Prior to this, he was an NSF-Sponsored Computing Innovation Fellow and Postdoctoral Research Fellow at the University of California, Davis. Ph.D., Electrical and Computer Engineering, University of Central Florida, 2020 M.S., Electrical and Computer Engineering, University of Central Florida, 2016 B.S., Isfahan University of Technology, Iran, 2014 Dr. Salehi's research focuses on the intersection of hardware, AI, and security. His work spans hardware and AI-enabled security in IoT , Generative AI for hardware design and security , neuromorphic and biologically-inspired AI hardware , emerging spin-based devices , reconfigurable architectures , low-power VLSI circuits , and digital twins and mixed reality for semiconductor workforce development . He also explores the application of Generative AI in personalized education . His recent publications, spanning 2023–2025, reveal a strong trend toward integrating AI and machine learning into hardware security and design. Key themes include automated secure IC design flows , AI-driven hardware obfuscation , firmware and side-channel attack analysis , security in neuromorphic and spiking neural networks , and educational frameworks using digital twins and generative models . His work appears in top venues like DAC, ICCAD, USENIX Security, IEEE TCAS-I, and ISCAS. Outstanding Reviewer Award, IEEE/ACM Design Automation Conference (DAC), 2023 Best Presentation of the Symposium Award, UC Davis Postdoctoral Research Symposium, 2021 UCF Excellence by a Graduate Teaching Assistant (University-Level), 2016 Nominated for 30-under-30 Award, UCF, 2020 Nominated for Postdoctoral Research Excellence Award, UC Davis, 2022 Dr. Salehi has secured significant research funding as PI and Co-PI, including a $300K NSF SaTC EAGER grant on Generative AI-based Personalized Cybersecurity Tutor, a $174,000 University of Arizona PIF Award, and multiple RII grants totaling over $198K. He has also received industry funding from CHEST. He actively mentors students and leads the PRISM Lab, which focuses on privacy-preserving and intelligent secure computing. His service includes roles as Technical Program Committee (TPC) Member and Session Chair at premier conferences such as DAC, ICCAD, CCS, NDSS, and GLSVLSI. The PRISM Lab, under his direction, conducts cutting-edge research in secure and intelligent hardware systems, with applications in IoT, edge computing, and workforce development. The lab emphasizes interdisciplinary collaboration and innovation in both research and education.

• Hardware Security
• AI-Enabled Security
• Internet of Things (IoT) Security
• +15 more

Prof. Baker Mohammad serves as Professor and Director of the System on Chip Lab in the Department of Computer and Information Engineering at Khalifa University. With over 15 years of industrial experience at Intel and Qualcomm designing microprocessors and DSP chips, he bridges academic research with real-world engineering challenges in high-performance computing and low-power systems. His educational background includes: Ph.D. in Electrical and Computer Engineering, University of Texas at Austin (2008) M.S. in Electrical and Computer Engineering, Arizona State University B.S. in Electrical Engineering, University of New Mexico Dr. Mohammad's research spans cutting-edge domains where VLSI design converges with AI acceleration and emerging memory technologies . His work pioneers Memristor applications in environmental sensing (radiation, vacuum, glucose) and neuromorphic computing, while advancing energy harvesting systems for wearable electronics. The integration of in-memory computing with security primitives represents a paradigm shift in hardware design, moving beyond traditional CMOS limitations. His publication trajectory reveals accelerating focus on self-powered neuromorphic systems and RRAM-based architectures, with recent work (2021-2023) emphasizing hardware-software co-design for edge AI. Over 75% of his recent publications involve cross-disciplinary collaborations spanning materials science, chemistry, and biomedical engineering. Notable scientific recognition includes: IEEE TVLSI Best Paper Award 2016 IEEE MWSCAS Myrill B. Reed Best Paper Award Qualcomm Qstar Award for Performance Leadership KUSTAR IP Excellence Award Multiple SRC Techon Best Session Papers As a dedicated mentor, he has supervised over 15 graduate students while securing competitive funding from Khalifa University, ADEK, Qualcomm, Tii, and UAE space agencies. His grant portfolio demonstrates exceptional translational impact, converting fundamental research in memristive devices into drone flight computers and medical sensors. Current projects integrate academic rigor with industrial deployment timelines. The System on Chip Lab operates as a multidisciplinary hub where semiconductor physicists collaborate with AI researchers to develop RISC-V-based secure processors and piezoelectric nanogenerator systems. Recent expansions include partnerships with Tii for aerospace applications and medical device startups for glucose monitoring technology.

• Very-Large-Scale Integration (VLSI)
• Hardware Accelerators for Artificial Intelligence
• Hardware Security
• +7 more