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Caroline Trippel is an Assistant Professor in the Departments of Computer Science and Electrical Engineering at Stanford University. Her research focuses on ensuring correctness and security in computer systems through formal methods, with particular emphasis on hardware verification, memory consistency models, and mitigating vulnerabilities like Spectre/Meltdown. She previously worked at Facebook’s FAIR SysML group before joining Stanford. Education: PhD in Computer Science, Princeton University BS in Computer Engineering, Purdue University Her work has influenced the RISC-V ISA memory consistency model and produced tools like CheckMate, which automatically synthesizes hardware exploits for security verification. She explores privacy-preserving ML, ML-driven hardware optimizations (e.g., neural recommendation), and datacenter reliability. Her research has earned awards including the 2020 ACM SIGARCH Dissertation Award and NVIDIA Fellowship. Key contributions include: Formal analysis of RISC-V memory models Exploitation synthesis frameworks (CheckMate) Hardware-software contracts for security Defenses against microarchitectural side-channel attacks Current projects include: VeriCoder: LLM-enhanced RTL code verification Multi-μPATH synthesis for security validation Near-data processing (RecSSD) for recommendation systems

• Computer Architecture
• Hardware Security
• Formal Methods
• +5 more

Cynthia Sturton serves as Associate Professor and Peter Thacher Grauer Scholar in the Department of Computer Science at the University of North Carolina at Chapel Hill. She leads the Hardware Security @ UNC research laboratory focused on developing formal verification tools for hardware security analysis. Her educational background includes a Ph.D. (2013) and M.S. from UC Berkeley, and a B.S.Eng. from Arizona State University. Her research centers on hardware security, applied formal methods, and symbolic execution techniques for identifying security vulnerabilities in processor designs before fabrication. Sturton's research demonstrates consistent innovation in hardware security verification, particularly through tools like Sylvia (symbolic execution for Verilog) and SylQ-SV (SystemVerilog analysis with query caching). Her work bridges theoretical formal methods with practical security applications, addressing critical challenges like path explosion and security property generation at scale. Nominated for Best Paper award at IEEE/ACM MICRO 2018 Intel Hardware Security Academic Award, 2nd place ($50,000) at IEEE Symposium on Security and Privacy 2020 Selected as Top Picks in Hardware and Embedded Security 2021 She advises multiple graduate students including Rui Zhang and Calvin Deutschbein, and has secured significant research funding from NSF (Grants 1816637, 651276), Semiconductor Research Corporation, Intel, Google, and UNC Chapel Hill. Her Hardware Security @ UNC lab develops critical tools for security property generation and vulnerability detection in hardware designs.

• Hardware Security
• Formal Methods
• Computer Security
• +4 more

Dr Graeme Bragg is a Senior Teaching Fellow at the University of Southampton within the Department of Electronics and Computer Science . His work spans teaching, research, and technical development with a focus on event-driven computing, bioinformatics, and computational modeling. He actively supervises PhD students and collaborates on interdisciplinary projects. Research Interests: Parallel computing, event-driven systems, genotype imputation, Petri net simulations, subglacial hydrology modeling Teaching: Specializes in hardware description languages and computational methods for engineering students Technical Expertise: RISC-V architecture, FPGA acceleration, bespoke compute fabric development His recent publications demonstrate expertise in applying event-driven computing to diverse problems including: 2025: Automated marking systems for SystemVerilog labs 2025: Seasonal dynamics in subglacial hydrology 2023: Genotype imputation using custom hardware 2022: Optimization algorithms and graph analysis Current research explores: Custom RISC-V FPGA clusters for bioinformatics Event-triggered systems for scientific simulations Parallel computing solutions for molecular modeling Contact: gmb@ecs.soton.ac.uk | +44 23 8059 2784

• Parallel Computing
• Event-driven Systems
• Bioinformatics
• +5 more

Jules Field is a Senior Tutor at the University of Southampton , actively contributing to academic and technical advancements. His work focuses on Open-source software development Cybersecurity infrastructure Educational technology innovation He maintains a strong presence in digital education and system security. His publications span 25 years and demonstrate expertise in: Automated marking systems Email security frameworks Internet security policy Notably, he has developed practical resources like the MailScanner User Guide and participated in foundational cybersecurity research for higher education. As an academic consultant and technical expert, Jules combines teaching responsibilities with real-world software engineering challenges, particularly in security and sustainability domains.

• Cybersecurity
• Software Engineering
• Educational Technology
• +3 more

Sarah Harris is Professor and Undergraduate Coordinator in the Department of Electrical and Computer Engineering at University of Nevada, Las Vegas. Her research focuses on computer architecture education, FPGA-based systems, and hardware implementations of neural networks. Research areas include: RISC-V architecture education tools FPGA-based hardware design Embedded AI systems Computer engineering pedagogy Her publication portfolio shows strong focus on educational innovation with 7 publications (2021-2024) on RISC-V teaching tools and MOOCs, alongside hardware implementations of neural networks and contributions to bioinformatics tools. Earlier work includes digital design fundamentals and memory systems.

• Computer Architecture
• FPGA Design
• RISC-V Systems
• +3 more

Professor Martin Schoeberl is affiliated with the Department of Applied Mathematics and Computer Science at the Technical University of Denmark (DTU). His research focuses on real-time systems, worst-case execution time analysis, and embedded systems engineering. He is actively involved in projects such as Rigoletto, aiming to develop high-performance automotive processors using RISC-V architecture. Research Interests: Schoeberl's work spans time-predictable processors, network-on-chip architectures, and hardware-software co-design for cyber-physical systems. He explores methodologies to ensure deterministic behavior in multicore environments and develops tools for WCET analysis. His contributions include advancements in compiler optimizations for neural networks and temporal semantics in embedded systems. Advising & Grants: Schoeberl supervises PhD students such as E. Khodadad (on rigorous design of time-predictable systems) and A. Cerioli (on compiler optimizations for neural networks). He leads or participates in funded projects including Rigoletto (2025-2028) and Multi-Core Architecture for L1 Deterministic Processing (2022-2025). These projects aim to enhance real-time capabilities in embedded systems and automotive computing platforms. Labs & Teams: As part of the Embedded Systems Engineering group at DTU, Schoeberl collaborates on hardware generators using Chisel and designs reactor-oriented architectures for cyber-physical systems. His work integrates reconfigurable logic and synchronous models to create efficient, time-predictable solutions.

• Real-Time Systems
• Embedded Systems
• Multicore Processing
• +3 more

Michael S. Hsiao is a Professor in the Bradley Department of Electrical and Computer Engineering at Virginia Tech. His research focuses on design, test, verification, and diagnosis of complex hardware and software systems. He earned his Ph.D., M.S., and B.S. in Electrical Engineering from the University of Illinois. Notably, he was elected an IEEE Fellow in 2013 for contributions to automatic test pattern generation. His work spans natural language processing in hardware verification, hybrid AI systems, and formal methods. He has authored over 80 peer-reviewed publications and led significant research projects. Education: Ph.D., University of Illinois, 1997 M.S., University of Illinois, 1993 B.S., University of Illinois, 1992 Research Interests: Testing and Verification of Hardware Systems Computer Architecture and Digital Design Algorithm Development for Hardware Diagnostics Natural Language Processing in Design Automation Recent Article Trends: Recent work emphasizes integrating NLP with formal verification (e.g., translating English specifications to SystemVerilog assertions), hybrid AI systems for intent clarification, and robotic path-finding using natural language. These contributions bridge abstract language-based specifications with rigorous engineering validation. Awards: IEEE Fellow (2013) – For contributions to automatic test pattern generation of integrated circuits Advising & Grants: While specific student names are not listed here, his research has been supported by over 160 projects. He has also contributed to industry collaborations, including work on anti-counterfeit ICs and hardware security.

• Testing Verification
• Computer Architecture
• Digital Design
• +5 more

Arto Oinonen is a Lecturer at Tampere University , affiliated with the Faculty of Information Technology and Communication Sciences and the Department of Computing Sciences . His work bridges academic instruction and research in advanced computing technologies. Dynamic Resource Allocation in SDN Cloud Hardware Acceleration for HEVC and IPsec SystemVerilog and UVM Implementation Oinonen's research focuses on FPGA-based hardware acceleration for video encoding (HEVC) and network security protocols (IPsec) in cloud environments. His publications analyze optimization strategies for resource allocation, latency reduction, and energy efficiency in programmable logic architectures. He also contributes to educational frameworks for SystemVerilog and UVM in digital design training. Key collaborations include researchers at Tampere University's System-on-Chip Design group. His work has been cited in academic and patent literature, with a focus on practical implementations in cloud and networked systems.

• FPGA
• HEVC Encoding
• Software-Defined Networking
• +6 more

Prof. Dr. Mario Fritz is a Professor at Saarland University and faculty member at CISPA Helmholtz Center for Information Security. He serves as a Fellow at the European Laboratory for Learning and Intelligent Systems (ELLIS). His research focuses on Trustworthy Information Processing at the intersection of AI & Machine Learning with Security & Privacy. Mario Fritz leads numerous significant research initiatives including the European Large Open Multi-Modal Foundation Models for Robust Generalization (ELLIOT), European Lighthouse on Secure and Safe AI (ELSA), and multiple projects on privacy-preserving AI applications in healthcare. His work spans security and privacy aspects of large language models, foundation models, and medical AI applications. He has established himself as a leading researcher in trustworthy AI through his extensive publication record and leadership in major collaborative projects. His recent research (2025 publications) demonstrates a strong focus on the security and safety challenges of large language models, including model stealing attacks, causal reasoning capabilities, sampling methods, and privacy risks. His work bridges theoretical foundations with practical applications across multiple domains, particularly in healthcare and cybersecurity. Mario Fritz actively mentors PhD students and Post-Docs, seeking new researchers to join his group. He has been involved in numerous grants and collaborative projects, including those funded by BMBF and the Helmholtz Association, demonstrating his ability to secure substantial research funding and lead large interdisciplinary teams.

• Artificial Intelligence
• Machine Learning
• Cybersecurity
• +7 more

José L. Sánchez is a full Professor in the Department of Computer Systems at the University of Castilla-La Mancha (Spain), where he has held a permanent academic position since 1986. His research spans high-performance computing, network architecture, and GPU acceleration, with particular focus on energy-efficient interconnection networks for data centers and exascale systems. His research interests center on interconnection network optimization , including torus topologies, deadlock-free routing, and QoS provision in high-radix switches. He pioneers energy-efficient networking through on/off link strategies and develops frameworks like VEF traces for modeling MPI traffic in large-scale simulations. His work bridges theoretical network design with practical GPU-accelerated implementations for real-time computer vision and similarity search algorithms. Recent publications reveal a strong trend toward exascale-ready networking solutions , with 60% of his 2019-2022 work addressing energy efficiency in HPC topologies, congestion management in lossy networks, and photonic interconnect challenges. His methodology consistently combines formal network modeling with hardware-aware implementations, particularly leveraging GPU parallelism for bioinspired vision algorithms and metric search optimization. Professor Sánchez leads significant contributions to network simulation tooling, including the TopGen library for topology modeling and VEF3 framework extensions. His collaborative work spans multiple EU institutions, with frequent co-authorship patterns indicating strong ties to research groups specializing in network-on-chip systems and high-performance interconnects.

• High-Performance Computing
• Computer Networks
• Parallel Computing
• +5 more

Professor Matthias Fertig serves as Professor of Digital Systems at the Faculty of Electrical Engineering and Information Technology, Konstanz University of Applied Sciences. His academic profile bridges theoretical research with practical engineering applications in digital systems design. His research portfolio spans several critical domains: Near-/In-Memory Computing (Universal Memory Automata theory) Digital HDL Design methodology (RAPID VHDL package development) Massively Parallel EM-Simulation optimization Computational Optics using advanced Fourier methods (WPM/VWPM) ASIC design and implementation workflows Prior to academia, Professor Fertig gained substantial industry experience at IBM (microprocessor design), Dialog Semiconductor (Power Management ICs), and Volvo Construction Equipment (control systems for heavy machinery). This background informs his practical teaching approach that emphasizes real-world applications alongside theoretical foundations. His professional recognition includes an invitation to join the Editorial Board of the American Journal of Computer Science and Technology (AMJCST) in May 2025. Professor Fertig actively develops new course content, with a 'uProcessor Architecture' course scheduled for summer term 2026. He teaches across the curriculum from undergraduate Digital Engineering courses through specialized Master's level laboratories in Silicon Photonics and Electromagnetic Simulation, utilizing industry-standard Cadence tools to provide students with professional design experience.

• Digital Systems
• Microprocessor Architecture
• VHDL Design
• +6 more

Richard Townsend serves as an Assistant Teaching Professor in the Department of Computer Science within the School of Engineering at Tufts University. He joined the institution in September 2019 after completing his Ph.D. at Columbia University, making a transition from research to teaching. Townsend is also the Founding Director of the Emerging Scholars Program in the Computer Science Department at Tufts University. His educational background includes a Doctor of Philosophy (2019), Master of Philosophy (2016), and Master of Science (2015) from Columbia University, along with a Bachelor of Arts in Computer Science from Oberlin College (2013). Townsend's research focuses on the application of functional programming languages to hardware design, specifically developing techniques to translate recursive algorithms with irregular memory access patterns into efficient hardware implementations. His work centers around an optimizing Haskell-to-SystemVerilog compiler project, exploring the semantic connections between functional languages and hardware specifications. He specializes in compilers for embedded systems, program analysis and optimization, and embedded domain-specific languages. His publication record demonstrates consistent contributions to the intersection of functional programming and hardware design, with multiple papers on compositional dataflow circuits, hardware synthesis from functional languages, and resource allocation for hardware implementations. His work shows a clear trajectory from theoretical foundations to practical implementations in hardware compilation. Senior Survey 2022 Significant Impact and Best Course (2022) Significant Impact Award (2021) Significant Impact Award (2020) Townsend actively mentors junior faculty through the Teaching Track Faculty Mentoring program and serves on various committees including the Teaching Track Search Committee and Computer Science Curriculum Committee. He teaches a range of courses including Programming Languages, Introduction to Computer Science, and specialized topics like Algorithmic Music Composition. His teaching approach incorporates evidence-based STEM teaching practices, as evidenced by his participation in multiple teaching development programs.

• Functional languages
• Compilers for embedded systems
• Program analysis and optimization
• +5 more

Peter Sewell is Professor of Computer Science at the University of Cambridge Computer Laboratory, where he leads the REMS group (Rigorous Engineering for Mainstream Systems). He is a Fellow of Wolfson College and a Fellow of the Royal Society. His research focuses on applying formal semantics to improve the foundations, robustness, and security of real-world computer systems. His research spans architecture specification, programming languages, verification, security, and networking, developing techniques from semantics, type systems, automated reasoning, and concurrency theory. He is particularly known for his work on the CHERI (Capability Hardware Enhanced RISC Instructions) project, which extends conventional hardware ISAs with new architectural features for fine-grained memory protection and software compartmentalization. His group has been instrumental in developing the Arm Morello evaluation platform as part of the UKRI Digital Security by Design Challenge. His publications reveal a strong focus on formal verification of hardware and software systems, with particular emphasis on memory safety, relaxed memory concurrency, and capability-based security architectures. Recent work demonstrates increasing industrial relevance, with collaborations with Arm, Google, IBM, and RISC-V International. Fellow of the Royal Society Sewell leads the REMS group, which was originally funded by an EPSRC Programme Grant and continues with funding from the EU ERC AdG ELVER (2018-2024), the ERC/UKRI Frontier Guarantee AdG SAFER (2024-2029), and donations from Arm, Google, Intel, and Amazon. His group develops tools like Sail (for ISA specification), Cerberus (for C semantics), and Lem (for semantics engineering).

• Formal Semantics
• Programming Languages
• Computer Architecture
• +7 more

Prof. Michael Pichler serves as a Professor at the University of Applied Sciences and Arts Northwestern Switzerland (FHNW) within the School of Engineering and Environment. He holds dual leadership roles as Head of the Microelectronics Team at the Institute for Sensors and Electronics and Programme Head for the Master of Advanced Studies (MAS) in Microelectronics, while also delivering instruction in Embedded System Engineering. His research expertise centers on Microelectronics and Embedded Systems, with specialized focus on Digital Design methodologies and Hardware Verification techniques. Prof. Pichler's technical proficiency includes industry-standard hardware description languages VHDL and SystemVerilog, particularly through PSL assertion-based verification approaches. Leading the Microelectronics Team at FHNW's Institute for Sensors and Electronics, Prof. Pichler drives initiatives in digital circuit validation and embedded systems development. His role as MAS Programme Head demonstrates significant commitment to advanced professional education in semiconductor technologies. While specific details regarding student supervision and research funding are not documented in the source material, his institutional responsibilities indicate active engagement in shaping microelectronics education and industry-relevant research at FHNW's Brugg-Windisch campus.

• Microelectronics
• Embedded Systems
• Digital Design
• +3 more

Minxue Pan is a Professor and PhD supervisor at the Software Institute, State Key Laboratory for Novel Software Technology, Nanjing University, China. His research focuses on the dependability of complex software systems, with expertise spanning software modeling and verification, software analysis and testing, cyber-physical systems, mobile computing, and intelligent software engineering. Ph.D. in Computer Science and Technology from Nanjing University (2014), supervised by Prof. Xuandong Li B.Sc. from Nanjing University Studied at UC Berkeley's Department of Electrical Engineering and Computer Sciences (2009-2010) under Prof. Edward A. Lee Professor Pan's research interests center on improving software dependability through innovative approaches to modeling, analysis, and testing. His work spans traditional software systems, mobile applications (particularly Android), cyber-physical systems, and the application of AI techniques to software engineering problems. He has made significant contributions to GUI testing, vulnerability detection, and deep learning applications in software engineering. His recent publications (2024-2025) demonstrate a strong focus on applying advanced machine learning techniques to software testing and security challenges. Key trends include leveraging large language models for test migration, enhancing fault localization with graph learning and contrastive learning, developing specialized frameworks for Android security analysis, and improving test efficacy through GUI and functional equivalence. His work consistently targets real-world industrial settings and addresses practical challenges in mobile and complex software systems. ISSTA 2020 Distinguished Paper Award ICSE 2025 Best Artifact Award Professor Pan actively advises graduate students and has developed several notable tools including Q-testing (reinforcement-learning based Android testing), ISDChecker (model checking for interrupt-driven systems), PREFEST (preference-wise testing for Android), Sketchoid (GUI code search), and PI-REC (hand-drawn draft conversion). His research is supported by extensive publication records in top-tier software engineering venues including ASE, ICSE, FSE, ISSTA, and TOSEM. He teaches undergraduate courses in Advanced Programming with C++, Software System Design, and Software Construction, as well as graduate courses in Advanced Software Design. His laboratory work focuses on developing practical solutions for real-world software dependability challenges through the State Key Laboratory for Novel Software Technology.

• Software Modelling and Verification
• Software Analysis and Testing
• Cyber-Physical Systems
• +5 more