Björn Brandenburg is a researcher at the Max Planck Institute for Software Systems (MPI-SWS) in Kaiserslautern, Germany. His work focuses on real-time systems, scheduling algorithms, and operating system design, with a particular emphasis on predictable resource allocation and performance guarantees in multiprocessor and cyber-physical environments. His research interests include real-time response-time analysis (e.g., PROSA ), locking protocols for multiprocessor systems, side-channel mitigation in cloud environments, and the verification of real-time scheduling policies. He has contributed to foundational studies on deadline failure probabilities, self-suspending tasks, and predictable real-time Linux implementations. Scientific awards include recognition for outstanding papers on TimerShield (2017) Offline Equivalence (2017) . His work intersects with practical systems like LITMUSRT and ROS 2, aiming to bridge theoretical guarantees with real-world applications in safety-critical and distributed real-time systems.
Brandon Lucia is a Professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University's College of Engineering. He holds the Kavčić-Moura Professorship and leads the Abstract research group. As CEO and co-founder of Efficient Computer Corp., he bridges academic research with commercial applications in energy-efficient computing. Dr. Lucia received his Ph.D. in Computer Science and Engineering from the University of Washington in 2013, following an MS from the same institution in 2010 and a BS in Computer Science from Tufts University in 2007. His research focuses on the intersection of computer architecture, computer systems, and programming languages, particularly in energy-constrained environments. His primary research interests include intermittent computing, energy harvesting computers, orbital edge computing, and parallel computing systems. Lucia's work addresses fundamental challenges in creating programmable, reliable computing devices that operate without batteries by harvesting energy from their environments, with applications in sensing, medical implants, and space systems. He also investigates software systems and architectures for making parallel computing correct, reliable, and efficient in the post-Moore's Law era. Lucia's publication record shows a clear trajectory toward orbital edge computing and nanosatellite systems, with recent work focusing on computational constellations, visual navigation for satellites, and energy-efficient processing in space. His research spans both theoretical foundations of intermittent computing and practical implementations in hardware and software. 2021 Sloan Research Fellowship 2018 NSF CAREER Award 2018 ASPLOS Best Paper Award IEEE MICRO Top Picks in Computer Architecture (2009, 2010, 2016) 2015 OOPSLA Best Paper Award 2019 IEEE TCCA Young Computer Architect Award 2022 Engineering Faculty Award As an advisor, Lucia has mentored numerous graduate students including Brad Denby, Zhuo Cheng, and Kyle McCleary, many of whom have become co-authors on his significant publications. His lab developed the world's first batteryless PocketQube nanosatellite (Tartan-Artibeus-1), which was deployed to low-Earth orbit aboard the SpaceX Transporter-3 Rocket. Lucia's research has received funding from sources including NSF, DARPA, Google, and VMware, supporting both fundamental research and practical implementations of energy-harvesting computing systems.
Michael Ferdman is an Associate Professor in the Department of Computer Science at Stony Brook University, where he leads research in computer architecture and systems. His office is located in Room 343 at Stony Brook, NY 11794-2424, and he can be contacted via phone (631-632-8449) or email. Ferdman directs the Computer Architecture and Systems Laboratory (compas.cs.stonybrook.edu), focusing on next-generation server infrastructure. Ferdman's research spans the entire computing stack with emphasis on: FPGA integration for server environments (Intel HARP, Microsoft Catapult) Machine learning accelerators for convolutional neural networks Server systems optimization in the post-Moore era Network processing and software-defined networking Programming models for emerging memory technologies (HBM, 3D XPoint) Reconfigurable hardware and high-level synthesis His work addresses both performance and security challenges in modern computing infrastructure. Analysis of his 15 most recent publications (2022-2025) reveals consistent focus on: Hardware acceleration techniques (FPGAs, specialized processors) Memory hierarchy optimization and cache management Security vulnerabilities in web applications and systems Post-Moore computing architectures Parallel processing and distributed systems His research shows strong emphasis on practical implementations bridging hardware and software layers. Awards recognizing his contributions include: Graduate Teaching Award (2014) Best Paper Award at ASPLOS XVII Best Paper Finalist at HPCA XVII Three IEEE Micro Top Picks selections (2009, 2012) He teaches advanced courses including CSE 502, CSE 602, and CSE 506 at Stony Brook University.
Moinuddin Qureshi is a Professor of Computer Science at Georgia Institute of Technology, affiliated with the School of Computer Science and involved in the Online Master of Science in Computer Science (OMSCS) program. He holds a Ph.D. and M.S. from the University of Texas at Austin. His research focuses on computer architecture, memory systems, hardware security, and quantum computing, with notable contributions to mitigating rowhammer vulnerabilities and advancing quantum error correction. Previously, he was a Research Staff Member at IBM T.J. Watson Research Center (2007–2011), where he contributed to caching algorithms for Power-7 processors. He has held leadership roles, including Program Chair of MICRO 2015 and Selection Committee Co-Chair of Top Picks 2017. His work has been recognized with prestigious awards, including the 2019 Persistent Impact Prize and multiple best paper awards. Key research areas include secure memory design (e.g., rowhammer mitigation techniques like MINT and Moat), quantum computing (e.g., Flag-Proxy Networks and Élivágar), and hardware vulnerability analysis (e.g., Roguerfm attacks and COAXIAL memory systems). His publications span 2009–2025, addressing topics like error correction, secure tracking, and quantum annealing optimization. Awards include membership in ISCA, MICRO, and HPCA Hall of Fame, alongside contributions to conferences like HiPC and IEEE MICRO. His work bridges theoretical advancements with practical implementations in both classical and quantum domains.
Dr. Feng Yan is an Associate Professor at the University of Houston's Computer Science Department, leading the Intelligent Data and Systems Lab (IDS Lab). He previously held an Associate Professor position at the University of Nevada, Reno. His research focuses on bridging Big Data, Machine Learning, and Systems, with interdisciplinary applications in wildfire science, materials engineering, and civil infrastructure. He has received prestigious awards such as the NSF CAREER Award and the Regents' Rising Researcher Award. Education: Ph.D. (2016) and M.S. (2011) in Computer Science from College of William and Mary; B.S. (2008) in Computer Science from Northeastern University. Research experience includes roles at Microsoft Research and HP Labs. Research Interests: Large Language Models (LLM), Distributed Deep Learning, AutoML, Serverless Computing, Federated Learning, and AI-driven domain sciences. His work emphasizes real-world impact through collaborations with industry and national labs. Publications: Over 60+ papers in top-tier venues like NeurIPS, ICLR, KDD, AAAI, SOSP, SC, and VLDB. Key contributions include ZeRO++ (collective communication optimization), Gradient Compression techniques, and Federated Learning frameworks like TiFL and HDFL. Awards: NSF EPSCoR Award ($20M), NSF CAREER Award, FAA BAKFAA Grant, and multiple best paper awards (IEEE CLOUD 2018, CLOUD 2019). Active in program committees for HPDC, ICAC, ICPE, and AAAI. Advising: Supervised over 30+ graduate/undergraduate students, with placements at Microsoft Research, IBM, Oak Ridge National Lab, Facebook, and MathWorks. Runs a vibrant lab with a focus on interdisciplinary AI/Systems research.
Rajeev Balasubramonian is a Professor and Associate Director at the School of Computing, University of Utah. He specializes in computer architecture, with a focus on memory systems, emerging technologies, and energy-efficient computing. His research addresses challenges in DRAM/NVM architectures, security, and acceleration for big data and machine learning workloads. Education: PhD in Computer Science (University of Rochester, 2003), M.S. (University of Rochester, 2000), B.Tech in Computer Science (IIT Bombay, 1998). Research Interests: Memory reliability, near-data processing, cache hierarchies, transactional memory, and hardware-software co-design for emerging technologies. He has led projects on crossbar accelerators, secure memory systems, and resistive memory architectures. Recent Trends in Publications: Focus on encrypted inference (Hyena), data prefetching (PATHFINDER), and neuromorphic computing (SpinalFlow). His work bridges hardware and software, emphasizing practical acceleration and security solutions. Awards: IEEE Fellow (2021), Google Faculty Awards (2019/2020), Intel Research Award (2017), and multiple best paper awards (ISCA, ISPASS, PACT). Grants & Students: Over $4M in NSF/industry funding. Advised 15+ PhD students (e.g., Ali Shafiee, Karl Taht) and currently mentors researchers in resistive memory and security accelerators. His lab includes teams like Utah Arch Research Group. Labs & Teams: Leads the Utah Arch Research Group , organizing workshops on near-data processing and memory systems (e.g., ISCA, HPCA).
Trevor E. Carlson is an Assistant Professor at the School of Computing, National University of Singapore (NUS), focusing on high-efficiency microarchitectures, hardware/software co-design, and secure chip design for IoT and server applications. He earned his Ph.D. in Computer Science from Ghent University (2014) and B.Sc./M.Sc. in Electrical & Computer Engineering from Carnegie Mellon University (2002/2003). Research Interests include energy-efficient processors, secure computing platforms, neuromorphic accelerators, and fast simulation methodologies. He co-developed the Sniper Multi-Core Simulator used globally for performance/power evaluation. Scientific Awards : Best Paper Award, International Conference on Embedded Computer Systems (2016) Best Paper Award, International Symposium on Performance Analysis of Systems and Software (2013) Heidelberg Laureate Forum participation (2015) HiPEAC Technology Transfer Award for Sniper Simulator (2013) Current Research involves secure Systems-on-Chip (SOCure project), hardware security for IoT, and simulation methodologies. He leads a lab with researchers working on topics like Capstone for trustless secure memory access and LABS for laser fault injection benchmarks.
Anuj Pathania serves as an Assistant Professor in the Parallel Computing Systems (PCS) group within the Informatics Institute at the University of Amsterdam's Faculty of Science. His research pioneers sustainable computing systems operating under severe power, thermal, and reliability constraints, with significant contributions to energy-efficient hardware design and embedded systems. Education: PhD in Computer Science (2018), Karlsruhe Institute of Technology MSc in Computer Science (2012), National University of Singapore B.Tech in Computer Science (2009), Maharaja Agrasen Institute of Technology Pathania's research centers on low-power design and sustainable systems for constrained environments, with particular expertise in thermal management of 3D-stacked architectures and energy-efficient machine learning inference . His work bridges electronic design automation with real-world reliability challenges, developing novel power budgeting techniques like T-TSP that incorporate transient temperature effects ignored by conventional methods. Current projects include EU-funded initiatives on energy labeling for digital services, addressing ecological impacts through technological, behavioral, and legal frameworks. His publication trajectory reveals a strategic evolution toward zero-waste computing , with recent work (2023-2025) focusing on hardware-software co-design for edge AI, energy modeling across computing continua, and parameter-efficient neural adaptation. Key themes include thermal-aware scheduling for S-NUCA many-cores, cooperative processor utilization in heterogeneous systems, and sustainability metrics for digital services. Scientific Recognition: Best Paper Award Nomination at IEEE Computer Society Annual Symposium on VLSI 2023 for 3D-TTP power budgeting technique Pathania actively mentors 4 PhD students (Ehsan Aghapour, Saeedeh Baneshi, Sudam Wasala, Yixian Shen) and has successfully supervised 5 Master's theses (including Cum Laude defenses by Joris op ten Berg and Jurre Wolff). His research is supported by major grants including Energy Labels for Ecologically Sustainable Digital Services (2023-2024) and Towards Zero-Waste Computing (2021-2025), developing simulation frameworks like HotSniper and CoMeT for thermal analysis. The PCS group maintains strong industry collaborations with ARM and NVIDIA, particularly through tools like ARM-CO-UP for heterogeneous processor utilization.
Jovan Stojkovic is an incoming Assistant Professor at the Department of Computer Science at the University of Texas at Austin, set to join in Fall 2026. Prior to his appointment at UT Austin, he will spend a year at Meta working with the AI and Systems Co-design group. His research focuses on cloud computing and datacenters, with particular emphasis on cloud-native workloads and machine learning inference. Education: PhD in Computer Science from the University of Illinois at Urbana-Champaign, advised by Professor Josep Torrellas Undergraduate studies at the School of Electrical Engineering, University of Belgrade, Serbia, where he was recognized as the best student of the Computer Engineering and Information Theory Department every year from 2017-2020 Research Interests: Jovan's research focuses on cloud computing and datacenters , with two primary domains: Cloud-native workloads , such as microservices and serverless computing. He investigates how to co-design novel hardware platforms and software systems that deliver orders-of-magnitude improvements in performance, energy efficiency, and resource utilization for these emerging workloads. Machine Learning (ML) inference , particularly large language models (LLMs). His work addresses the challenges of ML inference through smart scheduling, workload placement, and system-level configuration tuning to reduce energy, power, and thermal overheads while maintaining performance and accuracy guarantees. Publication Trends: Jovan's publications demonstrate a strong focus on optimizing cloud infrastructure for emerging workloads. His research spans across serverless computing, microservices, and large language model inference. A clear trend emerges in his work: addressing the performance, energy efficiency, and resource utilization challenges of modern cloud workloads through innovative hardware-software co-design approaches. His most recent work shows increasing focus on LLM inference optimization, particularly in the areas of thermal management, power efficiency, and scheduling for many-adapter environments. Awards and Honors: HPCA Best Paper Award (2025) IEEE MICRO Top Picks Honorable Mention (2024) 6 patents with IBM and Microsoft on: Serverless systems, Processor overclocking in the cloud, and Energy-efficient LLM inference W. J. Poppelbaum Memorial Award (2025) for hardware and architecture innovation Mavis Future Faculty Fellowship (2024–2025) Invited to present at 11th Heidelberg Laureate Forum (2024) Kenichi Miura Award (2022) for excellence in High Performance Computing Multiple student travel grants to ISCA, MICRO, ASPLOS, and HPCA Advising and Grants: Jovan is actively seeking prospective PhD students for his research group at UT Austin. His research has been supported through collaborations with major tech companies including IBM, Microsoft, and Meta. His six patents with IBM and Microsoft demonstrate the practical impact of his research in serverless systems, processor overclocking, and energy-efficient LLM inference. His work on serverless computing (MXFaaS, EcoFaaS) and LLM inference optimization has received significant recognition in top-tier computer architecture conferences. Research Groups: During his PhD at UIUC, Jovan worked with Professor Josep Torrellas on cloud infrastructure research. He has collaborated extensively with researchers at IBM Research (particularly Hubertus Franke) and Microsoft (particularly Íñigo Goiri and Ricardo Bianchini). His upcoming position at UT Austin will establish his independent research group focused on cloud computing and datacenter systems. His year at Meta working with the AI and Systems Co-design group will further strengthen his expertise in AI infrastructure.
James R. Green is a Professor in the Department of Systems and Computer Engineering at Carleton University , where he has been a faculty member since 2005. He holds a PhD from Queen's University and is a licensed Professional Engineer (P.Eng.) and Senior Member of IEEE. His work integrates machine learning, biomedical informatics, and high-performance computing. His educational background includes: B.A.Sc. in Systems Design Engineering, University of Waterloo (1998) M.Sc.(Eng.), Queen's University (2000) PhD, Queen's University (2005) Dr. Green's research focuses on machine learning challenges in biomedical informatics , particularly class imbalance and rare event prediction. Key areas include protein structure, function, and interaction prediction; microRNA detection in unique species; non-contact neonatal monitoring; and accelerating scientific computing via parallel architectures like the Cell BE processor. His lab has developed several widely used bioinformatics tools such as PIPE, ProtDCal, and PCI-SUMO. His recent publications reflect a strong trend in computational biology and machine learning , with applications in proteomics, genomics, and medical diagnostics. He has published over 100 peer-reviewed papers and secured funding from NSERC, CIHR, CFI, ORF, OCE, MITACS, and IBM. Scientific and teaching recognitions include: Three teaching awards NSERC Best Project Award (twice: 2006-2007 and 2007-2008) Multiple student projects resulting in conference papers (e.g., CMBEC) He has supervised numerous undergraduate capstone projects in areas such as assistive technologies, robotic systems, and bioinformatics. His teaching portfolio includes courses in Pattern Classification, Machine Learning, Computer Architecture, and Biomedical Engineering. He leads an active research group that bridges computer engineering and life sciences, fostering interdisciplinary collaboration. Lab and research team initiatives include: Development of open-access web servers for protein analysis Collaborations with biologists and clinicians Integration of hardware and software for medical applications
Rakesh Kumar is an Associate Professor in the Department of Computer Science (IDI) at the Norwegian University of Science and Technology (NTNU) , affiliated with the Computer Architecture Lab (CAL) within the Faculty of Information Technology and Electrical Engineering . Prior to joining NTNU, he held postdoctoral and research associate positions at Uppsala University and the University of Edinburgh, and interned at Intel Barcelona Research Center. Research Interests include improving large-scale datacenter efficiency through microarchitecture and memory system optimizations, hardware/software co-designed processors, dynamic code translation, vectorization, and serverless function execution. His work explores ready-aware instruction scheduling, branch prediction organization, and address translation mechanisms. Scientific Contributions span publications at top-tier conferences like MICRO (2024, 2023, 2018, 2016) HPCA (2020, 2019, 2023, 2022) ASPLOS (2018) DATE (2019, 2021) Journal articles appear in ACM Transactions on Computer Systems and IEEE Computer Architecture Letters . Awards include Intel Spontaneous Level II/Excellence Award (2014) Best Presentation Award at HiPC-SS08 (2008) Best Paper Award at National Conference on High Computing Technologies (2008) Distinguished Artifact Award at MICRO 2023 PhD Supervision involves advising students like Roman Kaspar Brunner, Elias Orrem, and Truls Asheim on topics spanning microarchitecture, vector units, and runahead execution policies.
Pejman Lotfi-Kamran is an Associate Professor at the School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran, where he also serves as the head of the school and director of Turin Cloud Services. His research focuses on computer architecture, systems, approximate computing, and cloud computing, with an emphasis on performance and energy efficiency for big-data applications. His educational background includes: Ph.D. in Computer Science, EPFL (2013) M.Sc. in Electrical and Computer Engineering, University of Tehran (2005) B.Sc. in Electrical and Computer Engineering, University of Tehran (2002) Lotfi-Kamran's research spans computer architecture innovations, including data and instruction prefetching, networks-on-chip, coherence protocols, and many-core processor design. He has pioneered work on scale-out processors, neural acceleration for GPUs, and approximate computing frameworks. His publications appear in top venues such as ISCA, HPCA, MICRO, and IEEE/ACM journals. His recent articles reflect a strong trend in improving system performance through intelligent prefetching, efficient NoC designs, and energy-aware architectures. Key themes include reducing frontend bottlenecks, optimizing cache behavior, and enhancing data delivery in large-scale systems. His work often combines cross-stack insights with hardware-software co-design for real-world impact. Scientific awards and recognitions include: 2017 CADS Best Paper Award 2016 Young Faculty Award from Iran's National Elites Foundation 2012-2013 Intel Ph.D. Fellowship 2012 and 2011 HiPEAC Paper Awards 2011 HPCA Best Student Paper Finalist Multiple academic honors from University of Tehran He has advised several graduate students including Paria Darbani, Ali Ansari, Mohammad Bakhshalipour, and Farid Samandi, many of whom have co-authored significant papers. His teaching spans institutions like Sharif University of Technology, Iran University of Science and Technology, and EPFL, covering advanced computer architecture and multiprocessor systems. He has led research projects such as AxBench and CloudSuite on Simics, and contributed to national initiatives like Iran’s National Grid. He is actively involved in tool development and continues to shape research in next-generation computing systems. He leads the Turin Cloud Services initiative at IPM and is deeply engaged in both theoretical and applied aspects of computer systems research, with ongoing work in neural acceleration, approximate computing, and scalable architectures.
Dr. Shengquan Wang is an Associate Professor in the Department of Computer and Information Science at the University of Michigan-Dearborn , affiliated with the College of Engineering and Computer Science . His career spans over a decade, with prior academic experience at Texas A&M University as a Research/Teaching Assistant. He received his Ph.D. in Computer Science from Texas A&M University in 2006, preceded by M.S. degrees in Mathematics (Texas A&M, 2000) and Applied Mathematics (Shanghai Jiao Tong University, 1998), and a B.S. in Mathematics (Anhui Normal University, 1995). Research Interests Real-Time Systems Sustainable Computing (Power/Energy/Thermal Management) Networks and Distributed Systems Security and Privacy Optimization and Machine Learning Publication Trends His work focuses on real-time systems under thermal constraints , secure overlay architectures , and energy-efficient server farms . Recent research explores statistical delay guarantees in wireless networks and nonmonotone optimization techniques . Collaborations span institutions like Texas A&M University and Karlsruhe Institute of Technology. Awards and Grants NSF CAREER Award (CNS 0746906) Rackham Faculty Research Grant Best Paper Award at ECRTS 2006 Advising and Leadership Dr. Wang advises Ph.D. and Master's students like Jun Liu and Nan Wang, fostering innovation in sustainable systems. He leads the Research Laboratory for Sustainable Systems (RLSS) , focusing on thermally constrained real-time systems and secure computing.
Alan J. Smith is a Professor in the Electrical Engineering and Computer Sciences department at the University of California, Berkeley, within the College of Engineering. With a distinguished career spanning several decades, he has made significant contributions to computer architecture, system performance analysis, and memory systems. Dr. Smith received his S. B. from MIT and a Ph.D. from Stanford University. His educational background provided the foundation for his extensive research in computer systems. Professor Smith's research focuses on computer architecture and engineering, particularly in system performance analysis, I/O systems, cache memories, and memory systems. His work has profoundly influenced how computer systems are designed and evaluated, with particular emphasis on optimizing storage systems, cache performance, and energy efficiency in computing platforms. His research has bridged theoretical analysis with practical implementation, resulting in numerous influential publications and real-world applications. His publication record shows a consistent focus on computer system performance, evolving from early work on cache memory and paging algorithms to more recent research on multimedia workloads, energy management, and storage systems. The breadth of his work spans fundamental computer architecture principles to applied system design, with particular emphasis on measurement-based analysis and optimization techniques. Harry Goode Award of the IEEE Computer Society (2006) IEEE Reynold B. Johnson Information Storage Systems Award (2008) A. A. Michelson Award of the Computer Measurement Group (2003) Fellow of the American Association for the Advancement of Science (2001) Fellow of the ACM (2000) Fellow of the IEEE (1988) Throughout his career, Professor Smith has actively contributed to the academic community through editorial roles, conference organization, and professional society leadership. He has served as Subject Area Editor for the Journal of Parallel and Distributed Computing since 1989, chaired ACM SIGARCH and SIGOPS, and participated in numerous technical committees. His research has been supported by various grants that enabled extensive experimental work and system development. Professor Smith has been instrumental in developing benchmarking methodologies and performance analysis techniques that have become standard practices in computer system evaluation. His work on cache memory systems, in particular his influential 1982 Computing Surveys paper "Cache Memories," has shaped the field for decades.
Johannes Geier is a Researcher at the Chair of Design Automation at the Technical University of Munich (TUM). His work focuses on electronic design automation, fault injection simulations, and security countermeasures for RISC-V processors. University: Technical University of Munich Department: Chair of Design Automation Email: johannes.geier@tum.de Research Interests Electronic Design Automation (EDA) for analog and digital circuits Fault tolerance and reliability in RISC-V architectures Security analysis of post-quantum cryptographic systems Timing analysis and microfabrication techniques Optical Networks-on-Chip (NoC) and emerging technologies Compiler-assisted hardware security implementations Recent Research Trends Specializes in fault injection methodologies for hardware security validation Develops open-source tools like vRTLmod for RTL simulation acceleration Explores RISC-V vector extensions for post-quantum cryptography Investigates differential fault effect equivalence checks for efficiency Designs compiler-based security countermeasures against instruction skip attacks Works on concurrent multi-node XCP proxy server architectures
