Find Academic Supervisors

Sagar KarandikarView profile

Assistant Professor

• Computer Architecture
• Hardware/Software Co-Design
• Hyperscale Cloud Data Centers
• +5 more

Sagar Karandikar is an Assistant Professor in the Electrical Engineering and Computer Sciences (EECS) department at UC Berkeley and the Jean and Hing Wong Foundation Faculty Fellow. He is also a Visiting Faculty Researcher at Google. His research focuses on hardware/software co-design for hyperscale cloud data centers powering critical applications including AI/ML, scalable data processing, and web services. His educational background includes: Ph.D. in Computer Science from UC Berkeley (2024) M.S. in Computer Science from UC Berkeley (2018) B.S. in Electrical Engineering and Computer Sciences from UC Berkeley (2015) Dr. Karandikar's research spans hardware accelerator and server system-on-chip design, full-stack system optimization, and agile, open-source hardware development methodologies. His work addresses system-level inefficiencies in warehouse-scale computers through data-driven hardware/software co-design. His group is part of the SpeciaLIzed Computing Ecosystems (SLICE) Lab at Berkeley. His publications reveal a consistent focus on improving hyperscale datacenter performance through hardware acceleration and system optimization. Key themes include FPGA-accelerated simulation (FireSim), hardware accelerators for specific workloads (like protocol buffers and compression), and open-source frameworks for agile hardware development (Chipyard). His work bridges the gap between theoretical architecture research and practical deployment in large-scale datacenters. Dr. Karandikar has received numerous prestigious awards for his research: 2025 ACM SIGARCH/IEEE CS TCCA Outstanding Dissertation Award ISCA@50 25-year Retrospective selection IEEE Micro Top Picks selection and honorable mention MICRO and ISCA Distinguished Artifact Awards David J. Sakrison Memorial Prize for outstanding graduate research UC Berkeley Outstanding Graduate Student Instructor Award DARPA Riser selection Dr. Karandikar actively mentors students and leads research projects including FireSim (used in over 70 peer-reviewed publications from institutions worldwide), Hyperscale SoC, and Chipyard. His work has been adopted by both academic institutions and industry for developing commercially available chips and as standard platforms for DARPA/IARPA programs. He is accepting new students for his research group. His research group is part of the SpeciaLIzed Computing Ecosystems (SLICE) Lab at Berkeley, focusing on hardware/software co-design for hyperscale cloud systems. The group develops frameworks like FireSim for FPGA-accelerated cycle-accurate simulation and Chipyard for agile RISC-V SoC design, enabling rapid prototyping and evaluation of specialized computing systems.

• Secure Systems
• Operating Systems
• Distributed Systems
• +5 more

Nickolai Zeldovich is the Joan and Irwin M. (1957) Jacobs Professor of Electrical Engineering and Computer Science at MIT and a member of the Computer Science and Artificial Intelligence Laboratory (CSAIL). His research focuses on building practical secure systems through the integration of formal methods with real-world system design. His research interests span secure systems, operating systems, distributed systems, formal verification, and cryptography. Recent work emphasizes automated reasoning for distributed system liveness, leakage-free hardware security modules, and privacy-preserving web technologies. Projects include CryptDB (encrypted databases), FSCQ (verified file systems), Algorand (cryptocurrency), and Vuvuzela (private messaging). His publication trends show consistent output in formal verification of distributed systems (Shipwright, Grove), hardware security (K2 Architecture), and privacy technologies (Tiptoe). Recent work increasingly combines theoretical verification with practical implementation constraints. Best Paper Awards at ACM SOSP (2013, 2015, 2017) Sloan Research Fellowship (2010) NSF CAREER Award (2011) MIT EECS Jamieson Award for Excellence in Teaching (2024) ACM SIGOPS Mark Weiser Award (2017) Amazon Research Award (2023) He advises PhD students through the PDOS research group with active grants from Amazon, Google, NSF, and DARPA. His teaching includes core courses like Computer Systems Security and Operating System Engineering, emphasizing hands-on security analysis. The PDOS lab maintains strong industry connections with multiple startup spin-offs and regular technology transfer to production systems. He leads the PDOS (Parallel and Distributed Operating Systems) Research Group, which focuses on building verified, secure, and high-performance systems through close collaboration between theory and practice.

• Embedded Systems
• Computer Architecture
• Internet of Things (IoT)
• +7 more

David Atienza is a Professor of Electrical and Computer Engineering at the Swiss Federal Institute of Technology Lausanne (EPFL), serving as Head of the Embedded Systems Laboratory (ESL) and Scientific Director of the EcoCloud Sustainable Computing Center. His academic credentials include: MSc in Computer Science and Engineering, Complutense University of Madrid (UCM), Spain (2001) Ph.D. in Computer Science and Engineering, Complutense University of Madrid (UCM), Spain, and IMEC, Belgium (2005) His research focuses on system-level design methodologies for high-performance multi-processor system-on-chip (MPSoC) and low-power Internet-of-Things (IoT) systems. Key specialties include 2-D/3-D thermal-aware design for MPSoCs and many-core servers, ultra-low power edge AI architectures for wireless body sensor nodes, HW/SW reconfigurable systems , dynamic memory optimizations, and network-on-chip design. This work drives innovations in sustainable computing and energy-efficient embedded systems. Dr. Atienza's accolades feature: ACM/IEEE ICCAD 10-Year Retrospective Most Influential Paper Award (2020) ACM/IEEE DAC Under-40 Innovators Award (2018) ERC Consolidator Grant for liquid-cooling 3D computing systems (2016) IEEE CEDA Early Career Award (2013) ACM SIGDA Outstanding New Faculty Award (2012) Sun Labs at Oracle Faculty Award (2011) He directs significant research initiatives including an ERC Consolidator Grant and mentors students through the Embedded Systems Laboratory. His leadership extends to editorial roles in premier journals and conference organization. Dr. Atienza heads the ESL and EcoCloud Center, driving collaborative research in sustainable computing, thermal-aware architectures, and edge AI with global industry partners to advance energy-efficient technologies.

William A. MasseyView profile

Professor

• Dynamical Queueing Systems
• Dynamic Optimization
• Operations of Communication Systems and Services
• +3 more

William A. Massey is a Professor in the Department of Operations Research and Financial Engineering at Princeton University's School of Engineering and Applied Science. His research focuses on dynamical queueing systems, stochastic networks, and dynamic optimization for telecommunications and service systems. Research Interests: Dynamical Queueing Systems, Dynamic Optimization, Stochastic Orders, CAARMS Conference leadership Email: wmassey@princeton.edu Contact: Phone: 609-258-7384 | Fax: 609-258-3791 Location: Princeton, NJ 08544 His recent work examines fluid/diffusion approximations for transient queueing systems, time-varying call center design, dynamic pricing models, and bandwidth provisioning in telecommunications. Publications span top journals like Management Science , Operations Research , and Queueing Systems . As founder of the Conference for African-American Researchers in the Mathematical Sciences (CAARMS), he actively promotes diversity in STEM through academic leadership and mentoring initiatives.

Jason MarsView profile

Professor

• Computer Architecture
• Warehouse-Scale Computing
• Machine Learning Systems
• +3 more

Jason Mars is a Professor at the University of Michigan's Department of Electrical Engineering and Computer Science, leading the Clarity-Lab. His research focuses on cross-layer architectures and runtimes for future computing systems, particularly in warehouse-scale computers. He has pioneered projects like Sirius (an open voice/vision personal assistant), Protean Code (dynamic code transformations), and Adrenaline (tail latency management). His work addresses challenges in energy efficiency, resource allocation, and performance optimization in large-scale systems. Key contributions include architectural designs for AI services, thermal management strategies, and compiler techniques for approximate computing. Mars collaborates with industry leaders like IBM and has advised numerous students who have published at top conferences such as ASPLOS and HPCA. Recent research spans AI ethics, scalable programming models (e.g., Data Spatial Programming), and edge-cloud collaboration frameworks like Neurosurgeon. He has delivered invited talks at Baidu, IBM Watson, and conferences worldwide, emphasizing the societal impact of computing systems.

Bruce LesterView profile

Professor

• Parallel Computing
• Programming Languages
• Multi-Core Processors
• +3 more

Dr. Bruce Lester is a Professor of Computer Science at Maharishi University of Management (MUM), where he founded the Computer Science Department and served as its Chair for eight years. He holds PhD, MS, and BS degrees from the Massachusetts Institute of Technology (MIT). His research focuses on Parallel Computing and Programming Languages for Multi-Core Processors, with a strong emphasis on compiler optimization and concurrency control. Education: Bachelor of Science, Massachusetts Institute of Technology Master of Science, Massachusetts Institute of Technology Doctor of Philosophy (PhD), Massachusetts Institute of Technology Research Interests: Dr. Lester’s work spans Parallel Computing, Programming Languages, and Multi-Core Processor Optimization. He has developed techniques for lock-free parallel data structures, operator fusion in data-parallel libraries, and compile-time detection of control flow errors in parallel programs. His contributions to the field include foundational research on concurrency debugging and the design of educational tools like Multi-Pascal for teaching parallel programming. Publications Trends: His publications emphasize practical applications of parallel computing, including high-performance algorithms, compiler techniques, and concurrency error detection. Recent work focuses on lock-free systems and data-parallel library optimizations. Awards & Honors: Best Paper Award at the 2011 International Conference of Parallel and Distributed Computing (World Congress on Engineering) Advising & Grants: No formal advisee names are listed in the provided data. His professional experience includes 13 years of teaching and six years as a Senior Software Engineer at Primus Telecommunications, where he developed client/server systems and internet platforms. Labs & Teams: While specific lab affiliations are not detailed, his role as founder of MUM’s Computer Science Department suggests leadership in departmental research initiatives.

• Embedded Systems
• IoT Security
• Digital System Design
• +3 more

Paulino Ruiz de Clavijo Vázquez is a Professor in the Department of Electronic Technology at the University of Seville. His primary research focuses on embedded systems, IoT security, digital system design, FPGA implementation, and hardware security. He leads and collaborates on numerous research projects, including advanced IoT boot systems, secure embedded communication, and high-precision timing synchronization for IoT devices. Key projects include the IRIS secure boot framework for IoT and the E-LUKS hardware encryption solution. His work spans both theoretical contributions (e.g., novel trigonometric computation algorithms) and applied hardware-software co-design (e.g., NanoFS file system). He has advised doctoral theses such as 'LILA: Low-level IoT Lightweight Applications.' His research also involves FPGA-based systems for real-time applications, including time servers and FFT modules. Projects like HAVOC (hardware audio codec) and HardTIME (high-precision timing) highlight his focus on practical hardware implementations. He has contributed to over 50 peer-reviewed publications, conference presentations, and patents related to embedded systems, digital circuit design, and IoT security solutions.

• Microelectronics
• Embedded Systems
• IoT Security
• +5 more

David Guerrero Martos is an Associate Professor in the Department of Electronic Technology at the University of Seville. His primary research focuses on microelectronics, embedded systems, and hardware security solutions. He leads the 'Digital Research and Development' group and has participated in numerous national and international grants, including the 'USECHIP: Chair in Microelectronics' project (TSI-069100-2023-001) and the 'Easy-to-deploy intelligent network for independent living for our seniors (RIING)' initiative (IPT-2012-0645-300000). His academic contributions include pioneering work on FPGA-based IoT security (e.g., E-LUKS), high-precision timing systems, and low-power digital circuit design. He has published extensively in journals like IEEE Access and Electronics , and his research spans topics such as trigonometric function computation, hardware bootloaders (NanoBoot), and SoC integration frameworks (evercodeML). Guerrero Martos has over 20 years of experience in both academic and applied research, with notable contributions to teaching methodologies in electronics. He holds patents for innovative digital circuits and has collaborated on open-source hardware projects, emphasizing practical applications of embedded systems.

Zomaya AlbertView profile

Academic

• Complex systems
• Parallel and distributed computing
• Sustainable computing
• +7 more

Dr. Zomaya is the Chair Professor of High Performance Computing & Networking and Founding Director of the Centre for Distributed & High Performance Computing at the University of Sydney, Australia. He has held leadership roles including Deputy Head of School and Head of School at The University of Western Australia and the University of Sydney. A Fellow of AAAS, IEEE, and IET, he leads research in distributed computing systems, sustainable computing, and edge intelligence. His research spans parallel/distributed computing, energy-efficient systems, and cloud/edge technologies. He has published over 600 papers, authored/edited 20+ books, and secured $22M+ in funding from ARC, Cisco, IBM, and others. He currently supervises 12 PhD students and has mentored 35 PhD completions. Key awards include the ACM MSWIM 2017 Fessenden Award and IEEE Technical Achievement Award (2014). He serves as Editor-in-Chief of IEEE Transactions on Sustainable Computing and has chaired over 700 conferences. His current projects focus on data analytics over cloud/edge platforms and holistic energy-aware scheduling for distributed systems.

• Telecommunications Engineering
• Electromagnetic Field Theory
• Wireless Sensor Networks
• +3 more

Dr. Jarosław Emilianowicz holds a PhD in Electrical Engineering and serves as a researcher at the Department of Telecommunications and Teleinformatics within Wrocław University of Science and Technology's Faculty of Information and Communication Technology. Doctoral degree in Electrical Engineering Specializes in electromagnetic field applications and wireless communication systems Active in LPWAN technologies and IoT implementations His research spans electromagnetic field shaping, wireless sensor networks, and real-time location systems. Recent work focuses on LoRaWAN-based environmental monitoring in large buildings, demonstrating practical IoT applications for smart infrastructure. Publications show expertise in microwave techniques, WLAN security analysis, and embedded communication systems. Key technical interests include signal processing algorithms, secure wireless transmission mechanisms, and microprocessor-based measurement devices. Active in conference proceedings and book chapters related to telecommunications applications, with contributions appearing in IEEE publications and Polish technical monographs.

• Artificial Intelligence
• Network Administration
• Multi-agent Systems
• +6 more

Horia Popa is a Lecturer at the Faculty of Computer Science , West University of Timișoara. He has taught courses such as Artificial Intelligence , Network Administration , and Functional and Logic Programming since the 2022-2023 academic year, with additional historical courses dating back to 2011-2012. His teaching emphasizes hands-on lab work, software tools (Jess, CLIPS, WEKA), and project-based learning. Education: Not explicitly mentioned in the text. Research: Focuses on multi-agent systems, distributed constraints, asynchronous search algorithms, and system administration. Research Interests: Horia Popa specializes in Artificial Intelligence and Multi-agent Systems , particularly in asynchronous search techniques and constraint satisfaction problems. His work explores scale-free networks, nogood processors, and distributed execution environments. He also investigates Network Administration (DHCP, firewall configuration, kernel recompilation) and Knowledge Discovery through agent-based modeling. Article Trends: His publications (2001-2015) span Computer Science , Artificial Intelligence , and Multi-agent Systems . Key subfields include Asynchronous Algorithms , Constraint Networks , Protein Folding Simulation , and Kernel-Level System Management . He frequently uses NetLogo for large-scale simulations and integrates Samba/ldap for networked environments. Teaching and Projects: Students in his courses work on projects involving Jess , Prolog , and JADE . Assignments include implementing search algorithms (A*, Hill Climbing, RBFS), configuring NIS and Samba servers, and analyzing system monitoring tools like sar and top . He emphasizes practical implementation and cross-language diversity (e.g., Racket, Prolog).

• Model-Based Design Methods
• Design Automation
• Optimization
• +5 more

Marc Geilen is an Associate Professor at the Electronic Systems group of Eindhoven University of Technology (TU/e) . He leads the Model-Based Design Lab within the CompSOC Lab and High Tech Systems Center .

• Computer Architecture
• Parallel Computing
• Multicore Processors
• +3 more

Oyekunle Olukotun is a Professor at Stanford University, internationally recognized for transformative contributions to computer architecture and parallel systems. His pioneering work established foundational principles for modern processor design that bridge academic research and industrial implementation. His research centers on parallel computing systems with emphasis on multicore and multithreaded processor architectures. Key innovations include chip multiprocessor (CMP) technology that became the industry standard for modern CPUs, fine-grained multithreading techniques for CPU efficiency optimization, and the Transactional Coherence and Consistency (TCC) framework for simplifying parallel programming. These contributions address critical challenges in performance scaling and energy efficiency for contemporary computing systems. Olukotun's publications reveal a consistent focus on hardware-software co-design for parallel systems, with significant impact across computer architecture and high-performance computing domains. His work demonstrates evolutionary progression from theoretical frameworks to industry adoption, particularly in server processor design. Scientific awards include: ACM-IEEE CS Eckert-Mauchly Award (2023) for contributions to parallel systems development ACM Fellow (2006) for multiprocessor and multithreaded processor design ASPLOS Most Influential Paper Award (2011) for the 1996 landmark paper ISCA Most Influential Paper Award (2019) for the 2004 transactional memory paper While the provided text lacks specific details about student advising or grant funding, Olukotun's entrepreneurial impact is evident through Afara WebSystems, which advanced server technology prior to its acquisition by Sun Microsystems. His research directly enabled Oracle's Niagara chip family used in SPARC-based servers. Industrial collaboration represents a critical dimension of his work, with designs transitioning from academic concepts to commercial implementations that shaped server processor evolution. The TCC framework co-developed with Christos Kozyrakis remains influential in parallel programming research.

Jie LuView profile

Associate Professor

• Software Security
• Program Analysis
• Vulnerability Detection
• +5 more

Jie Lu is an Associate Professor at the Institute of Computing Technology of the Chinese Academy of Sciences (ICT, CAS), where he leads research in software security and program analysis. His work focuses on developing advanced program analysis techniques to improve software reliability and security, with applications in cloud systems, distributed environments, and modern web applications. Dr. Lu's research interests include: Software Security: Focusing on vulnerability detection and prevention in open-source software Program Analysis: Specializing in static/dynamic analysis techniques and context-sensitive pointer analysis Cloud Systems: Researching distributed system security, crash-recovery, and concurrency bug detection His recent publications demonstrate a strong focus on practical security solutions for real-world systems. The research spans Kubernetes ecosystems, PHP applications, Linux kernel security, Java web applications, and Windows IPC systems. A notable trend is the development of precise static analysis techniques that balance efficiency with accuracy, addressing the longstanding challenge in program analysis. His work often bridges theoretical advances with practical implementations that have been adopted by industry. Dr. Lu has received several prestigious awards: ACM SIGSOFT Distinguished Paper Award 2025 Best Paper Honorable Mention at CCS 2022 Chinese Academy of Sciences Outstanding Doctoral Dissertation 2021 Chinese Academy of Sciences President's Special Award 2020 ICT New Hundred Stars 2020 Dr. Lu actively mentors students and researchers, recruiting PhD candidates, Master students, and research interns interested in software security and program analysis. His research has been supported by the National Natural Science Foundation of China, CCF-Huawei Innovation Research Plan, and CCF-Ant Research Fund. The Program Analysis Group (ICT-PAG) at the National Key Laboratory of Processor has successfully identified numerous errors and vulnerabilities in popular open-source applications, with over 200 severe bugs confirmed by the open-source community and assigned more than 100 CVE numbers. His research group, the Program Analysis Group (ICT-PAG), is based in the National Key Laboratory of Processor at ICT, CAS. The group has achieved significant impact through both academic publications in top venues (SOSP, CCS, USENIX Security, NDSS, OOPSLA, ISSTA, FSE, ASE, TSE) and practical applications in leading IT companies and government organizations.