Saeid Moslehpour is Chair and Associate Professor in the Department of Electrical and Computer Engineering at the University of Hartford's College of Engineering, Technology, and Architecture. He holds a Ph.D. in Industrial Technology and Computer Engineering (1993) from Iowa State University, along with multiple degrees from the University of Central Missouri including an Ed.Sp in Industrial Technology. Ph.D., Industrial Technology and Computer Engineering - Iowa State University (1993) Ed.Sp, Industrial Technology - University of Central Missouri MS, Electronics - University of Central Missouri BS, Electronics - University of Central Missouri His research focuses on Soft Processors , Electronic Modeling , and Cyber Learning , with expertise in SPICE modeling, FPGA/VHDL/Verilog programming, microprocessor design, telecommunications, and digital signal processing. He has pioneered laboratory developments including wireless, telecommunications, and surface roughness analysis systems. Recent work includes publications on EEG signal analysis , space systems hazard analysis , and embedded electronics . He received academic honors from Phi Kappa Phi and Epsilon Pi societies and maintains certifications in telecommunications and Cisco networking systems. Phi Kappa Phi Academic Honor Society (1993) Epsilon Pi Industrial Technology Honor Society (1993) Excellent Student Scholarship (1992-94) As an ASEE editor and committee chair, he has shaped engineering education policy and assessment. His industry collaborations with Northern Net Technology and Pars Server Tehran demonstrate practical applications of his work.
Ricardo Fernández Pascual is an Associate Professor at the Computer Engineering Department (DITEC) of the Universidad de Murcia , Spain. He teaches introductory and advanced computer architecture courses like ' Estructura y Tecnología de Computadores ' and ' Organización y Arquitectura de Computadores '. His academic work focuses on computer architecture , particularly in memory hierarchies for chip multiprocessors cache coherence protocols fault tolerance energy-efficient design His PhD thesis (2009) at the Universidad de Murcia, titled ' Fault-tolerant Cache Coherence Protocols for CMPs ', was supervised by José Manuel García Carrasco and Manuel Eugenio Acacio Sánchez. He has also collaborated with institutions like Intel Barcelona Research Center and FORTH. Recent research trends in his publications include optimizing coherence directories for manycore scalability hybrid photonic-electronic interconnects fault-tolerant mechanisms in CMP architectures transactional memory enhancements dynamic resource management private-shared cache organization He has advised PhD student Antonio García Guirado, who completed his thesis on energy-efficient cache-coherent multi-cores in 2013. His work has been published in leading journals like IEEE Transactions on Parallel and Distributed Systems, Journal of Parallel Distributed Computing, and conferences including ICS, HPCA, and SBAC-PAD.
Marios Papaefthymiou is a Professor of Computer Science and Ted and Janice Smith Family Foundation Dean of the Donald Bren School of Information and Computer Sciences at the University of California, Irvine. Previously, he held faculty roles at the University of Michigan (including Computer Science & Engineering Division Chair) and Yale University. His research focuses on energy-efficient computing, charge-recovery technologies, and high-performance systems. Education: Ph.D., Electrical Engineering and Computer Science, MIT (1993) S.M., Electrical Engineering and Computer Science, MIT (1990) B.S., Electrical Engineering, Caltech (1988) Research Interests: Papaefthymiou pioneered charge-recovery (adiabatic) technologies, demonstrating energy-efficient silicon prototypes. His work spans energy-efficient design, high-performance computing, and electronic design automation. He co-founded Cyclos Semiconductor to commercialize these innovations, used in AMD/IBM server chips. Current interests include AI ethics, cybersecurity, and machine learning. Awards: Arthur Greer Memorial Prize (Yale) Outstanding Achievement Award (U. Michigan EECS) IEEE Fellow (2009) NSF CAREER/ITR Awards Advising & Grants: Advised numerous students (e.g., H.-S. Wu, Z. Zhang) and secured grants from NSF, ARO, DARPA, and industry partners. As Dean, he expanded the School’s fundraising to $10M annually, launched new programs, and founded centers like the HPI Research Center for Machine Learning. Leadership: Spearheaded initiatives like the Steckler Center for Responsible Technology and the Initiative on AI, Law & Society. Strengthened alumni engagement through events and the ICS Industry Showcase.
Prof. Dr.-Ing. Bernhard Lang is a Professor at the Faculty of Engineering and Computer Science (IuI) at Osnabrück University of Applied Sciences. His research focuses on digital multimedia systems and microprocessor technology, with expertise in FPGA-based systems and RISC-V architectures. He leads the Laboratory for Digital and Microprocessor Technology, where he develops hardware GDB-Server solutions for embedded systems. His work includes projects such as a GDB-Server implementation for VexRiscv processors and fine-grained multithreading designs. He actively contributes to open-source projects, including hardware-software co-design frameworks for FPGAs. Prof. Lang teaches courses in digital systems and advises students on final theses in related fields. His research infrastructure includes the Basys3 FPGA board, with synthesized designs available for practical implementation.
Dalibor Radovanović is an academic affiliated with Singidunum University, where he holds the position of Professor. His academic journey includes a doctoral dissertation from Singidunum University (2016) and postgraduate studies at the Faculty of Business Informatics. He has contributed extensively to cybersecurity, blockchain, IoT, and IT governance research. His research focuses on cybersecurity challenges in IoT and blockchain applications, smart card security, and e-business safety. He has authored/co-authored over 50 publications including books on Internet marketing and technical journals. Notable works include analysis of blockchain in healthcare IoT (2022), IoT security in industrial markets (2022), and evolutionary algorithms for environmental performance (2019). Radovanović's work spans academic conferences such as Sinteza, FINIZ, and IEEE events. His contributions address both theoretical and practical aspects of IT security, digital transformation in Serbian businesses, and data protection mechanisms. He has advised on virtualization bottlenecks, penetration testing for wireless networks, and cryptographic tool development for education. He has collaborated with institutions like the European Journal of Applied Economics and contributed to projects analyzing Serbia's investment advantages (2015) and mobile banking impact (2016). His research often bridges technical innovation with real-world business applications.
Jan Piotr Chudzikiewicz is an Assistant Professor at the Faculty of Cybernetics of Warsaw University of Technology. His research focuses on cybersecurity, military IoT systems, wireless sensor networks (WSN), and fault tolerance mechanisms. He has extensively collaborated on projects involving trusted platform modules (TPM) for securing communication, hypercube network architectures, and reliability engineering in embedded systems. Key contributions include developing authentication protocols for WSNs, optimizing resource placement in fault-tolerant networks, and integrating security frameworks into military IoT infrastructure. His work often combines theoretical analysis with simulation-based validation, addressing challenges in both civilian and defense-oriented network systems. Notable publications span topics such as secured sensor domains, hypercube network reconfiguration, and reliability solutions for MIoT. His interdisciplinary approach bridges computer science, electrical engineering, and cybersecurity to address real-world operational challenges.
Luca Abeni is an Associate Professor at the ReTiS Lab (Real-Time Systems) of Scuola Superiore S. Anna , Pisa. He graduated in Computer Engineering from the University of Pisa in 1998 and earned his PhD at Scuola Superiore S. Anna (1999-2002), focusing on real-time operating systems, scheduling algorithms, and QoS management. His career includes a visiting researcher role at Carnegie Mellon University (2000) and Oregon Graduate Institute (2001), followed by a full-time researcher position at the University of Trento's DISI department (2006-2017). Research Interests include real-time systems, cloud computing, virtualization, containerization (e.g., RT-Kubernetes), Linux kernel optimization, fault tolerance, and scheduling algorithms. His work addresses temporal isolation in cloud/edge environments, energy-efficient real-time computing, and adaptive resource management. Scientific Awards 2021 RTSS Influential Paper Award for 1998 paper on real-time scheduling Notable Contributions involve Xen/KVM latency analysis, deadline-based scheduling, ARM big.LITTLE partitioning, and kernel bypass mechanisms. He developed tools like PROSIT for probabilistic real-time analysis and artifacts for reproducing experiments.
Ulas Yaman is an Assistant Professor in the Department of Mechanical Engineering at Middle East Technical University (ODTÜ), Ankara, Turkey. He holds a PhD (2014), MSc (2010), and BSc (2007) in Mechanical Engineering from ODTÜ, with a minor in Mechatronics. His academic career includes a Visiting Assistant Professor role at Purdue University (2014-2015) and Research Assistant positions at ODTÜ (2007-2014). Education: PhD, Mechanical Engineering, ODTÜ (2007-2014) MSc, Mechanical Engineering, ODTÜ (2007-2010) BSc, Mechanical Engineering, ODTÜ (2003-2007) Minor in Mechatronics, ODTÜ (2004-2007) Professor Yaman's research focuses on 3D Printing, Additive Manufacturing, CAD/CAM architectures, FPGA-based embedded systems, and computational geometry for manufacturing . His work addresses challenges in dimensional accuracy, interior structure optimization, and command generation paradigms for CNC and 3D printing systems. He developed the LIPRO pipeline, leveraging Python-based scripting and List Processors to reduce G-code file sizes by up to 99.7% in FDM applications. Scientific Contributions: Fundamental advancements in 2.5D curve offset generation using mathematical morphology Innovative shrinkage compensation techniques for FDM 3D printing Hybrid manufacturing systems integrating additive and subtractive processes Query-based CAD/CAM architectures for heterogeneous printing Real-time interpolator implementations on FPGA hardware Awards & Grants: Best Paper Award, IEEE Workshop on Intelligent Solutions in Embedded Systems (2016) TÜBİTAK 1001 Project Grant (2017-2020) for Hybrid Manufacturing Systems TÜBİTAK 3001 Grant (2017-2018) for LIPRO Pipeline Development ODTÜ-BAP Grant (2016) for Dimensional Accuracy Improvement TÜBİTAK PhD Scholarship (2010-2014) As an educator, he has taught advanced courses including ME 533 - Computer-Aided Design and ME 414 - System Dynamics at ODTÜ since 2015. His laboratory leads projects on smart manufacturing systems and develops open-architecture platforms for experimental validation of novel fabrication paradigms.
Tanvir Ahmed Khan is an Assistant Professor at Columbia University, specializing in computer architecture and systems. His research focuses on enabling efficient data center processing through hardware-software co-design, particularly in instruction and data caching, branch prediction, and profile-guided optimizations. His work has been adopted by industry leaders like Intel and ARM, and recognized with awards such as the MICRO 2022 Best Paper Award and the ACM SIGARCH/IEEE CS TCCA Outstanding Dissertation Award. He holds a PhD from the University of Michigan, where he previously conducted research on techniques like I-SPY, DMon, and Ripple. His current projects aim to address bottlenecks in data center applications by leveraging repetitive execution patterns for predictive optimizations. Khan has mentored numerous students, including Kan Zhu (first place in MICRO 2022 SRC) and Yuxuan Zhang (first author of OCOLOS). His service roles include program committee memberships for ISCA, MICRO, and CGO, reflecting his influence in the field. Key achievements include the Rackham Predoctoral Fellowship, Qualcomm Innovation Fellowship finalist status, and multiple SRC Best Paper awards.
Mohammad Alian is an Assistant Professor at the School of Electrical and Computer Engineering, Cornell University. He earned his Ph.D. (2020) and MS (2015) from UIUC and UW-Madison, respectively. His research focuses on redefining data-delivery hierarchies in data centers through computer architecture and systems research. Current Projects: Near-Memory Acceleration, Accelerator Fusion, Micro-Service Co-Design, Compound AI Systems, Memory Specialization, Gem5 Simulation Tools. Recent Awards: MICRO Hall of Fame (2025), NSF CAREER (2022), Miller Faculty Scholar (2023), Open Innovation Contest placements. His research spans Computer Architecture , Memory Systems , and Networked Computation , emphasizing algorithm-hardware co-design for distributed and heterogeneous computing. Recent work includes accelerating large-context LLMs (LongSight), optimizing gem5 simulation (Userspace Networking), and designing cross-accelerator chains (Data Motion Acceleration). ARG (Alian Research Group) collaborates with industry leaders like NVIDIA, Samsung, and SRC/DARPA JUMP 2.0 ACE Center. He serves on PC/Organizing Committees for top conferences (MICRO, ISCA, HPCA) and teaches Data Center Architecture (ECE 6960) and Digital Logic (ECE 2300) . Scientific Awards Inducted into MICRO Hall of Fame (2025) NSF CAREER Award (2022) IEEE Micro Top Picks Honorable Mention (2017) Best Paper Nominee - HPCA 2017, MICRO 2018 Open Innovation Contest: 2nd Place (2022), Finalist (2021) As Principal Investigator, he leads NSF-funded projects (CCRI, AI-Assisted Scaffolding) and co-leads the $31.5M SRC/DARPA JUMP 2.0 ACE Center . His lab develops open-source tools like dist-gem5 and DPDK on gem5, with industry support from NVIDIA (equipment donation) and Samsung.
Edouard Bugnion is a Professor at École Polytechnique Fédérale de Lausanne (EPFL), where he joined in 2012. His research focuses on datacenter systems through the Data Center Systems Lab (DCSL). Professor Bugnion's research interests span Operating Systems , Datacenter Infrastructure , Systems Networking , and Computer Architecture . His work aims to combine low latency, high throughput, and efficiency in protected dataplane systems, with a particular focus on virtualized datacenters and operating system design. His publication record shows a consistent focus on operating systems and virtualization technologies, with significant contributions spanning from the late 1990s to the present. His work demonstrates a progression from foundational virtualization research to practical datacenter systems engineering, particularly in optimizing networking performance while maintaining kernel protection benefits. Professor Bugnion's scientific achievements have been recognized with several prestigious awards: ACM Software System Award for VMware 1.0 (2009) Best Paper Award at SOSP '97 for "Disco: Running Commodity Operating Systems on Scalable Multiprocessors" ACM SIGOPS Hall of Fame Award (2008) OSDI 2014 Best Paper Award for work on the IX dataplane operating system Before joining EPFL, Professor Bugnion co-founded two successful startups: VMware and Nuova Systems (acquired by Cisco). At VMware (1998-2005), he served in various roles including CTO. At Nuova/Cisco (2005-2011), he helped build the core engineering team and became VP/CTO of Cisco's Server, Access, and Virtualization Technology Group, which developed Cisco's Unified Computing System (UCS) platform for virtualized datacenters. Professor Bugnion leads research in the Data Center Systems Lab (DCSL) at EPFL, which focuses on next-generation datacenter technologies. His lab maintains a strong collaboration with Stanford University, as evidenced by the joint development of the IX Operating System, demonstrating his continued engagement with top academic institutions and industry partners in advancing datacenter infrastructure.
Boris Grot is a Professor holding the Personal Chair of Computer Systems and Architecture in the School of Informatics at the University of Edinburgh, where he leads research on optimizing large-scale datacenter efficiency through hardware-level innovations in server architectures, memory systems, and interconnect networks. His academic background includes a PhD in Computer Science from The University of Texas at Austin (thesis: scalability and quality-of-service in on-chip networks) followed by post-doctoral research at EPFL's Parallel Systems Architecture Lab. Research focuses on critical infrastructure challenges driven by three converging factors: mobile/embedded system constraints (battery, thermal, form factor), massive-data applications (search, social networking), and enterprise cloud migration. Key problem domains include: Re-inventing server architectures for specialized datacenter workloads Overcoming semiconductor voltage scaling limitations Addressing the 1.3% global energy footprint of datacenters (growing rapidly) Designing football-field-scale facilities handling 5-20 MW power loads He directs the EASE Lab investigating these challenges, emphasizing the economic and environmental urgency as datacenter deployment accelerates worldwide. No scientific awards or student advisees were specified in the source material, and grant details remain undocumented in the provided text.
Daniel Lemire is a full professor of computer science at the Université du Québec (TELUQ), recognized as one of the top 2% most cited scientists globally according to Stanford University's 2024 rankings. He ranks among the 0.0006% most followed programmers on GitHub, with his work adopted by major technology companies including Google, Facebook, Intel, and Shopify. Education: Ph.D. in Engineering Mathematics (University of Montreal and Polytechnique Montréal), Master's in Mathematics (University of Toronto), Bachelor's in Mathematics with High Distinction (University of Toronto) Current Role: Editor of Software: Practice and Experience journal since 2020 Professional Recognition: Co-chair of NSERC's Computer Science Discovery Grants Committee (2020-2021) Professor Lemire's research focuses on software performance optimization and data indexing techniques. His work bridges theoretical computer science with practical applications, particularly in areas where performance bottlenecks exist in real-world systems. He specializes in leveraging hardware capabilities through vectorization (SIMD instructions) to dramatically improve processing speeds for fundamental operations that have remained inefficient for decades. His approach combines deep theoretical understanding with practical implementation, resulting in algorithms that are both mathematically sound and immediately applicable in production systems. Lemire's research portfolio demonstrates a consistent pattern of identifying critical performance bottlenecks in widely used software operations and developing innovative solutions that achieve order-of-magnitude improvements. His work spans multiple domains including JSON parsing, Unicode string processing, URL parsing, base64 encoding, and bitmap indexing. A common thread through his publications is the application of hardware-specific optimizations, particularly SIMD instructions, to accelerate operations that were previously considered near-optimal. His research has evolved from foundational algorithm development to influencing major software ecosystems, with his libraries becoming integral components of industry-standard tools. Among the 2% most cited scientists globally (Stanford University, 2024) Université du Québec's Prix d'excellence 2020 for research success Most read articles at Software: Practice and Experience (2024, 2025) Best voted talk at QCon San Francisco 2019 Editor of Software: Practice and Experience journal since 2020 Numerous citations in patents held by Microsoft, LinkedIn, Oracle, and Fujitsu Professor Lemire maintains an active research group that has graduated numerous PhD students, many of whom now hold key positions at leading technology companies. He offers automatic scholarships for all students making progress on M.Sc. theses and Ph.D. programs in his lab, with tuition waivers for international Ph.D. students. His laboratory is equipped with a diverse server farm featuring multiple processor architectures (Intel Xeon, Core i7, Xeon Phi, POWER9, ARMv8) specifically designed for software performance experiments. The lab also explores virtual reality applications in data science. Lemire actively recruits students who are passionate about high-performance programming and open-source development, with special programs for Canadian undergraduate and graduate students through NSERC funding mechanisms.
Marc Geilen is an Associate Professor at the Electronic Systems group of Eindhoven University of Technology (TU/e) . He leads the Model-Based Design Lab within the CompSOC Lab and High Tech Systems Center .
Robert René Maria Birke is a tenured assistant professor in the Department of Computer Science at the University of Turin, leading research in the Parallel Computing group. His expertise spans virtual resource management, network design, workload characterization, and optimization of AI/big-data applications. Previously, he served as a visiting researcher at IBM Research Zurich and Principal Scientist at ABB Corporate Research, combining industry experience with academic rigor since earning his Ph.D. from Politecnico di Torino in 2009. His educational background includes: Ph.D. in Electronics and Communications Engineering, Politecnico di Torino (2009) Dr. Birke's research centers on systems-level challenges in distributed AI, with current projects investigating federated learning architectures, confidential computing via Trusted Execution Environments, and RISC-V processor optimizations for decentralized machine learning. His work bridges theoretical foundations with practical deployments, particularly in edge computing scenarios and high-performance data synthesis applications. Recent publications reveal growing emphasis on securing generative models against forgery attacks and optimizing tabular data synthesis techniques. Analysis of his 15 most recent publications (2024-2026) shows dominant themes in confidential federated learning (33% of works), RISC-V system optimizations (27%), and generative model security/synthesis (40%). This output spans premier venues including IEEE Transactions, ACM Computing Surveys, and SIGCOMM-affiliated conferences, demonstrating consistent contributions to systems-AI intersection research. Professional recognition includes: IEEE Senior Member While the text confirms extensive collaboration through co-authorships (notably with Marco Aldinucci, Lydia Chen, and Giulio Malenza), no specific student advisees or grant details are provided. His work appears embedded within European initiatives like ICS and EUPilot projects, focusing on compute continuum challenges. Dr. Birke actively contributes to the Parallel Computing group's mission through projects including HPC4AI@UNITO (datacenter digital twins) and Cross-Facility Federated Learning frameworks. His research ecosystem involves multi-institutional teams across Italy, Switzerland, and the EU, with recent talks addressing FLaaS implementations and generative model impacts on system design.
