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Alberto Ros is a Full Professor at the University of Murcia , Spain, in the Computer Engineering Department (DITEC) . His work focuses on cache coherence , memory hierarchy designs , memory consistency , and processor microarchitecture , with over 100 peer-reviewed publications. Dr. Ros earned his MS (2004) and PhD (2009) in Computer Science from the University of Murcia. He interned at the School of Informatics, University of Edinburgh , and held postdoctoral positions at the Technical University of Valencia and Uppsala University . He is an IEEE Senior Member . Research interests include optimizing hardware for multicore systems. His work spans cache coherence protocols, transactional memory, speculative execution, and data/instruction prefetching techniques. He led the ERC Consolidator Grant (2018) and ERC Proof of Concept Grant (2023) to improve multicore architecture performance. Recent publications emphasize hardware transactional memory efficiency, speculative execution, and secure cache systems. Notable works include cache locking, memory dependency prediction, and fine-grain coherence protocols. Scientific awards : Inducted into the MICRO Hall of Fame ISCA Hall of Fame 27 HiPEAC paper awards (MICRO, ISCA, HPCA, ASPLOS) Winner, ML-based Data Prefetching Competition Winner, 1st Instruction Prefetching Championship IEEE MICRO TopPicks for ISCA'17, MICRO'21 (honorable), MICRO'16 (honorable) Best paper awards at HiPC'16, FORTE'16 Honorable mention at HPCA'24 Nomination at ISCA'22 Grants as Principal Investigator include ERC Proof of Concept (2023) ERC Consolidator (2018) Europe Excellence (2018) Seneca Foundation, Young Leaders in Research (2014) . Dr. Ros is affiliated with the Computer Architecture and Parallel Systems Group (CAPS) at the University of Murcia and previously with UPMARC at Uppsala University.

• Computer Architecture
• Parallel Processing
• Multicore Processors
• +5 more

Ramon Canal is a Professor at the Universitat Politècnica de Catalunya (UPC), affiliated with the Barcelona School of Informatics and the Computer Architecture Department. He has served as Vice Dean of postgraduate studies and leads the VirtuOS (Virtualization and Operating Systems) research group. His academic background includes BSc, MSc, and PhD from UPC, with thesis supervision by Antonio González (UPC) and James E. Smith (University of Wisconsin-Madison). He completed sabbaticals at Harvard University (2006-2007) and University of Cyprus (2019-2020). Education: PhD, MSc, BSc in Computer Engineering (UPC) Research focus: Microarchitecture security, reliability across circuit/system levels, cloud optimization Recent publications address privacy in IoT, secure hardware accelerators, and safety-critical systems. His work contributes to the DRAC project (2019-2022), Red-RISCV network, and Horizon's Vitamin-V project. Awards include HiPEAC Paper Awards, IEEE Senior Member status, Fulbright recognition, and multiple education excellence accolades. Scientific Honors HiPEAC Paper Award (ISCA-44, 2017) IEEE Senior Member (2016) Best Paper Nominee (ICCD-32, 2014) UPC Outstanding PhD Award supervision (2011) He advises current MSc students and has mentored multiple PhD graduates. Professional activities span academic leadership, research collaborations with Barcelona Supercomputing Center (BSC), and technical contributions to reliability analysis frameworks like RECIPE and FRACTAL.

• Secure microarchitectures
• System reliability
• Virtualization and operating systems
• +5 more

Georgios Portokalidis is an Associate Research Professor at IMDEA Software Institute and Visiting Research Professor at Stevens Institute of Technology. He leads research in software systems security with focus on binary analysis, software hardening, and operating system security. His research develops practical defenses against software vulnerabilities through techniques like binary debloating, system call filtering, and hardware-assisted security. Current projects explore Rust language security, processor-assisted protection mechanisms, and vulnerability mitigation through code reduction. Publication trends show evolution from foundational binary analysis to applied security hardening, with recent emphasis on Rust security, hardware-assisted defenses, and real-world system protection. Work demonstrates consistent focus on practical, deployable security solutions. He has supervised numerous PhD students and postdocs, currently mentoring researchers at IMDEA. His group investigates binary analysis, software debloating, and system hardening techniques. Major grants include DARPA YFA (2021-2023) and ONR funding (2017-2022) supporting adaptive binary debloating research. Leads the systems security research group at IMDEA Software Institute, collaborating with international partners. Maintains active research partnerships and regularly contributes to top security conferences as program committee member.

• Systems Security
• Binary Analysis
• Software Hardening
• +1 more

Jose Luis Abellan Miguel is a Ramón y Cajal Fellow and Tenure-Track Associate Professor at the University of Murcia's Department of Computer Engineering and Technology. He leads the EcoArTech team and is a European R3 researcher. Previously, he held roles at the University of Ferrara, Boston University, and Universidad Católica de Murcia. His research focuses on GPU architectures, accelerators for machine learning, and privacy-preserving computing, particularly Fully Homomorphic Encryption (FHE). He has authored over 70 peer-reviewed publications and contributed to conferences like ISCA, HPCA, and MICRO. Education: Bachelor's, Master's, and PhD in Computer Science and Engineering (University of Murcia, 2007–2012) Research Interests: Abellan's work emphasizes architectural enhancements for GPU systems, customized accelerators for ML and FHE, and efficient synchronization/communication in many-core architectures. His contributions include tools like MGPU-Sim and STONNE for simulation, and frameworks like FIDESlib for FHE on GPUs. Recognition: HiPEAC Paper Awards (2011, 2019–2024) Top Picks in Hardware and Embedded Security 2024 European R3 Certificate (2024) Editorial roles at ACM TACO and Frontiers in Electronics Grants & Leadership: Recipient of a Ramón y Cajal fellowship and a Consolidación Investigadora grant. He chairs sessions at conferences like ISPASS and serves on TPCs for venues including DATE, HPCA, and MICRO. His lab collaborates with institutions like Georgia Tech, Northeastern University, and Intel. Labs/Teams: He leads the EcoArTech team, focusing on next-gen computing systems via architectural simulators. Collaborators include researchers from MIT, Boston University, and industry partners like NVIDIA and Intel.

• Computer Architecture
• GPU Systems
• Accelerators for Machine Learning
• +4 more

Alberto Ros Bardisa is a Professor at the Department of Computer Engineering and Technology within the Faculty of Informatics at the University of Murcia. He holds a Doctorate from the same university, completing his thesis on Efficient and Scalable Cache Coherence for Many-Core Chip Multiprocessors in 2009. His research focuses on computer architecture , with particular emphasis on cache coherence protocols , hardware transactional memory , speculative execution , and many-core systems . He has contributed to optimizing memory subsystems, concurrency management, and scalability in parallel computing environments. His work often bridges hardware-software co-design to enhance performance and security in modern architectures. Dr. Ros Bardisa is affiliated with the Computer Architecture and Parallel Systems research group and previously contributed to the Architecture and Parallel Computing group. His publications (over 130+ listed) reflect a sustained focus on advancing cache efficiency, transactional memory systems, and speculative execution techniques. His current work explores innovative solutions for fine-grain coherence , secure prefetching , and atomic operation optimization , with recent contributions in 2025 addressing novel protocols like WoperTM and MASCOT.

• Computer Architecture
• Parallel Computing
• Hardware Optimization
• +6 more

José L. Abellán is a Ramón y Cajal Fellow (Tenure-Track Associate Professor) and European R3 researcher at the University of Murcia's Department of Computer Engineering and Technology. He leads the EcoArTech research group and holds a Ph.D. in Computer Science from the University of Murcia (2012). His career includes postdoctoral positions at Boston University and previous faculty roles at Universidad Católica de Murcia. Dr. Abellán's research focuses on architectural enhancements for GPU systems and customized accelerators targeting machine learning and fully homomorphic encryption applications. His work spans hardware/software co-design, microarchitectural extensions for privacy-preserving computation, and efficient parallel processing. His extensive publication record demonstrates consistent contributions to GPU architecture, processing-in-memory, hardware acceleration for cryptography, and graph neural networks. Recent work has appeared in top computer architecture venues including MICRO, ASPLOS, and HPCA. Awards and Honors HiPEAC Paper Awards (2019, 2020, 2023, 2024) Best Paper Award at IPDPS 2011 Top Picks in Hardware and Embedded Security 2024 European R3 Certificate (2024) Dr. Abellán leads the EcoArTech research team and serves as Associate Editor for ACM Transactions on Architecture and Code Optimization (TACO) and Frontiers in Electronics. He is a Senior Member of IEEE and active in the HiPEAC European network.

• GPU Architecture
• Hardware Accelerators
• Machine Learning
• +3 more

Jan Reineke is a Professor of Computer Science at Saarland University , where he leads research at the intersection of hardware and software. His work focuses on timing-predictable microarchitectures, real-time systems, and hardware-software security contracts. Affiliation: Saarland University (since 2012) Previous: Postdoctoral scholar at UC Berkeley (2009-2011) Research Interests include static program analysis, real-time systems, computer architecture, and hardware-related security issues. His group develops tools like LLVMTA , uops.info , and Spectector for cache analysis, microarchitectural profiling, and speculative execution security. Design of timing-predictable processors (RTSS 2018, RTSS 2019) Exact LRU cache analysis (CAV 2017, POPL 2019, RTSS 2019) Detection of speculative information flows (S&P 2020, S&P 2021) Quantitative cache analysis frameworks (RTAS 2025) Recent Articles span cache timing analysis, speculative execution vulnerabilities, and performance modeling. Keywords include Real-Time Systems , Security , Computer Architecture , and Static Analysis , with sub-fields covering cache persistence, hardware-software contracts, throughput prediction, and formal verification of side-channels. Scientific Awards include an ERC Advanced Grant (2021) , multiple best paper awards (RTAS 2025, DATE 2024, CCS 2023), and the Intel Early Career Faculty Honor Program (2012). Advising and Grants : He actively recruits PhD students and postdocs for hardware-software security research, supported by the ERC grant. His lab's alumni include Dr. Sebastian Hahn, and he has hosted numerous student assistants. Labs and Teams : He leads the Real-Time and Embedded Systems Lab at Saarland Informatics Campus, collaborating on projects like uops.info (Intel microarchitectural profiling) and chi (cache hierarchy inference).

• static analysis
• real-time systems
• computer architecture
• +1 more

Alexandra Jimborean is a Ramón y Cajal researcher at the University of Murcia and affiliated Associate Professor at Uppsala University. She holds a PhD from the University of Strasbourg and specializes in compile-time code analysis, optimization, and software-hardware co-designs for performance and energy efficiency. Research focuses on: Instruction prefetching and speculative execution mechanisms Compiler-assisted code optimization techniques Hardware-software co-design for secure and efficient processors Dynamic program analysis frameworks Significant contributions include the development of the DAEDAL and Clairvoyance compiler technologies, commercialized through the EtaScale startup. Holds leadership roles in major conferences including Program Chair for CGO 2019 and CC 2020.

• Compiler Design
• Hardware-Software Co-Design
• Code Optimization
• +5 more

Lesly-Ann Daniel is an Assistant Professor at EURECOM in the software and system security (S3) group , specializing in formal methods for low-level security . Her research spans binary analysis, symbolic execution, and hardware-software co-designs for microarchitectural security. PhD in Computer Science (2021) from CEA List , supervised by Sébastien Bardin and Tamara Rezk Postdoctoral researcher at DistriNet, KU Leuven (2021-2025) Co-developer of tools Binsec/Rel and Binsec/Haunted for binary-level security analysis Her research focuses on applying formal methods to detect vulnerabilities in cryptographic code, mitigate microarchitectural side-channels , and enhance security through RISC-V extensions . Key projects include ProSpeCT for secure speculation and Architectural Mimicry for control-flow linearization. Notable awards include the FWO Junior postdoctoral fellowship , PhD thesis award from Université Côte d’Azur , and the L’Oréal-UNESCO Jeunes Talents France fellowship. She serves on program committees for CCS, EuroS&P, and PriSC workshops.

• Formal Methods
• Low-Level Security
• Binary Analysis
• +5 more

Marco Vassena is an Assistant Professor at the Department of Information and Computing Sciences, Utrecht University. His research focuses on using programming language techniques like type systems, compilers, and program verification to build secure systems with reliable security guarantees. Affiliation: Utrecht University, Netherlands Research Areas: Language-based security, memory safety, constant-time programming, information flow control, WebAssembly security, and defenses against microarchitectural attacks. His work includes developing frameworks for secure execution environments, such as MSWasm for WebAssembly, and advancing tools like Blade to mitigate speculative leaks in cryptographic code. He has contributed to leading conferences including POPL, PriSC, and PLDI. Scientific Awards: Veni Grant (2023)

• Programming Languages
• Security
• Compilers
• +7 more

Gilles Barthe is Research Professor (part-time) at IMDEA Software Institute and Director at Max Planck Institute for Security and Privacy. His research develops programming language techniques and verification methods for security applications, particularly cryptographic implementations and differentially private computations. Research focuses on formal methods for security proofs, including relational program verification, cryptographic protocol analysis, and privacy-enhancing technologies. Key areas include automated proofs for lattice-based cryptography, secure compilation techniques, and verifying constant-time properties against side-channel vulnerabilities. Barthe leads projects on formal verification of cryptographic standards including AES-GCM and SHA-3, and develops tools like EasyCrypt for computer-aided cryptographic proofs. Recent work addresses Spectre vulnerability mitigations and quantum program verification.

• Formal Methods
• Programming Languages
• Cryptography
• +3 more

Marco Guarnieri is an Associate Research Professor at the IMDEA Software Institute in Spain. He holds a PhD in Computer Science from ETH Zurich (2017), an MSc in Computer Engineering from the Università degli Studi di Bergamo (2012), and a BSc in Computer Engineering from the same institution (2010). His research focuses on secure hardware-software co-design, microarchitectural side-channel attacks, and formal methods for verifying security guarantees. Education : PhD in Computer Science, ETH Zurich (2017) MSc in Computer Engineering, Università degli Studi di Bergamo (2012) BSc in Computer Engineering, Università degli Studi di Bergamo (2010) Research Interests : Security, privacy, programming languages, formal methods, and microarchitectural security. His work emphasizes practical systems for securing sensitive data storage and processing, with recent focus on leakage contracts for open-source processors and automated testing of secure speculation countermeasures. Awards : Best Paper Award at CCS 2024 for work on leakage contracts for RISC-V processors Distinguished Paper Award at CCS 2023 for Spectre attack detection Best Paper Award at S&P 2021 for hardware-software contracts for secure speculation Grants & Advising : He leads a research group at IMDEA, actively mentoring PhD students and postdocs in hardware-software security. His projects include AMuLeT (automated testing of secure speculation) and LeaVe (verifying leakage contracts). Labs/Teams : IMDEA Software Institute’s security research group, focusing on cross-layer hardware-software security solutions.

• Security
• Privacy
• Programming Languages
• +3 more

Juan Jose Costa Prats is a researcher in the Department of Computer Architecture at the Universitat Politècnica de Catalunya (UPC), affiliated with the Escola Tècnica Superior d'Enginyeria de Telecomunicació de Barcelona. He is a key member of the CRAAX - Centre de Recerca d'Arquitectures Avançades de Xarxes, contributing to advanced research in computing systems and network architectures. His work is deeply integrated into competitive R&D projects, including Horizon Europe and national initiatives focused on digital innovation and infrastructure. Research Interests: Costa Prats specializes in high-performance and distributed computing, with a strong focus on parallel programming models (especially OpenMP), software distributed shared memory (SDSM), cloud computing, virtualization, and cybersecurity. His recent work emphasizes secure and resilient computing systems, particularly through RISC-V-based architectures, hypervisor extensions, and runtime malware detection using opcode analysis and machine learning. He also contributes to educational innovation through remote datacenter laboratories. Publication Trends: His recent publications (2021–2024) reflect a shift toward secure, trustworthy computing environments, especially in cloud and IoT contexts. Themes include RISC-V virtualization, intrusion detection using transfer learning, GPS spoofing detection, and secure development frameworks like Vitamin-V. These works highlight a convergence of system architecture, security, and machine learning. Scientific Awards: No specific awards mentioned in the provided text. Advising and Grants: While no formal students are listed, Costa Prats collaborates extensively with leading researchers such as Beatriz Otero, Ramon Canal, and Javier Verdú. He participates in numerous competitive R&D+i projects funded by the Spanish government and the European Union, including Horizon Europe, RIS3CAT, and national research programs, focusing on cloud resilience, intelligent cloud management, and RISC-V ecosystem development. Labs and Teams: He is an active member of the CRAAX research group at UPC, which works on advanced computing architectures. His research often involves collaboration with the Barcelona Supercomputing Center. His projects, such as Vitamin-V and Remote DasaLAB, indicate involvement in both secure computing environments and innovative educational platforms.

• High-Performance Computing
• Distributed Systems
• Parallel Computing
• +12 more

Ramon Canal Corretger is a Full Professor in the Department of Computer Architecture at the Faculty of Informatics of Barcelona (FIB), Universitat Politècnica de Catalunya (UPC). He previously served as Vice Dean of Postgraduate Studies at FIB and leads the VirtuOS (Virtualization and Operating Systems) research group. His work bridges computer architecture, hardware security, and system-level reliability. Doctorate from UPC, co-supervised at the University of Wisconsin-Madison Sabbaticals at Harvard University (2006–2007) and the University of Cyprus (2019–2020) Active leadership in EU-funded projects such as Vitamin-V (Horizon Europe) His research focuses on microarchitecture, processor and memory design, reliability under variability, and security at the hardware-software interface. He explores low-power multicore architectures, virtualization optimizations, and secure RISC-V-based systems. His recent work integrates AI for intrusion detection and privacy-preserving federated learning in fog computing environments. The most recent publications demonstrate a strong trend toward security, reliability, and trustworthy computing , particularly in RISC-V ecosystems and cloud/edge infrastructures. There is increasing emphasis on hardware-software co-design , attack detection via performance monitoring , and energy-efficient secure accelerators using emerging technologies like neuromorphic and photonic computing. Scientific Awards: HiPEAC Paper Awards (2017, 2010) IEEE Senior Member (2016) Fulbright Award (2006) IBM Faculty Award (2000) Best Student Paper at HPCA-6 (2000) Multiple teaching excellence recognitions from UPC and AQU Catalunya First Prize in Epson Foundation Rosina Ribalta Award (2001) He has advised several PhD students including Manish Rana, Zoran Jaksic, and Shrikanth Ganapathy, many of whom received honors such as the Intel Doctoral Student Programme recognition. His research is supported by competitive grants from the Spanish government, EU Horizon programs, and industry collaborations. He is actively involved in the design of secure, reliable, and efficient computing systems for future cloud and embedded applications. He leads the VirtuOS research group, which focuses on virtualization, operating systems, and hardware-software interface optimization. The group contributes to open-source RISC-V initiatives and participates in large-scale European R&D projects targeting trustworthy computing infrastructures.

• Microarchitecture
• Processor Design
• Memory Design
• +15 more

Manuel Alejandro Pajuelo González is a researcher at the Universitat Politècnica de Catalunya (UPC), affiliated with the Department of Computer Architecture and the School of Computer Science. His research focuses on Performance measurement Operating systems Virtualization Thread assignment in multithreaded processors Recent publications show strong trends in RISC-V architectures, cybersecurity, and performance optimization. Key themes include Hardware virtualization Intrusion detection frameworks Statistical thread assignment approaches Spin-lock overhead analysis Scientific awards include BDigital Global Congress 15ª Edició Computación de Altas Prestaciones VI HiPEAC Paper Award He participated in multiple competitive R&D projects, including the DRAC project focused on RISC-V accelerators for next-generation computing.

• Performance Measurement
• Operating Systems
• Virtualization
• +3 more