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Luo MaiView profile

Assistant Professor

• Computer Systems
• Machine Learning Systems
• Data Management
• +3 more

Luo Mai is an Assistant Professor at the University of Edinburgh's School of Informatics , with an upcoming promotion to Associate Professor (UK Reader) in August 2025. He leads the Large-Scale Machine Learning Systems Group and co-leads the UK EPSRC Centre for Doctoral Training in Machine Learning Systems and an ARIA Project on Scaling AI Compute by 1000X . PhD in Computer Science (Imperial College London, 2018) MRes in Advanced Computing (Imperial College London, 2012) His research focuses on the intersection of computer systems , machine learning , and data management . Key contributions include award-winning systems like WaferLLM (wafer-scale LLM inference), Tenplex (elastic ML), and ServerlessLLM (serverless LLM serving), published at top venues (OSDI, SOSP, ICML, NeurIPS, JMLR). Recent publications demonstrate trends in GPU-based distributed systems , LLM optimization , and adaptive machine learning . His team has developed groundbreaking open-source projects including TensorLayer , TorchOpt , and ServerlessLLM . Awarded Microsoft Research StarTrack Scholar (2024) , secured ARIA grant (2024) with Imperial College & Cambridge University, and received Google Fellowship during PhD (2012-2016). As an educator, he designed Edinburgh's popular Machine Learning Systems course (150+ students). His group supervises multiple PhD students including Yao Fu (recognized as 2024 Rising Star in ML & Systems) and Leyang Xue .

Mateo Valero CortésView profile

Professor

• Computer Architecture
• High-Performance Computing
• Parallel Computing
• +3 more

Mateo Valero Cortés is a renowned Professor of Computer Architecture at the Polytechnic University of Catalonia and Director of the Barcelona Supercomputing Center (BSC). He has held academic and leadership roles since 1974, advancing high-performance computing (HPC) and computer architecture research. His work includes pioneering contributions to vector architectures, multithreading, and instruction-level parallelism. Education includes a Telecommunications Engineering degree from the Polytechnic University of Madrid (1974) and a PhD in Telecommunications Engineering from the Polytechnic University of Catalonia (1980). His research spans over 700 publications, focusing on HPC systems, parallel computing, and supercomputing infrastructure. Key research interests include vector processing, super-scalar processors, and task-based programming models. Recent work emphasizes scalable architectures for exascale computing and energy-efficient hardware-software co-design. Notable achievements include the Eckert-Mauchly Prize (highest in computer architecture), Seymour Cray Award, and Charles Babbage Prize. He has led initiatives like the Spanish Supercomputing Network (RES) and PRACE (European HPC partnership). Academic affiliations include the Royal Academy of Engineering of Spain, ACM Fellow, and IEEE Fellow. He has received 13 honorary doctorates and awards such as Mexico’s Order of the Aztec Eagle. Current projects include the Mont-Blanc HPC prototype and ERC-funded research on multi-core chip design. His BSC oversees over 300 researchers and manages MareNostrum supercomputers.

Georgios PortokalidisView profile

Research Professor

• Systems Security
• Binary Analysis
• Software Hardening
• +1 more

Georgios Portokalidis is an Associate Research Professor at IMDEA Software Institute and Visiting Research Professor at Stevens Institute of Technology. He leads research in software systems security with focus on binary analysis, software hardening, and operating system security. His research develops practical defenses against software vulnerabilities through techniques like binary debloating, system call filtering, and hardware-assisted security. Current projects explore Rust language security, processor-assisted protection mechanisms, and vulnerability mitigation through code reduction. Publication trends show evolution from foundational binary analysis to applied security hardening, with recent emphasis on Rust security, hardware-assisted defenses, and real-world system protection. Work demonstrates consistent focus on practical, deployable security solutions. He has supervised numerous PhD students and postdocs, currently mentoring researchers at IMDEA. His group investigates binary analysis, software debloating, and system hardening techniques. Major grants include DARPA YFA (2021-2023) and ONR funding (2017-2022) supporting adaptive binary debloating research. Leads the systems security research group at IMDEA Software Institute, collaborating with international partners. Maintains active research partnerships and regularly contributes to top security conferences as program committee member.

Leonardo SurianoView profile

Researcher

• Runtime Adaptive Hardware/Software execution
• High-Performance Computing
• Parallel Computing
• +4 more

Leonardo Suriano is a Ph.D. student at the Universidad Politécnica de Madrid (UPM), affiliated with the Department of Electronic Engineering. His research focuses on runtime adaptive hardware/software execution in complex heterogeneous systems (CPU + FPGA + GPU), high-performance computing, parallel computing, and embedded systems. He has contributed to European projects Enable S3 and Cerbero, developed tools for dataflow-based design space exploration, and is a contributor to the PREESM open-source project on GitHub. His work bridges hardware acceleration, cyber-physical systems, and real-time computation. He received the Best Research Project at the Industrial Research Meeting 2016 Best Oral Session award in the Simposio Tu Tesi en 4 Minutos (UPM, 2018) He has published extensively on heterogeneous MPSoC optimization, inverse kinematics, and image processing, with key subfields including GPU/FPGA integration, task scheduling, and firmware development.