Find Academic Supervisors

Daniel W. BlissView profile

Professor

• Radar
• Wireless Communications
• Precision Positioning
• +7 more

Daniel W. Bliss is a Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University and Director of ASU's Center for Wireless Information Systems and Computational Architectures (WISCA). With over $50 million in research funding as principal investigator from organizations including DARPA, ONR, Google, and Airbus, his work bridges theoretical foundations with practical implementations across multiple domains of wireless systems. Dr. Bliss received his educational foundation with a B.S.E.E. from Arizona State University (1989), followed by M.S. and Ph.D. degrees in Physics from the University of California-San Diego (1995, 1997). His academic journey includes significant industry experience at General Dynamics (1989-1993) and MIT Lincoln Laboratory (1997-2012) before joining ASU. His research program focuses on advanced wireless systems spanning radar, communications, precision positioning, computational architectures, and medical monitoring applications. Bliss employs information theory, estimation theory, and signal processing to develop novel system concepts with disruptive capabilities. Current research emphasizes RF convergence, integrated sensing and communications, and anticipatory medical analytics using wireless technologies, with particular focus on extracting physiological data from radar signals. Analysis of recent publications reveals a strong trend toward integrated sensing and communications systems, particularly utilizing mmWave and radar technologies for medical monitoring applications. His work increasingly bridges traditional communications and radar domains while expanding into physiological monitoring, demonstrating a clear trajectory toward convergence of wireless technologies for healthcare applications and remote vital sign detection. Dr. Bliss has received significant recognition for his contributions: Fellow of the IEEE (2015) 2021 IEEE Warren D. White Award for Excellence in Radar Engineering 2016-2017 Top 5% Teaching Award at ASU 2017 ASU Fulton Engineering Exemplar Faculty As a dedicated mentor, Dr. Bliss has supervised numerous graduate students through successful dissertation and thesis defenses across both PhD and Master's programs. His research portfolio includes substantial funding from diverse sources with over $50 million secured as principal investigator. Current projects include the $17M DARPA DASH project focused on advanced software-reconfigurable heterogeneous SoCs for next-generation RF systems, and multiple initiatives in contactless vital sign monitoring using radar technologies. Dr. Bliss leads the BLISS Lab and serves as director of WISCA, fostering interdisciplinary research in wireless systems. His team includes researchers working on distributed coherent systems, MIMO radar, RF convergence, and medical monitoring applications, with recent successes including the Making Waves team that tied for first place in the Air Force Spark Tank challenge. He has founded two startup companies: DASH Tech Integrated Circuits Company and the Big Little Sensor Company, focusing on high-performance embedded processing and small-scale radar physiological monitoring, respectively.

Gustavo AlonsoView profile

Professor

• Databases
• Distributed Systems
• Cloud Computing Architecture
• +4 more

Gustavo Alonso is Full Professor at the Department of Computer Science (D-INFK) of ETH Zurich and Head of the Institute for Computing Platforms . He has been at ETH since 1995, first as a post-doc, then as Assistant Professor from April 1998, and promoted to Full Professor in October 2001. Within the Systems Group he leads the Information and Communication Systems Research Group . Education: 1989 – Telecommunications Engineering (undergraduate), Madrid Technical University (UPM-ETSIT), Spain 1992 – M.S. Computer Science, University of California, Santa Barbara (UCSB) 1994 – Ph.D. Computer Science, University of California, Santa Barbara (UCSB) Research Interests: His work spans databases, distributed systems, cloud-computing architecture, FPGAs, hardware acceleration for data science, parallel and reconfigurable computing . The group investigates how modern heterogeneous hardware—from GPUs to SmartNICs—can be integrated into data-processing systems to achieve orders-of-magnitude performance gains, energy savings, and new functionality such as in-network computation and serverless acceleration. Scientific Awards & Honors: Fellow of the ACM (Association for Computing Machinery) Fellow of the IEEE (Institute of Electrical and Electronics Engineers) Distinguished Alumnus, Department of Computer Science, UC Santa Barbara Four Test-of-Time / Most Influential Paper Awards across databases, programming languages, cloud computing, and software engineering Labs & Projects: He directs the Information and Communication Systems Research Group within the Systems Group ( systems.ethz.ch ). The lab develops open-source platforms such as Coyote v2 for FPGA abstractions, Shuhai for HBM benchmarking, and MicroRec for micro-second recommendation serving, while collaborating with industry on SmartNICs, serverless analytics, and cloud-scale data analytics.

Andre DeHonView profile

Professor

• Reconfigurable Computing
• FPGA Architecture
• Interconnect Design
• +6 more

André DeHon is the Oliver C. Boileau Jr. and Nan Eleze Boileau Professor of Electrical Engineering at the University of Pennsylvania, with affiliations in the Electrical and Systems Engineering (ESE) and Computer and Information Science (CIS) departments. He founded the Penn Computer Engineering (CMPE) program and directs the DARPA-sponsored CyberSavvy Security Center. His research spans reconfigurable computing, FPGA architecture, interconnect design, hardware security, and energy efficiency, with a focus on adapting to fabrication imperfections and runtime variability. His work explores programmable substrates (e.g., CMOS VLSI, molecular electronics) and algorithmic mappings to create resilient, efficient systems. Current projects include runtime feedback mechanisms (REFINE), partial reconfiguration (ExHiPR), and security frameworks like SCALPEL and μSCOPE. Recent publications highlight advancements in FPGA compilation (PLD, HiPR), security (SCALPEL, μSCOPE), and interconnect optimization (Asymmetry in NoC). These studies intersect computer architecture, security, and embedded systems. Scientific awards and recognitions: 2023 IEEE Fellow 2020 IEEE Mary Kenneth Keller Teaching Award 2018 ACM Fellow TCFPGA Hall of Fame (2019) Best Paper at ICFPT 2015 Academic leadership: He chairs the ACM/SIGDA Technical Committee on FPGAs and Reconfigurable Computing, previously held faculty roles at Caltech (1999–2006), and was a postdoc at UC Berkeley (1996–1999). Education includes MIT SB (1990), SM (1993), and PhD (1996) in Electrical Engineering and Computer Science.

Zhonghai LuView profile

Professor

• Computer Architecture
• Embedded Systems
• Network-on-Chip (NoC)
• +7 more

Zhonghai Lu is a Professor of Electronic Systems Design (specializing in Dependable and Autonomous Systems) at KTH Royal Institute of Technology, part of the Department of Electrical Engineering in the School of Electrical Engineering and Computer Science (EECS). He serves as Program Director for KTH's Embedded Systems master's program and Director of Studies at the Division of Electronics and Embedded Systems. His research focuses on Network-on-Chip (NoC), computer architecture, embedded systems, and Prognostics and Health Management (PHM) of power electronics. He leads a research group exploring in-network processing and embedded intelligence, transforming passive networks into active computational frameworks. Lu holds a BSc from Beijing Normal University (1989), MSc and PhD from KTH (2002, 2007), and an MBA in Innovation and Growth from the University of Turku (2012). He has authored over 240 scientific papers, including journal articles and peer-reviewed conferences, with notable recognitions such as Best Paper Awards at NOCS’2015 and EU HiPEAC, and a Featured Paper in IEEE Transactions on Computers (2020). He serves as Associate Editor for ACM Transactions on Architecture and Code Optimization (TACO) and has chaired major conferences like HiPEAC’2017 and NOCS’2018. His research group’s recent work includes integrating AI into hardware acceleration, fault-tolerant neural networks, and RUL estimation for power electronics using recurrent neural networks. Lu has secured grants from the Swedish Research Council and Intel Corporation and developed courses like IL2230 (Hardware Architectures for Deep Learning) and IL2233 (Embedded Intelligence), pioneering embedded AI education at KTH. Education: BSc (Beijing Normal University), MSc/PhD (KTH), MBA (University of Turku) Awards: Best Paper Awards (NOCS, EU HiPEAC), Swedish Research Council Grants, Intel Research Gifts Labs/Teams: Research Group on In-Network Processing and Embedded Intelligence

Carlos Errando HerranzView profile

Assistant Professor

• quantum photonics
• integrated photonics
• color centers
• +3 more

Carlos Errando Herranz serves as an Assistant Professor in the Quantum and Computer Engineering Division at Delft University of Technology's Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS) and as a Principal Investigator at QuTech. His research focuses on developing scalable quantum photonic integrated circuits using semiconductor fabrication processes compatible with existing infrastructure for quantum internet applications. He received Bachelor's and Master's degrees from Universitat Politècnica de València (2013) and a PhD in Micro and Nanosystems from KTH Royal Institute of Technology (2018), followed by postdoctoral positions at KTH and MIT as a Marie Curie fellow. His lab investigates quantum photonics, integrated photonics, and color centers with emphasis on diamond tin-vacancy systems and silicon-based quantum emitters. Recent publications demonstrate strong expertise in tuning quantum emitters via strain engineering, heterogeneous integration of spin-photon interfaces, and MEMS-enabled reconfigurable photonics. Key advancements include cavity-enhanced quantum memories, superconducting detector integration, and spectral control of solid-state emitters for quantum networks. Dr. Herranz advises seven graduate students including PhD candidates Vicky Dominguez Tubio, Arjan Mejas, Matteo Pirro, Christian Primavera, Jan Riegelmeyer, and Elena Volkova, along with Master student Bram Zijlstra. His team comprises postdocs Lin Jin and Pat Laferriere, and interns Elsa Herranz Valiente and Ernest Staffetti Cruañas. The Errando Herranz Lab operates within QuTech's Quantum Internet Division at Delft University, maintaining specialized facilities for nanofabrication and optical characterization of quantum photonic devices. Current research directions include developing CMOS-compatible quantum memories operating at telecom wavelengths and scalable architectures for quantum repeaters.

José F. MartínezView profile

Professor

• Computer Architecture
• Microprocessor Design
• Multiprocessor and Multicore Architectures
• +5 more

José F. Martínez holds the Lee Teng-hui Professorship of Engineering at Cornell University's College of Engineering, where he leads research in computer architecture and systems. His roles include Vice Chair of ACM SIGARCH, IEEE Fellow, and past leadership roles in ISCA, MICRO, and IEEE Computer Society journals. He has received prestigious awards such as the NSF CAREER Award, IBM/Qualcomm Faculty Awards, and multiple teaching accolades including Tau Beta Pi Professor of the Year (2011). Education: Licenciado en Informática de Sistemas (1996), Universidad Politécnica de Valencia M.S. (1999) and Ph.D. (2002) in Computer Science, University of Illinois at Urbana-Champaign His research focuses on computer architecture , including microprocessors, multiprocessors, memory subsystems, embedded systems, and processing-in-memory (PIM) innovations. He co-leads the DARPA/SRC ACE Center for Evolvable Computing and NSF's CROPPS Center, and previously co-founded Cornell's Institute for Digital Agriculture (CIDA). His work bridges hardware-software co-design and sustainable computing. Key Contributions: Advancing energy-efficient multiprocessor architectures Developing PIM frameworks like PUMICE and Membrane Market-based resource allocation systems (e.g., XChange, ReBudget) His advising spans over 15 graduate students and has guided Merrill Presidential Scholars. Current research explores evolvable computing paradigms and AI hardware acceleration, reflecting his dual focus on foundational architecture and applied systems innovation.

Marco PlatznerView profile

Professor

• Reconfigurable Computing
• Approximate Computing
• Self-Aware Computing
• +7 more

Marco Platzner is a Professor for Computer Engineering at Paderborn University , Germany. He serves as the Dean of Research for the Faculty of Computer Science, Electrical Engineering and Mathematics and heads the Department of Computer Science. Previously, he held research positions at ETH Zurich, Stanford University, GMD (now Fraunhofer IAIS), and Graz University of Technology. Education: Diploma and PhD in Telematics (Graz University of Technology, 1991 and 1996), Habilitation in Hardware-Software Co-Design (ETH Zurich, 2002) Research Interests focus on reconfigurable computing, approximate computing, self-* computing, and embedded systems. His work addresses hardware security, FPGA design, and sustainable AI in data centers. Current projects include energy-efficient AI through deep neural network approximation for FPGAs (EKI-App) and lifecycle sustainability of socio-technical systems (SAIL). Publication Trends show expertise in FPGA security, approximate circuit synthesis, robotics, and hardware acceleration. Collaborations span robotics (ROS 2 integration), AI (transformer optimization), and cybersecurity (Trojan detection). Scientific Awards: ACM SIGDA Hall of Fame (2020) Significant Paper Award (FPL 2015) Best Paper Awards at IEEE ISVLSI (2024), ARC (2018), IEEE ReConFig (2015), and others Weierstraß Prize for Teaching (2008) Leadership Roles include membership in the board of Paderborn Center for Parallel Computing (PC2) and the Jenny Aloni Centre for Early Career Researchers. He has contributed to EU FP7 FET project EPiCS and German priority programs on embedded systems and organic computing.

Julia R. GreerView profile

Professor

• Mechanics of Hierarchical Architectures
• Nanomaterials
• Additive Manufacturing
• +7 more

Julia R. Greer serves as the Ruben F. and Donna Mettler Professor of Materials Science, Mechanics and Medical Engineering at the California Institute of Technology (Caltech), where she also holds the position of Executive Officer for Applied Physics and Materials Science since 2025. She earned her B.S. from MIT (1997) and M.S./Ph.D. from Stanford University (2000/2005), joining Caltech as Assistant Professor in 2007, promoted to Professor in 2013, and appointed to her current named professorship in 2019. Her research spans mechanics of hierarchical architectures , nanomaterials , and additive manufacturing , with significant contributions to energy storage systems and biomedical materials . Key focus areas include nano-scale mechanical properties, in-situ deformation analysis, and development of novel fabrication techniques for micro-architected materials. Her group pioneered hydrogel infusion additive manufacturing for metals and multiphoton 3D lithography standards. Analysis of recent publications reveals strong emphasis on solid-state battery interfaces (2025), bioresorbable microrobots (2024), and AI-enabled material design (2024), demonstrating cross-disciplinary impact across energy, healthcare, and quantum technologies. Her work consistently bridges fundamental nanomechanics with practical applications in energy storage and medical devices. 2024 ASME Nadai Medal 2024 SES A.C. Eringen Medal Elected to National Academy of Sciences (2025) Fletcher Jones Foundation Director (2019-2025) Professor Greer has advised over 40 PhD students including Seola Lee (2025) and Wenxin Zhang (2025), with research funded by collaborations spanning MIT, UCSF, Purdue, and ETH Zurich. Her group maintains active projects in lightweight nanoarchitected materials for impact absorption, electroactive polymers for braille devices, and 3D interdigitated solid-state batteries. Current leadership includes Editor-in-Chief of the Journal of Applied Physics (2024-) and direction of Caltech's Materials Science department.

• Storage Systems
• Persistent Memory
• Key-Value Stores
• +4 more

Oana Balmau is an Assistant Professor in the School of Computer Science at McGill University, where she leads the Data-Intensive Storage and Computer Systems Laboratory (DISCS Lab). She also holds a status-only appointment at the University of Toronto and serves as a working group chair for MLPerf Storage. Her research focuses on creating storage infrastructure that enables fast and energy-conscious insights from data, with particular emphasis on storage and persistent memory technologies for machine learning, data science, and edge computing workloads. Dr. Balmau's research interests span computer systems, with specific focus on: Design and implementation of efficient key-value stores Storage systems for machine learning workloads Edge computing infrastructure Persistent memory technologies Performance optimization of data-intensive systems Her recent work has led to significant contributions in storage benchmarking through the MLPerf Storage benchmark and in edge computing frameworks. The MLPerf Storage benchmark has become an industry standard for evaluating storage performance in machine learning environments, while her work on hierarchical edge computing addresses security and performance challenges in distributed edge environments. Her publications show consistent high-impact contributions to top systems venues, with recent work focusing on processing-in-memory virtualization, stream processing reconfiguration, and efficient data preprocessing pipelines. Dr. Balmau has received numerous awards for her research, including: SEC 2024 Best Paper Award for "Falcon: Live Reconfiguration for Stateful Stream Processing on the Edge" MLCommons Hero Award 2023 for leadership as MLPerf Storage working group chair ACM SIGOPS Dennis M. Ritchie Doctoral Dissertation Award 2021 Honorable Mention CORE John Makepeace Bennett Award 2021 for the best Computer Science doctoral dissertation in Australia and New Zealand USENIX ATC 2019 Best Paper Award for "SILK: Preventing Latency Spikes in Log-Structured Merge Key-Value Stores" As an educator, Dr. Balmau teaches courses on advanced computer systems, operating systems, and principles of computer systems design at McGill University. She has served on program committees for top systems conferences including SOSP, SIGMOD, FAST, and EuroSys, and has co-organized workshops on resource-efficient machine learning and edge computing. She leads the DISCS Lab, which focuses on two main research directions: Systems for ML (including the MLPerf Storage benchmark) and Edge computing (including frameworks for fast and secure edge computing in hierarchical edge environments).

• Reconfigurable Computing
• Field-Programmable Gate Arrays (FPGA)
• High-Level Synthesis
• +3 more

Paolo Ienne is a Professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), where he leads the Processor Architecture Laboratory (LAP) within the School of Computer and Communication Sciences. His research focuses on advancing reconfigurable computing systems through innovative FPGA architectures and high-level synthesis methodologies. His primary research domains include reconfigurable computing, FPGA architecture design, dynamically scheduled dataflow circuits, and hardware acceleration techniques. Recent work emphasizes memory system optimization for FPGAs, formal verification of circuit transformations, and rapid C-to-hardware compilation flows. He has pioneered approaches for handling thousands of outstanding memory misses in FPGA accelerators and developed novel techniques for switch-block exploration without explicit pattern enumeration. Analysis of his 2023-2025 publications reveals a strong trend toward practical FPGA deployment challenges, with increasing focus on HBM integration, virtual memory systems for PCIe-attached devices, and formally verified circuit transformations. His work consistently targets real-world bottlenecks in high-level synthesis toolchains while maintaining theoretical rigor in dataflow architecture design. Professor Ienne's laboratory receives support from the Swiss National Science Foundation and industry partners including Huawei, enabling cutting-edge research in FPGA-based acceleration. His collaborative network spans major semiconductor companies and academic institutions worldwide, with frequent co-authorship on conference proceedings and journal publications in IEEE and ACM venues.

Jingtong HuView profile

Associate Professor

• Cyber-Physical Systems
• Infrastructure Security
• Non-Volatile Memory Systems
• +6 more

Jingtong Hu is an Associate Professor at the Swanson School of Engineering, University of Pittsburgh, where he also holds the William Kepler Whiteford Faculty Fellowship. His research focuses on Cyber-Physical Systems and Infrastructure Security, with significant contributions to embedded systems, non-volatile memory architectures, and hardware/software co-design for energy-constrained environments. Dr. Hu received his PhD from the University of Texas at Dallas (2007-2013) and his Bachelor of Engineering from Shandong University (2003-2007). His research spans multiple interdisciplinary areas including energy harvesting systems, non-volatile processors, FPGA acceleration, and machine learning at the edge. His recent publications demonstrate a strong focus on algorithm-hardware co-design, particularly for vision transformers, federated learning, and non-volatile memory systems. His work often addresses the challenges of implementing AI on resource-constrained edge devices, with emphasis on energy efficiency, reliability, and performance optimization. The trend in his publications shows increasing focus on sustainable AI processing, heterogeneous computing architectures, and personalized machine learning for IoT applications. Selected Awards: IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award (2021) ACM SIGDA Meritorious Service Award (2019) Multiple Best Paper Award nominations at top conferences including DAC, ASP-DAC, and CODES+ISSS Dr. Hu's research has been supported by multiple grants focusing on energy-efficient computing, non-volatile memory systems, and hardware acceleration for machine learning. His collaborative work spans numerous institutions and involves interdisciplinary teams working at the intersection of computer architecture, embedded systems, and artificial intelligence. His publications show extensive collaboration with researchers at the University of Pittsburgh, particularly with Albert K. Jones and Yiyu Shi. His laboratory work focuses on implementing practical systems for energy harvesting powered devices, non-volatile processors, and hardware accelerators for machine learning applications. Current projects appear to emphasize sustainable AI processing at the edge, heterogeneous FPGA acceleration, and personalized federated learning for health monitoring applications.

Tulika MitraView profile

Professor

• Hardware-Software Co-design
• Real-Time Embedded Systems
• Energy-Efficient Computing
• +7 more

Professor Tulika Mitra is the Dean of the School of Computing and Vice Provost (Special Projects) at the National University of Singapore (NUS). She holds the Provost’s Chair Professor in the Department of Computer Science and has been instrumental in shaping academic policies and strategic initiatives at NUS since joining in 2001. PhD in Computer Science, Stony Brook University (2000) M.E. in Computer Science, Indian Institute of Science (1997) B.E. in Computer Science, Jadavpur University (1995) Her research focuses on hardware-software co-design for energy-efficient computing systems, particularly in real-time embedded systems, heterogeneous architectures, and AI accelerators. She leads major research programs such as the NRF Competitive Research Programme on Low-Power Edge Accelerators and the MOE Tier-3 Programme on Green AI , collaborating with industry leaders like ARM, AMD, and Meta. Her recent publications highlight innovations in CGRA optimization , sparse attention mechanisms , photonic-digital hybrid architectures , and low-power ML inference . These works often integrate compiler techniques, architectural design, and real-time constraints for edge computing applications. Scientific Awards : ESWEEK Test-of-Time Award (2022), ACM SIGDA Distinguished Service Award, IEEE CEDA Outstanding Service Recognition Award, Teaching Excellence Award (2006), and multiple best paper recognitions. Education Leadership : Spearheaded the Computer Engineering (CEG) Programme at NUS, a joint initiative between Engineering and Computing. As a mentor , she has supervised over 25 PhD students , many now in prominent academic or industrial roles. Her research group eCO Lab focuses on embedded computing challenges, while her grant collaborations include projects on 5G base stations, reconfigurable architectures, and IoT-optimized SoCs.

Oliver DiesselView profile

Associate Professor

• Reconfigurable Hardware
• Computer Architecture
• Digital Systems
• +6 more

Associate Professor Oliver Diessel is a faculty member at the University of New South Wales (UNSW) within the School of Computer Science and Engineering. He has been actively teaching and conducting research at UNSW since at least 2000, with teaching experience spanning various computer architecture and digital systems courses. Dr. Diessel completed his education at the University of Newcastle, Australia, earning a B.E. (Computer, Hons) and B.Math. in 1991, followed by a PhD in 1998. His academic career has focused on reconfigurable computing systems and computer architecture. His primary research interests center around the design, test, and implementation of digital systems in reconfigurable logic devices called Field-Programmable Gate Arrays (FPGAs). Specifically, he focuses on dynamically reconfigurable digital systems where circuits can be modified while the system is operational. His work aims to develop architectures, design methods, and tools that enhance the benefits and reduce the costs of reconfigurable systems. Current research projects include fault-tolerant FPGA-based systems for space applications and fine-grained accelerators for heterogeneous devices. Dr. Diessel has published extensively with 2 books, 1 book chapter, 16 journal articles, 67 conference papers, 1 edited conference proceedings, and 7 conference presentations to his credit. His publications reflect a strong emphasis on reconfigurable technology, computer architecture, and electronic design automation. As a supervisor, Dr. Diessel currently mentors two MPhil students: Tong Wu working on Runtime reconfiguration and Junning Fan working on Fault-tolerance of FPGA-based applications. He has previously supervised six students to completion. His supervision interests include reconfigurable technology and systems, electronic design automation, and computer architecture. Dr. Diessel is an active member of the professional community, serving on the Editorial Board of ACM Transactions on Reconfigurable Technology and Systems and as an IEEE Member. He has taught numerous courses including Configurable Systems (COMP4601), Computer Architecture (COMP3211, COMP4211), Digital Systems (COMP3222), and FPGA Implementation of Digital Systems using Verilog.

• Wireless Communications
• Coding Theory
• Quantum Information Processing
• +5 more

Olav Tirkkonen serves as a Full Professor in the Department of Communications and Networking at Aalto University, Finland, a position he has held since August 2006. He leads the Communication Theory research group, driving innovation in wireless communication systems. His academic journey includes a distinguished career spanning industry and academia, with significant contributions to 3G, 4G, and 5G technologies. His educational qualifications are: Doctor of Science (Ph.D.) in Theoretical Physics, Helsinki University of Technology, 1994 Master of Science (M.Sc.) in Theoretical Physics, Helsinki University of Technology, 1990 Professor Tirkkonen's research interests are centered on wireless communications, with a focus on physical layer processing, coding theory, and quantum information processing. His group explores advanced topics including 5G and beyond wireless networks (spectrum management, large-scale MIMO, ultra-reliable low-latency communication), network-level interference coordination, collaborative caching, machine learning applications for wireless channel geography, coding on manifolds, and quantum communication systems. This research bridges fundamental theory with practical implementation in next-generation wireless networks. Analysis of his recent publications (2024-2025) indicates a predominant focus on machine learning techniques for wireless channel modeling (channel charting), pilot allocation in MIMO systems, and quantum error correction. His work is instrumental in addressing key challenges in 5G/6G networks, particularly in scenarios demanding ultra-reliability, low latency, and efficient resource utilization. His scientific contributions include: Co-inventor of approximately 80 families of patents and patent applications Co-author of the book "Multiantenna transceiver techniques for 3G and beyond" Throughout his career, Professor Tirkkonen has mentored numerous graduate students and secured substantial research funding from various sources. His industry experience at Nokia Research Center (1999-2010) and visiting position at Cornell University (2016-2017) have enriched his research perspective and fostered strong industry-academia collaborations. The Communication Theory group, under his leadership, maintains active collaborations with leading institutions and companies worldwide, positioning Aalto University at the forefront of wireless communications research.

Debjit PalView profile

Research Fellow

• Machine Learning for Electronic Design Automation (EDA)
• System-on-Chip (SoC) Verification
• Hardware Verification
• +6 more

Debjit Pal is a Post-Doctoral Associate at the School of Electrical and Computer Engineering, Cornell University, and a member of the Computer Systems Laboratory. His research focuses on machine learning techniques for hardware verification, SoC validation, and FPGA optimization. Education: Ph.D. in Computer Engineering (University of Illinois at Urbana-Champaign, 2019) M.S. in Computer Science (IIT Kharagpur, 2012) B.E. in Electronics Engineering (Jadavpur University, 2008) Research Interests: Machine Learning for Electronic Design Automation (EDA) System-on-Chip (SoC) Verification Edge Intelligence as a Service Compiler Optimizations for Reconfigurable and High-Performance Computing Scientific Awards: IEEE CEDA Student Research Award (2016) Best Paper Nomination (ICCAD 2015, DAC 2018, ASP-DAC 2019) E. J. McCluskey Best Doctoral Thesis Competition Semi-Finalist (2020) Travel Grants for ICCAD/DAC/ASPDAC (2018-2019) Professional Roles: Technical Program Committee Member (DAC, VLSID), Reviewer (IEEE TVLSI, DATE, ICCAD). Collaborates with researchers like Zhiru Zhang and Shobha Vasudevan.