Find Academic Supervisors

Brandon M. LuciaView profile

Professor

• Computer Architecture
• Computer Systems
• Programming Languages
• +7 more

Brandon M. Lucia is the Kavčić-Moura Professor of Electrical and Computer Engineering at Carnegie Mellon University and CEO/co-founder of Efficient Computer Company. He leads the Abstract research group and focuses his work on the intersection of computer architecture, systems, and programming languages. Education: Ph.D. in Computer Science and Engineering, University of Washington (2013) — advised by Luis Ceze Research Focus: Brandon's research is broadly centered on intermittent computing , edge computing , and energy-efficient architectures . Two major thrusts define his current work: Intermittent Computing: Making battery-free, energy-harvesting devices programmable and reliable despite frequent power failures. Applications include medical implants, space systems, and large-scale sensing. Orbital Edge Computing: Designing nanosatellite constellations that perform on-orbit data processing, enabling low-latency, high-resolution sensing in space-constrained environments. Scientific Awards: NSF CAREER Award (2017) IEEE TCCA Young Computer Architect Award (2019) Sloan Foundation Fellowship (2021) ASPLOS 2020 Best Paper Award OOPSLA 2015 Distinguished Paper & Artifact Awards IEEE Micro Top Picks (2016, 2018 Honorable Mention) Advising & Grants: Brandon actively advises a strong cohort of Ph.D. students including Zhuo Cheng, Bradley Denby, Souradip Ghosh, Harsh Desai, Kiwan Maeng, Emily Ruppel, and others. His group is funded by the NSF (CAREER and SHF grants), the Sloan Foundation, and industry partnerships. Labs & Teams: He directs the Abstract research group at CMU ECE, which hosts interdisciplinary projects spanning hardware design, compiler construction, and system software for ultra-low-power and space-borne computing platforms.

Shweta ShindeView profile

Assistant Professor

• Trusted Computing
• System Security
• Hardware Security
• +4 more

Shweta Shinde is an Assistant Professor in the Department of Computer Science at ETH Zurich where she leads the Secure & Trustworthy Systems (SECTRS) research group. She is also a member of the Institute of Information Security and the ZISC Center at ETH Zurich. Her work bridges theoretical foundations with practical implementations in hardware and system security. Dr. Shinde's research focuses on the intersection of trusted computing, system security, and program analysis. Her group investigates both foundational aspects of security to protect phones, servers, and accelerators, as well as practical aspects of realizing these solutions through large-scale system building. Her work spans hardware security primitives, trusted execution environments, confidential computing, and secure system design across multiple platforms including mobile devices, cloud infrastructure, and blockchain systems. Her publication record demonstrates significant impact in the field, with numerous papers in top security venues including IEEE S&P, USENIX Security, CCS, and NDSS. Her research has uncovered critical vulnerabilities in major hardware security technologies like Intel SGX and AMD SEV-SNP while also proposing novel frameworks for building more secure systems. The work spans multiple domains including hardware security, cloud security, mobile security, and blockchain security, with a consistent thread of identifying and addressing fundamental security challenges in trusted computing. Among her notable achievements are multiple best paper awards including at SysTEX 2025 and nominations at DATE 2025, a Distinguished Paper Award at IEEE S&P 2024, and recognition as a Most Innovative Research Pwnie Award Nominee in 2024. Her work on WeSee received particular attention for breaking AMD SEV-SNP through novel interrupt-based attacks. Dr. Shinde actively mentors PhD students including Mark Kuhne, Supraja Sridhara, Mélisande Zonta-Roudes, Benedict Schlüter, Andrin Bertschi, and others. She teaches courses on Systems Security, Information Security Lab, Seminar on Systems Security, and Current Topics in Information Security at ETH Zurich. Her service to the community includes extensive program committee work for major security conferences including Oakland (S&P), NDSS, USENIX Security, and CCS, where she has served as track co-chair and program co-chair for several workshops.

Hyesoon KimView profile

Professor

• Computer Architecture
• GPU
• Compilers and Runtime Systems
• +3 more

Hyesoon Kim is a Professor at the Georgia Institute of Technology , affiliated with the College of Computing and leading the HPArch research group . She co-directs the Center for Research into Novel Computing Hierarchies (CRNCH) . Her research focuses on Computer Architecture , GPU , Compilers and Runtime Systems , and Hardware Security , particularly for heterogeneous systems. Contact : hyesoon@cc.gatech.edu Location : 266 Ferst Drive, KACB 2344, Atlanta, GA Research Trends Her recent work spans RISC-V extensions for security, CUDA optimization on softcore GPUs, memory safety techniques, and energy-efficient deep learning architectures. Articles emphasize heterogeneous computing , GPU performance scaling, and IoT -oriented neural network methods. Open Source Projects She leads development of Macsim (heterogeneous architecture simulator) and Vortex (open-source GPU platform).

Sarita V AdveView profile

Professor

• Computer Architecture
• Extended Reality Systems
• Heterogeneous Computing
• +4 more

Sarita V Adve is the Richard T. Cheng Professor of Computer Science at the University of Illinois at Urbana-Champaign, where she conducts research spanning hardware, programming languages, operating systems, and applications with a focus on domain-specific systems. Her work bridges theoretical foundations and practical implementations, particularly in extended reality and heterogeneous computing. Her educational background includes a Ph.D. and M.S. in Computer Science from the University of Wisconsin-Madison (1993, 1989) and a B.Tech in Electrical Engineering from the Indian Institute of Technology Bombay (1987). Prior to joining Illinois, she served on the faculty at Rice University from 1993 to 1999. Adve's research centers on generalizable and scalable specialization for domain-specific systems, with current emphasis on extended reality (XR) systems including virtual, augmented, and mixed reality. She chairs the ILLIXR consortium to democratize XR research and developed the first fully open-source XR system (ILLIXR). Her foundational contributions include memory consistency models for C++ and Java programming languages, the Spandex coherence framework for heterogeneous systems, and software-driven approaches for hardware reliability. Her work spans hardware reliability (SWAT and RAMP projects), power management (GRACE system), and instruction-level parallelism. Recent publications reveal a strong focus on energy-efficient XR systems, hardware-software co-design for AI workloads, and resilience analysis. Her team explores rendering offload, visual-inertial odometry optimization, and compositional error injection frameworks, often targeting tradeoffs between energy, latency, and accuracy in mobile and edge environments. Fellow of the American Academy of Arts and Sciences Fellow of the ACM and IEEE ACM/IEEE-CS Ken Kennedy Award Anita Borg Institute Woman of Vision in Innovation Award ACM SIGARCH Maurice Wilkes Award Alfred P. Sloan Research Fellowship UIUC University Scholar University of Illinois Campus Award for Excellence in Graduate Student Mentoring Adve actively mentors students and has received multiple teaching awards. She co-founded the CARES movement to address discrimination in CS research events and chairs CS@Illinois CARES. Her service includes leadership roles in ACM SIGARCH (2015-2019), DARPA/ISAT study group, ACM Council, and Computing Research Association. She has secured significant funding including DARPA initiatives and Google Faculty Research Awards. She leads the ILLIXR consortium and has established collaborative research programs such as the $8.3M DARPA Joint University Microelectronics Program. Her lab focuses on open-source XR development, heterogeneous system architectures, and reliability-aware designs, with strong industry and government partnerships.

Shweta ShindeView profile

Assistant Professor

• Trusted Computing
• System Security
• Program Analysis
• +4 more

Shweta Shinde is an Assistant Professor at ETH Zürich's Department of Computer Science. She leads the Secure & Trustworthy Systems (SECTRS) group and is affiliated with the Institute of Information Security and the ZISC Center. Her research focuses on foundational and practical aspects of trusted computing, system security, and program analysis to protect devices ranging from smartphones to cloud servers. Key areas include AMD SEV-SNP, Arm CCA, Intel SGX, and hardware-software co-design for security. Dr. Shinde has made significant contributions to confidential computing, including frameworks like OpenCCA and tools for analyzing hardware vulnerabilities. Her work has been recognized with Best Paper Awards and Distinguished Paper Awards at top venues. She advises a group of PhD students, including Mark Kuhne, Supraja Sridhara, and Benedict Schlüter. Her service includes program committee roles at IEEE Security & Privacy, USENIX Security, and as Track Co-Chair for AsiaCCS 2026.

• Computer Engineering
• Circuit Design
• Fault Tolerance
• +6 more

Matteo Sonza Reorda is a Full Professor at the Polytechnic University of Turin, affiliated with the Department of Automatic Control and Computer Science (DAUIN). He holds roles such as Partnership Agreement Coordinator with SMAT and has served as Vice-Rector for Research (2021–2024). His research focuses on fault tolerance, hardware reliability, and AI acceleration, with contributions to GPU/CNN reliability, self-test libraries, and defect-oriented testing. Education: M.S. in Electronics Engineering, Politecnico di Torino (1986) Ph.D. in Computer Engineering, Politecnico di Torino (1990) Research Interests: His work spans automatic test equipment, circuit reliability, GPU fault tolerance, neural network hardening, and embedded systems safety . He leads the Electronic CAD & Reliability Group and collaborates with institutions like the ISI Foundation and the National Research Council (CNR). Publications & Impact: With over 180 publications, his recent work emphasizes AI accelerator reliability, fault injection techniques, and safety-critical systems. Key trends include GPU resilience for CNNs, self-test library optimization, and radiation fault modeling in neural networks. Awards & Recognition: IEEE Fellow (2016–) Multiple best-paper awards at IEEE conferences (DDECS, DATE, etc.) Grants & Collaborations: Coordinator of EU projects (RESCUE, TUTORIAL) Partnerships with EDF, Marelli Europe, and SMAT Lead on National HPC/Quantum Computing Spoke 1 (2022–2025) Labs/Teams: Leads the CAD Group and collaborates with the French-Italian LIA LAFISI lab on hardware-software integration.

Manoj SachdevView profile

Professor

• Semiconductor Devices
• Low-Power Electronics
• VLSI Design
• +7 more

Manoj Sachdev is a Professor in the Department of Electrical and Computer Engineering at the University of Waterloo, Faculty of Engineering. His research focuses on semiconductor devices, low-power electronics, and secure hardware systems. He leads projects in flexible electronics, nanotechnology, and radiation-hardened circuits, with applications in displays, memory technologies, and biomedical sensors. His work integrates advanced materials science with circuit design to address challenges in energy efficiency and security. Education: Not explicitly stated in provided text. Research interests span thin-film transistors (TFTs), resistive switching memories, neuromorphic computing, and physically unclonable functions (PUFs). Recent efforts include developing low-power circuits for flexible substrates and secure microprocessors. His contributions to semiconductor device physics and integration techniques have advanced applications in wearable electronics and medical diagnostics. Publications highlight innovations in low-power flip-flops, energy-efficient display drivers, and memristor-based systems. He collaborates on interdisciplinary projects combining photonics, nanoelectronics, and biomedical engineering. Awards: None explicitly listed in provided text. Grants and advising: Advises on semiconductor fabrication, secure hardware design, and radiation effects in electronics. Leads research groups focused on next-generation memory technologies and flexible integrated systems. Labs/Teams: Active in the University of Waterloo's semiconductor and flexible electronics research clusters, contributing to both academic and industry partnerships.

Baker MohammadView profile

Professor

• Very-Large-Scale Integration (VLSI)
• Hardware Accelerators for Artificial Intelligence
• Hardware Security
• +7 more

Prof. Baker Mohammad serves as Professor and Director of the System on Chip Lab in the Department of Computer and Information Engineering at Khalifa University. With over 15 years of industrial experience at Intel and Qualcomm designing microprocessors and DSP chips, he bridges academic research with real-world engineering challenges in high-performance computing and low-power systems. His educational background includes: Ph.D. in Electrical and Computer Engineering, University of Texas at Austin (2008) M.S. in Electrical and Computer Engineering, Arizona State University B.S. in Electrical Engineering, University of New Mexico Dr. Mohammad's research spans cutting-edge domains where VLSI design converges with AI acceleration and emerging memory technologies . His work pioneers Memristor applications in environmental sensing (radiation, vacuum, glucose) and neuromorphic computing, while advancing energy harvesting systems for wearable electronics. The integration of in-memory computing with security primitives represents a paradigm shift in hardware design, moving beyond traditional CMOS limitations. His publication trajectory reveals accelerating focus on self-powered neuromorphic systems and RRAM-based architectures, with recent work (2021-2023) emphasizing hardware-software co-design for edge AI. Over 75% of his recent publications involve cross-disciplinary collaborations spanning materials science, chemistry, and biomedical engineering. Notable scientific recognition includes: IEEE TVLSI Best Paper Award 2016 IEEE MWSCAS Myrill B. Reed Best Paper Award Qualcomm Qstar Award for Performance Leadership KUSTAR IP Excellence Award Multiple SRC Techon Best Session Papers As a dedicated mentor, he has supervised over 15 graduate students while securing competitive funding from Khalifa University, ADEK, Qualcomm, Tii, and UAE space agencies. His grant portfolio demonstrates exceptional translational impact, converting fundamental research in memristive devices into drone flight computers and medical sensors. Current projects integrate academic rigor with industrial deployment timelines. The System on Chip Lab operates as a multidisciplinary hub where semiconductor physicists collaborate with AI researchers to develop RISC-V-based secure processors and piezoelectric nanogenerator systems. Recent expansions include partnerships with Tii for aerospace applications and medical device startups for glucose monitoring technology.

Ozcan OzturkView profile

Professor

• Heterogeneous Computing
• Hardware Accelerators
• GPU Computing
• +7 more

Ozcan Ozturk is a Professor in the Computer Science and Engineering and Electronics Engineering programs at Sabancı University's Faculty of Engineering and Natural Sciences. Previously, he held professorships at Bilkent University and adjunct roles at North Carolina State University. His expertise spans heterogeneous computing, parallel systems, processor architecture, and compiler optimization. He earned his Ph.D. from Penn State University, with prior academic roles at the University of Florida and internships at Intel and Marvell. Education: Ph.D. in Computer Science and Engineering (2007), Pennsylvania State University M.S. in Computer Engineering (2002), University of Florida B.Sc. in Computer Engineering (2000), Bogazici University Research interests include accelerator technologies, GPU-based systems, multicore processors, and compiler optimizations. His work focuses on improving parallelization efficiency, energy optimization, and reliability in heterogeneous architectures. He leads funded projects like 'Machine Learning for Compiler Flags' and 'Graph Accelerator Design'. Notable awards include the Bilkent Teaching Award (2019), BAGEP (2018), and HiPEAC Paper Award (2016). He serves on editorial boards of IEEE and ACM journals and chairs major conferences like ASPLOS and ICS. Grants and collaborations include partnerships with Huawei, Intel, NVIDIA, and TÜBİTAK. He advises over 20 students and has supervised projects in safety-critical systems, FPGA accelerators, and compiler-directed optimizations. His lab develops domain-specific architectures, including RISC-V extensions for graph processing.

Tosiron AdegbijaView profile

Associate Professor

• Computer Architecture
• Embedded Systems Design
• Low-Power Embedded Systems
• +14 more

Tosiron Adegbija is an Associate Professor in the Department of Electrical and Computer Engineering at the University of Arizona, where he serves as Director of Graduate Studies and Thomas R. Brown Endowed Fellow. He is a member of the Graduate Faculty and actively contributes to research and teaching in computer architecture and embedded systems. Education: PhD in Electrical and Computer Engineering, University of Florida, 2015 MS in Electrical and Computer Engineering, University of Florida, 2011 BS in Electrical Engineering, University of Ilorin, Nigeria, 2005 His research centers on energy-efficient computing with a focus on bio-inspired computer architecture , including spiking neural network (SNN) accelerators and in-memory computing. He also explores domain-specific architectures , adaptable memory systems , and microprocessor optimizations for IoT . His work leverages novel memory technologies like STT-RAM to enhance performance and reduce energy consumption in embedded and resource-constrained systems. Recent publications highlight trends in hybrid SNN acceleration, domain-specific accelerator generation, and system-level design space exploration. His research is increasingly focused on neuromorphic computing, automated hardware design, and ultra-efficient architectures using emerging materials like antiferromagnetic tunnel junctions. Scientific Awards: National Science Foundation (NSF) CAREER Award (2019) Elected IEEE Senior Member (2020) Best Paper Award at IEEE ISVLSI (2014) Teaching Award, University of Arizona (2018) ACM GLSVLSI Travel Award (2015) He advises numerous graduate and undergraduate students, many of whom have pursued careers at institutions like Pacific Northwest National Labs, Micron Technology, and Amazon. He has secured significant funding, including a $1.9M NSF FuSE2 grant for energy-efficient computing. His lab collaborates with UA Physics, CMU, and UNL. He has also developed educational tools for Chipyard and RISC-V, supporting hands-on learning in computer architecture. Labs and Research Teams: Leads a research group focused on bio-inspired and domain-specific computing, fostering innovation in energy-efficient hardware. The lab emphasizes hardware/software co-design, neuromorphic engineering, and real-world deployment in IoT and biomedical applications.

Brandon LuciaView profile

Professor

• computer architecture
• computer systems
• programming languages
• +8 more

Brandon Lucia is a Professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University's College of Engineering. He holds the Kavčić-Moura Professorship and leads the Abstract research group. As CEO and co-founder of Efficient Computer Corp., he bridges academic research with commercial applications in energy-efficient computing. Dr. Lucia received his Ph.D. in Computer Science and Engineering from the University of Washington in 2013, following an MS from the same institution in 2010 and a BS in Computer Science from Tufts University in 2007. His research focuses on the intersection of computer architecture, computer systems, and programming languages, particularly in energy-constrained environments. His primary research interests include intermittent computing, energy harvesting computers, orbital edge computing, and parallel computing systems. Lucia's work addresses fundamental challenges in creating programmable, reliable computing devices that operate without batteries by harvesting energy from their environments, with applications in sensing, medical implants, and space systems. He also investigates software systems and architectures for making parallel computing correct, reliable, and efficient in the post-Moore's Law era. Lucia's publication record shows a clear trajectory toward orbital edge computing and nanosatellite systems, with recent work focusing on computational constellations, visual navigation for satellites, and energy-efficient processing in space. His research spans both theoretical foundations of intermittent computing and practical implementations in hardware and software. 2021 Sloan Research Fellowship 2018 NSF CAREER Award 2018 ASPLOS Best Paper Award IEEE MICRO Top Picks in Computer Architecture (2009, 2010, 2016) 2015 OOPSLA Best Paper Award 2019 IEEE TCCA Young Computer Architect Award 2022 Engineering Faculty Award As an advisor, Lucia has mentored numerous graduate students including Brad Denby, Zhuo Cheng, and Kyle McCleary, many of whom have become co-authors on his significant publications. His lab developed the world's first batteryless PocketQube nanosatellite (Tartan-Artibeus-1), which was deployed to low-Earth orbit aboard the SpaceX Transporter-3 Rocket. Lucia's research has received funding from sources including NSF, DARPA, Google, and VMware, supporting both fundamental research and practical implementations of energy-harvesting computing systems.

Jing LiView profile

Associate Professor

• Computer Architecture
• Compiler Design
• Distributed Systems
• +7 more

Dr. Jing Li is an Associate Professor and Eduardo D. Glandt Faculty Fellow at the University of Pennsylvania , holding dual appointments in the Electrical and Systems Engineering and Computer and Information Science departments. As co-director of the CyberSavvy nationwide security research center and director of the Penn Computational Intelligence Lab (PennCIL) , she pioneers innovations in non-von Neumann computing paradigms. Her research spans post-CMOS technologies, in-memory computing, and hardware-software co-design for security and AI applications. PhD in Computer Engineering, Purdue University (2009) BSc in Electrical Engineering, Shanghai Jiaotong University (2004) Research Focus: Dr. Li's work addresses fundamental challenges in computer systems across the stack. Key areas include: In-Memory Computing: Liquid Silicon architecture combining RRAM with silicon CMOS through monolithic 3D integration Security Engineering: Transforming computer security from "Art" to formal "Engineering" discipline within CyberSavvy Virtualization: Cloud FPGA abstraction layers decoupling compilation from runtime resource management Graph Analytics: Degree-aware optimization techniques for massive-scale graph processing Deep Learning Systems: Roofline model extensions for FPGA-based CNN acceleration Scientific Impact: Awarded DARPA Young Faculty Award , NSF CAREER Award , and IBM CEO Milestone Award , her team has achieved world records in energy-efficient computing (ENIAD supercomputer). With 46 U.S. patents and over 80 publications, she leads ecosystem development for emerging computing architectures through initiatives like the open-source MEG simulation platform . Community Leadership: Dr. Li serves on program committees for flagship conferences ( ISCA , FPGA Symposium ), chairs the International Memory Workshop , and contributes to the MLsys conference's inaugural committee. She actively mentors through multiple PhD openings and industry collaborations.

• High-Performance Computing
• Reconfigurable Computing
• FPGA Acceleration
• +7 more

Carlos Alvarez Martinez is a faculty member at the Universitat Politècnica de Catalunya (UPC), affiliated with the Department of Computer Architecture at the Barcelona School of Informatics (FIB). He is a key member of the Programming Models (PM) research group and collaborates closely with the Barcelona Supercomputing Center (BSC). His research focuses on high-performance computing, FPGA acceleration, task-based programming models like OmpSs, and hardware-software co-design for heterogeneous systems. His research interests center on advancing parallel computing through innovative programming models and hardware acceleration. He investigates efficient task scheduling, resource management in multicore and FPGA-based systems, and runtime support for dataflow models. His work enables high-performance execution of complex applications in domains such as scientific computing and cyber-physical systems. He actively contributes to European initiatives like TEXTAROSSA and AXIOM, aiming to develop next-generation exascale supercomputing technologies. The trend in his recent publications shows a strong focus on leveraging FPGAs for HPC, optimizing SpMV operations, improving task scheduling with hardware support, and developing frameworks for multi-FPGA clusters. His work consistently bridges theoretical models with practical implementations, emphasizing performance, scalability, and energy efficiency in heterogeneous computing environments. Scientific Awards: Premi UPC al Compromís Social 2019 Premi Disseny per al Reciclatge 2013 Alvarez Martinez has advised or collaborated with several doctoral students, including Jaume Bosch, Xubin Tan, and Fahimeh Yazdanpanah. He has been involved in numerous competitive R&D projects, often related to high-performance computing and parallel programming models. His work includes significant contributions to educational innovation, particularly in active learning methodologies and formative assessment using interactive systems. He leads and participates in research labs and teams focused on programming models and computer architecture, notably the PM group at UPC/BSC. These teams develop runtime systems, compilers, and hardware accelerators to push the boundaries of parallel computing efficiency and programmability.

Dimitris GizopoulosView profile

Professor

• Computer Architecture
• Computer Systems
• Fault Tolerance
• +5 more

Prof. Dimitris Gizopoulos is a Professor at the Department of Informatics & Telecommunications, University of Athens, leading the Computer Architecture Laboratory. His research focuses on fault tolerance, design validation, performance, and energy efficiency in microprocessors, GPUs, and AI accelerators. He is an IEEE Fellow (2013) and ACM Distinguished Member (2022). His work is supported by Horizon Europe projects like DARE, Neuropuls, and Vitamin-V, alongside industry grants from AMD, Cisco, and Meta. He participates in networks like HiPEAC and Eurolab4HPC and serves on editorial boards of journals including ACM Computing Surveys and IEEE Transactions on Computers . Prof. Gizopoulos teaches Computer Architecture courses at both undergraduate and graduate levels. His research spans cross-layer reliability analysis, voltage scaling effects, and secure hardware design. Notable contributions include frameworks for GPU reliability assessment (GUFI, GPUI-4) and tools like MerLIN for microarchitecture-level analysis. His lab’s work has been funded by the EuroHPC Joint Undertaking and the Greek-China Research Collaboration program. Key Projects: DARE (RISC-V Europe), Neuropuls (neuromorphic accelerators), Vitamin-V (RISC-V cloud environments). Awards: IEEE Fellow (2013), ACM Distinguished Member (2022), IEEE Golden Core (since 2002). Industry Partnerships: AMD, Cisco, Bosch, NVIDIA, Intel, IBM Research. Labs: Leads the Computer Architecture Lab, focusing on fault tolerance and energy-efficient computing. His work emphasizes bridging hardware-software co-design challenges, with publications in top venues like IEEE Transactions on Computers and ACM Computing Surveys . Recent efforts include analyzing silent data corruptions (SDCs) in CPUs and GPUs, and developing validation frameworks for cloud-native architectures.

• Computer Engineering
• Embedded Systems
• Fault Tolerance
• +4 more

Corrado De Sio is a Fixed-term Researcher at the Department of Control and Computer Science (DAUIN) , Politecnico di Torino , affiliated with the College of Computer, Film, and Mechatronics Engineering . His academic roles include course instruction and collaboration for Reconfigurable Computing , High Performance Computing (HPC) , and Operating Systems for High-Performance Supercomputers across multiple academic years (2020-2025). Research Interests focus on: Reliability of reconfigurable systems and FPGAs under radiation effects Hardware-software co-design for fault tolerance Embedded systems in aerospace and safety-critical applications Machine learning acceleration on reconfigurable hardware Radiation effects on real-time operating systems and CNN implementations Recent publications address: 2025: Selective hardening of RISCV soft-processors for space applications 2025: Real-time 'signal for help' gesture recognition systems 2024: Reliability analysis of RISC-V processors and CNN placement algorithms 2023: Fault tolerance in FPGA-based CNNs and radiation effects on RTOS Patents include: PyXEL - Python Toolkit for Reconfigurable Hardware Surveillance Software for Real-Time Violence Detection Academic Supervision : Co-supervisor for PhD candidate Arash Amini Bardpareh in Computer and Systems Engineering .