Shweta Shinde is an Assistant Professor at ETH Zürich's Department of Computer Science. She leads the Secure & Trustworthy Systems (SECTRS) group and is affiliated with the Institute of Information Security and the ZISC Center. Her research focuses on foundational and practical aspects of trusted computing, system security, and program analysis to protect devices ranging from smartphones to cloud servers. Key areas include AMD SEV-SNP, Arm CCA, Intel SGX, and hardware-software co-design for security. Dr. Shinde has made significant contributions to confidential computing, including frameworks like OpenCCA and tools for analyzing hardware vulnerabilities. Her work has been recognized with Best Paper Awards and Distinguished Paper Awards at top venues. She advises a group of PhD students, including Mark Kuhne, Supraja Sridhara, and Benedict Schlüter. Her service includes program committee roles at IEEE Security & Privacy, USENIX Security, and as Track Co-Chair for AsiaCCS 2026.
Dr. Jing Li is an Associate Professor and Eduardo D. Glandt Faculty Fellow at the University of Pennsylvania , holding dual appointments in the Electrical and Systems Engineering and Computer and Information Science departments. As co-director of the CyberSavvy nationwide security research center and director of the Penn Computational Intelligence Lab (PennCIL) , she pioneers innovations in non-von Neumann computing paradigms. Her research spans post-CMOS technologies, in-memory computing, and hardware-software co-design for security and AI applications. PhD in Computer Engineering, Purdue University (2009) BSc in Electrical Engineering, Shanghai Jiaotong University (2004) Research Focus: Dr. Li's work addresses fundamental challenges in computer systems across the stack. Key areas include: In-Memory Computing: Liquid Silicon architecture combining RRAM with silicon CMOS through monolithic 3D integration Security Engineering: Transforming computer security from "Art" to formal "Engineering" discipline within CyberSavvy Virtualization: Cloud FPGA abstraction layers decoupling compilation from runtime resource management Graph Analytics: Degree-aware optimization techniques for massive-scale graph processing Deep Learning Systems: Roofline model extensions for FPGA-based CNN acceleration Scientific Impact: Awarded DARPA Young Faculty Award , NSF CAREER Award , and IBM CEO Milestone Award , her team has achieved world records in energy-efficient computing (ENIAD supercomputer). With 46 U.S. patents and over 80 publications, she leads ecosystem development for emerging computing architectures through initiatives like the open-source MEG simulation platform . Community Leadership: Dr. Li serves on program committees for flagship conferences ( ISCA , FPGA Symposium ), chairs the International Memory Workshop , and contributes to the MLsys conference's inaugural committee. She actively mentors through multiple PhD openings and industry collaborations.
Austin Rovinski is an Assistant Professor in the Department of Electrical and Computer Engineering at New York University’s Tandon School of Engineering. He specializes in chip design, electronic design automation (EDA), and open-source hardware methodologies. His research focuses on VLSI design, domain-specific accelerators, and chiplet-based systems. Prior to NYU, he held a postdoctoral position at Cornell University and earned all his degrees (Ph.D., M.S., and B.S.) from the University of Michigan. Education: Ph.D., Electrical Engineering, University of Michigan - Ann Arbor Master’s, Electrical Engineering, University of Michigan - Ann Arbor Bachelor’s, Electrical Engineering, University of Michigan - Ann Arbor Research Focus: Developing open-source EDA frameworks like OpenROAD Optoelectronic interconnect systems for 2.5D packaging Agile hardware design methodologies Reconfigurable sparse matrix accelerators RISC-V-based manycore processors (e.g., Celerity project) Key Contributions: Austin led the development of the OpenROAD RTL-to-GDS flow and contributed to the Sirius and Celerity projects. His work emphasizes reproducibility, democratizing chip design through open-source tools. Awards: IEEE Micro Top Picks (2015) Michigan EECS Outstanding Research Award (2016) NSF Graduate Research Fellowship Honorable Mention (2017, 2018) Advising & Grants: Actively mentors graduate students in chip design and EDA. His research is supported by NYU’s Tandon School of Engineering and collaborations with industry partners. Labs & Teams: Core contributor to the OpenROAD project, part of NYU’s hardware design and EDA initiatives, and collaborator on the Celerity manycore processor project.
Luca Carloni is a Professor of Computer Science and Department Chair at Columbia University's Columbia Engineering. He leads the System-Level Design Group, focusing on heterogeneous system-on-chip (SoC) architectures, networks-on-chip (NoC), and embedded systems. Carloni holds a Laurea Summa Cum Laude in Electronics Engineering from the University of Bologna and a PhD in Electrical Engineering and Computer Sciences from UC Berkeley. His work emphasizes specialized hardware design, energy-efficient computing, and FPGA-based prototyping. Research interests include system-level design methodologies for SoCs, embedded accelerators, and quantum computing hardware. He has pioneered frameworks like Embedded Scalable Platforms (ESP) and tools like MosaicSim for rapid SoC prototyping. Carloni has received numerous awards, including the NSF CAREER Award (2006), IEEE Fellow (2017), and multiple best paper awards at DATE and CloudCom conferences. He has served on editorial boards of IEEE Transactions on CAD and ACM Transactions on Embedded Computing , and chaired key conferences like EMSOFT and ESWeek. His research addresses challenges in heterogeneous architectures, power management, and the intersection of machine learning with embedded systems. Current projects explore quantum control systems, brain-computer interfaces, and energy-efficient datacenter computing.
David Wentzlaff is a Professor of Electrical and Computer Engineering at Princeton University, with associated faculty roles in Computer Science and the High Meadows Environmental Institute (HMEI). He leads research in computing architecture, green computing, and sustainable system design. As Director of Undergraduate Studies, he shapes educational programs in his field. Education: Ph.D., Electrical Engineering, MIT (2012) M.S., Electrical Engineering and Computer Science, MIT (2002) B.S., Electrical Engineering, University of Illinois at Urbana-Champaign (2000) Research Focus: Future Computing Systems: Designing manycore architectures, cloud computing infrastructure, and chiplet-based systems for exascale computing. Sustainability: Developing energy-efficient hardware, recyclable computing systems, and eco-friendly decommissioning strategies. Hardware-Software Co-Design: Exploring FPGA integration, in-memory computing, and parallel processing frameworks. Advising & Grants: Advises 8 current graduate students, focusing on topics like chiplet design, neural acceleration, and sustainable computing. Recipient of NSF grants for projects like OpenPiton (open-source manycore research platform) and CAREER awards for energy-efficient architectures. Labs & Collaborations: Leads the Wentzlaff Research Group at Princeton. Develops open-source frameworks like PRGA (FPGA prototyping) and OpenPiton (manycore processor).
Dr Graeme Bragg is a Senior Teaching Fellow at the University of Southampton within the Department of Electronics and Computer Science . His work spans teaching, research, and technical development with a focus on event-driven computing, bioinformatics, and computational modeling. He actively supervises PhD students and collaborates on interdisciplinary projects. Research Interests: Parallel computing, event-driven systems, genotype imputation, Petri net simulations, subglacial hydrology modeling Teaching: Specializes in hardware description languages and computational methods for engineering students Technical Expertise: RISC-V architecture, FPGA acceleration, bespoke compute fabric development His recent publications demonstrate expertise in applying event-driven computing to diverse problems including: 2025: Automated marking systems for SystemVerilog labs 2025: Seasonal dynamics in subglacial hydrology 2023: Genotype imputation using custom hardware 2022: Optimization algorithms and graph analysis Current research explores: Custom RISC-V FPGA clusters for bioinformatics Event-triggered systems for scientific simulations Parallel computing solutions for molecular modeling Contact: gmb@ecs.soton.ac.uk | +44 23 8059 2784
Professor Klaus McDonald-Maier is a full Professor in the School of Computer Science and Electronic Engineering (CSEE) at the University of Essex , where he leads the Embedded and Intelligent Systems (EIS) Research Laboratory and heads the Intelligent Embedded Systems and Environments Research Group . He is also Director of Impact , Visiting Professor at the University of Kent, and Visiting Research Affiliate at NASA Jet Propulsion Laboratory, California Institute of Technology. Education PhD in High-Performance Parallel Neural Network Architectures, Friedrich-Schiller-University Jena (Germany, 1999) Electronic Engineering studies, University of Ulm (Germany) Electronic Engineering studies, Cardiff University (Wales) Electronic Engineering studies, École Supérieur de Chimie Physique Électronique de Lyon (CPE-Lyon) (France) Research Interests Professor McDonald-Maier’s research integrates embedded systems , System-on-Chip (SoC) architectures , and AI-driven robotics . He pioneers visual place recognition techniques that remain robust under severe appearance and viewpoint changes, develops cybersecurity frameworks based on ICMetrics for autonomous vehicles and IoT, and designs approximate real-time computing solutions for energy-constrained multicore and FPGA platforms. His work on radiation-tolerant systems supports space and nuclear applications, while his bio-inspired algorithms enable lightweight, neuromorphic perception on resource-limited robots. Publication Trends Between 2022 and 2025 his output converges on FPGA-accelerated AI , secure edge intelligence , visual navigation for autonomous systems , and healthcare analytics . He repeatedly couples rigorous algorithmic innovation with practical hardware deployment, yielding energy-efficient, real-time systems validated in domains ranging from autonomous driving to post-stroke rehabilitation. Scientific Awards & Recognition Best Paper Award – IEEE Transactions on Sustainable Computing (2024) Best Paper Award – IEEE/ACM DATE (2024) Best Paper Award – IEEE Systems Journal (2022) Best Paper Award – IEEE Sensors Journal (2021) Best Paper Award – IEEE Access (2020) Research Grants & Industrial Collaboration He has secured major funding from EPSRC , EU Horizon 2020 , Innovate UK , and industry partners. Current projects span trustworthy autonomy, radiation-hardened edge AI, and AI-enhanced rehabilitation technologies. He is Chief Scientist of UltraSoC Technologies Ltd and CEO of Metrarc Ltd , commercialising University research in semiconductor debug and cybersecurity respectively. Laboratory & Team Leadership As Director of the Embedded and Intelligent Systems Laboratory (EIS Lab) , he oversees a multidisciplinary team of researchers and PhD students, providing state-of-the-art FPGA, robotics, and embedded-systems facilities. The lab collaborates closely with NASA JPL, UK Atomic Energy Authority, and leading semiconductor firms to translate fundamental research into high-impact industrial solutions.
Pablo Parra Espada is an Associate Professor at the Department of Automática, University of Alcalá (Spain), affiliated with the Space Research Group (SRG-UAH). He holds a PhD from the University of Alcalá (2012) titled Integración de tecnologías de desarrollo y análisis basadas en componentes bajo un enfoque multi-plataforma , supervised by Dr. Sebastián Sánchez Prieto and Dr. Óscar Rodríguez Polo. His research focuses on space systems engineering , particularly in RISC-V processor design , embedded systems , and model-driven engineering . Key areas include hardware-software co-design for satellite systems, real-time computing, and fault-tolerant architectures. He has contributed to the Solar Orbiter mission through work on the Energetic Particle Detector (EPD) and its on-board software validation. His recent work emphasizes virtualization techniques for LEON processors, FPGA-based digital beamforming , and spaceborne phased array systems . He also explores model-driven approaches for automated configuration of ground support equipment. His interdisciplinary contributions bridge computer architecture with aerospace applications. Prof. Parra Espada has published extensively on topics such as hardware performance monitoring, memory management units for satellites, and system-level verification of space software. His work combines rigorous engineering methodologies with cutting-edge technologies to address challenges in space instrumentation and embedded systems.
Pierre-Emmanuel Gaillardon is a Professor in the Department of Electrical & Computer Engineering and Adjunct Professor in the School of Computing at the University of Utah. He holds a joint appointment since July 2024, having previously served as Assistant Professor (2016–2019) and Adjunct Assistant Professor in Computing (2016–2019). His research focuses on FPGA design, VLSI systems, nanoelectronics, and hardware security. He leads projects in emerging devices like TIGFETs, compute-in-memory architectures, and radiation-hardened FPGA fabrics. Teaching includes courses on Digital VLSI Design, Embedded Systems Design, and thesis supervision. He has secured grants from NSF, DARPA, and industry partners totaling over $10M, addressing topics like FPGA redaction, neuromorphic systems, and environmental sensors. Notable awards include the NSF CAREER Award (2018) and IEEE Senior Member elevation (2016). He actively serves on IEEE committees for nanoelectronics and EDA tools, contributing to standards like OpenFPGA.
Prof. Dr.-Ing. Marc Reichenbach serves as the Chair of Integrated Systems at the Institute for Applied Microelectronics and Data Technology at the University of Rostock. His office is located at Albert-Einstein-Straße 26, 18059 Rostock, Room 102 (1st floor), with contact information including telephone (0381) 498 7270 and email marc.reichenbach@uni-rostock.de. Professor Reichenbach's research focuses on the intersection of hardware design and artificial intelligence, with particular expertise in memory technologies and computing architectures. His work spans several key areas: Development of specialized computer architectures for deep learning applications Advanced VLSI design and CPU architecture Emerging memory technologies, particularly RRAM (Resistive Random-Access Memory) FPGA-based acceleration systems Hardware implementations for neural networks and AI applications Analysis of Professor Reichenbach's recent publications (2023-2025) reveals a strong focus on memory computing technologies, particularly RRAM-based systems. His work demonstrates expertise across multiple dimensions of computer architecture including ASIC design, FPGA acceleration, and novel memory systems. The publications show a clear trajectory toward implementing AI and machine learning capabilities directly in hardware, with applications ranging from edge computing to satellite systems. A significant portion of his recent work addresses the challenges of implementing neural networks using emerging memory technologies, focusing on efficiency, reliability, and performance optimization. Professor Reichenbach teaches several advanced courses including: Computer architectures for deep learning applications Project seminar Embedded Systems Advanced VLSI Design (Advanced CPU Design) His research group appears to be actively engaged in several cutting-edge projects related to hardware acceleration for AI applications, memory computing, and embedded systems design. The group collaborates on projects involving digital twins for hardware systems, real-time operating systems for heterogeneous architectures, and specialized computing systems for various applications from medical devices to drone technology.
Roberto Giorgi is an Associate Professor of Computer Engineering at the Department of Information Engineering, University of Siena, Italy. He has held this position since October 1, 2006, following his tenure as an Assistant Professor since March 15, 1999. His educational background includes a Ph.D. in Computer Engineering from the University of Pisa (1999) with a thesis on coherence protocols for shared-memory multiprocessors, and an Electronic Engineering degree (1995) with a thesis on trace-driven performance evaluation of multiprocessors. Giorgi's primary research focuses on Computer Architecture , particularly on multiprocessor/multicore issues including processor design, coherence protocols, programmability, and energy efficiency. His work spans both theoretical and practical aspects of computer architecture, with emphasis on real-world implementations and educational tools. He has coordinated significant EU-funded projects including AXIOM (2014-2018) on Smart Cyber-Physical Systems and TERAFLUX (2009-2014) on Many-Cores. His recent publications (2022-2025) demonstrate a strong progression toward practical applications of computer architecture research, with particular emphasis on RISC-V architecture, FPGA-based acceleration, dataflow computing models (especially DF-Threads), and graph processing. Many of his papers address educational tools for computer architecture education, real-time object detection on embedded platforms, and novel execution paradigms for edge computing and HPC. IEEE Senior Member ACM Lifetime Member Coordinator of EU-funded AXIOM project (2014-2018) on Smart Cyber-Physical Systems Coordinator of EU-funded TERAFLUX project (2009-2014) on Many-Cores Giorgi has been actively involved in securing research funding and building collaborations, particularly in high-performance computer architecture research with emphasis on scalable architectures and embedded systems. He leads the Computer Architecture Lab (ROOM 223) at the University of Siena, which was established in 2007, and has been instrumental in developing practical implementations of architectural concepts including the AXIOM platform for cyber-physical systems.
Sarah Azimi is a fixed-term researcher at the Department of Control and Computer Science (DAUIN) within the College of Computer, Film and Mechatronics Engineering at Politecnico di Torino. She actively contributes to research and teaching in the domains of reliable computing, reconfigurable systems, and AI applications for space and smart city security. Research Interests: Reliability and fault tolerance in safety-critical and space systems RISC-V and FPGA-based architectures High-performance computing (HPC) and reconfigurable computing AI resilience and real-time gesture recognition for public safety Radiation effects and hardening techniques for aerospace applications Publication Trends: Her recent publications focus on RISC-V reliability, radiation effects in space missions, AI resilience in reconfigurable platforms, and smart city security through gesture recognition. Her work spans both journal and conference venues, emphasizing practical and mission-tailored solutions in embedded and aerospace computing. Scientific Awards: No awards explicitly mentioned in the provided text. Advising and Grants: Sarah Azimi supervises multiple PhD students including Federico Buccellato, Aobo Cui, and Giorgio Cora. She leads the competitive research project Safe Smart City: Detecting Violence and Requests for Help in Real Time Through Video Surveillance Devices (2024). She is also a member of the RAMSES CubeSat-1 Development project (2025–2026) and led the commercial research project on the Rempro fault-tolerant processor (2022–2023). Labs and Teams: She is a key member of the CAD - Electronic CAD & Reliability Group (DAUIN) at Politecnico di Torino, contributing to cutting-edge research in electronic design automation and system reliability for aerospace and terrestrial applications.
Tanvir Arafin serves as an Assistant Professor in the Department of Cyber Security Engineering at George Mason University, where his research focuses on hardware security and trust mechanisms for emerging computing platforms. With publications in premier venues including IEEE Transactions on Very Large Scale Integration Systems, IEEE Transactions on Computers, and ACM International Conference on Computer-Aided Design, he addresses critical security challenges in next-generation systems through rigorous hardware-software co-design approaches. His research portfolio spans Hardware Security, Trusted Computing, and IoT Security, with specialized expertise in Side-Channel Attacks and Secure Hardware Design. Dr. Arafin investigates electromagnetic side-channel vulnerabilities in O-RAN networks, develops countermeasures for autonomous vehicle cybersecurity, and pioneers RRAM-based security solutions for memory-constrained devices. His work bridges theoretical security models with practical implementations, emphasizing real-world applicability in edge computing environments and autonomous navigation systems. Current projects explore machine learning integration for anomaly detection in connected vehicles and secure acceleration of cryptographic operations. Analysis of Dr. Arafin's 2022-2025 publications reveals strategic focus areas: electromagnetic fingerprinting for radio units in O-RAN (2025), spatial acceleration of Kolmogorov-Arnold Networks (2025), and NTT-based cryptography accelerators (2024). His research demonstrates consistent innovation in securing autonomous navigation systems and edge devices, with emerging work on in-memory computing architectures using resistive memory technologies. Key trends include hardware-centric defense against model inversion attacks, voltage overscaling for lightweight authentication, and robust multi-robot coordination in dynamic environments. Scientific Awards: No scientific awards, fellowships, or medals were documented in the source materials. Dr. Arafin leads significant collaborative research, including the NSF CISE-MSI grant (DP: CNS) for edge-based robust multi-robot systems. His educational initiatives feature Capture-the-Flag competitions targeting underrepresented students in cybersecurity. Current grant activities emphasize practical security solutions for autonomous navigation, multi-robot coordination, and IoT edge devices, with demonstrated focus on translating research into deployable countermeasures for real-world threats in dynamic operational environments.
Jonathan Balkind is an Assistant Professor in the Department of Computer Science at the University of California, Santa Barbara (UCSB). His research focuses on the intersection of computer architecture, programming languages, and operating systems, with an emphasis on pragmatic system design and open-source hardware. He leads the ArchLab at UCSB and is affiliated with the OpenPiton project, an open-source manycore research framework. Education includes a PhD and MA in Computer Science from Princeton University (adviser: Prof. David Wentzlaff), an MSci in Computing Science from the University of Glasgow (advisers: Prof. Joseph Sventek and Dr. John O'Donnell), and exchange studies at UCSB. His work has been supported by awards such as the NSF Early CAREER Award (2023) and the Open Hardware Trailblazer Fellowship (2022). Research interests span heterogeneous computing, cache-coherent systems, FPGA integration, and domain-specific architectures. Notable projects include the 25-core Piton chip, the CIFER SoC with embedded FPGA, and the DECADES manycore processor. Recent publications address fused-kernel operating systems (Stramash), control logic synthesis, and hyperloop data-center architectures. His awards reflect contributions to open-source hardware and academic mentorship, including Siebel Scholarship (2018), Gordon Y.S. Wu Fellowship (2013–2017), and multiple teaching/research recognitions. He actively collaborates with industry (e.g., Microsoft Research, ARM) and advises on open-source projects.
Tiago Manuel Ribeiro Gomes is an Assistant Professor at the Department of Industrial Electronics within the School of Engineering at the University of Minho, Portugal. He is also a Senior Researcher at Centro ALGORITMI and a member of both the IE R&D Group and the ESRG R&D Lab. Holding a Ph.D. in Electronics and Computers Engineering, his research focuses on embedded real-time systems, computer architectures, and hardware/software co-design for IoT devices. Academic Degree: Ph.D. in Electronics and Computers Engineering Current Position: Assistant Professor, School of Engineering, University of Minho Gomes has led extensive research in IoT systems over 15 years, particularly in hardware acceleration for automotive LiDAR sensors, secure embedded systems, and efficient OS frameworks for low-end devices. His work includes the EU-funded CROSSCON project and spans hardware-assisted security, dynamic binary translation, and wireless sensor networks. Recent publications highlight his expertise in automotive sensor technology, with articles like FOG-Zip for LiDAR compression, SecureQNN for TinyML security, and Hardware-Assisted Range Image Generation for LiDAR processing. His work bridges IoT, embedded systems, and cybersecurity, focusing on real-time performance and hardware-software co-design. Projects include the development of reliable/secure automotive sensor solutions and EU project CROSSCON. He contributes to open-source frameworks like UTango for IoT security and investigates heterogeneous fault tolerance architectures using Arm/RISC-V processors. Labs: IE R&D Group, ESRG R&D Lab Education: Ph.D. in Electronics and Computers Engineering, Master’s in Telecommunications Engineering (both from University of Minho)
