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Jean Pierre DavidView profile

Professor

• Digital Signal Processing
• Distributed and Concurrent Processing
• Computer Architecture and Design
• +6 more

Jean Pierre David is a Full Professor in the Department of Electrical Engineering at Polytechnique Montréal. He has been with the institution since January 2006, was promoted to Associate Professor in June 2013, and became a Full Professor in June 2021. His research focuses on digital systems design, reconfigurable systems, and hardware implementations of artificial intelligence applications. David received his Electrical Engineering degree (specializing in electronics) from the University of Liège (Belgium) in 1995. He completed his Ph.D. in June 2002 at the Catholic University of Louvain, with research focused on reconfigurable systems (FPGAs). Before joining Polytechnique Montréal, he was a professor at the University of Montreal from August 2002 to January 2006. Jean Pierre David's research spans several key areas in electrical engineering and computer science. His primary focus is on digital systems design, configuration, and programming, with particular expertise in reconfigurable systems such as FPGAs and microcontrollers. He has made significant contributions to Hardware Description Languages (HDL), developing methodologies for fast, safe, and simple design of digital architectures. His work extends to Hardware-in-the-Loop (HIL) simulation, Deep Packet Inspection (DPI) for high-speed communications (10GBE, 40GBE, 100GBE), and applications of digital systems in artificial intelligence, particularly neural network implementations. David's recent research has increasingly focused on energy-efficient AI hardware, RISC-V processor design for neural network acceleration, and specialized architectures for low-precision computation. His publication record shows a clear evolution from foundational work in digital system design and FPGA implementation toward increasingly sophisticated applications in artificial intelligence and neural network acceleration. The most recent publications demonstrate expertise in creating specialized hardware for efficient AI computation, with a strong emphasis on low-precision and binary neural networks that can run efficiently on resource-constrained devices. His work bridges computer architecture, electrical engineering, and artificial intelligence, creating practical hardware solutions for emerging computational challenges. David is affiliated with several important research groups and institutions including the Strategic Microsystems Group of Quebec (ReSMiQ), the Institute of Electrical and Electronics Engineers (IEEE), and the Institute for Data Valorization (IVADO). His work has been recognized through numerous publications in high-impact journals and conferences, with a total of 108 publications to his name. Professor David has supervised an impressive number of graduate students throughout his career, mentoring 9 Ph.D. students and 24 Master's students to completion. His students have worked on diverse topics including FPGA-based neural network acceleration, hardware implementations of deep learning algorithms, energy harvesting systems for IoT devices, and specialized architectures for low-precision computation. His lab appears to maintain strong connections with industry through various research projects and collaborations with researchers like Yves Savaria. His research laboratory focuses on the intersection of hardware design and artificial intelligence, with particular emphasis on creating efficient implementations of neural networks on specialized hardware platforms. The lab maintains strong connections with industry partners and collaborates extensively on projects related to network processing, AI acceleration, and energy-efficient computing systems.

Fareena SaqibView profile

Associate Professor

• Hardware Security
• IoT Security
• Hardware Trust and Authentication
• +5 more

Fareena Saqib is an Associate Professor in the Department of Electrical and Computer Engineering at the University of North Carolina at Charlotte (UNCC), serving as Director of the Hardware and Embedded Design and Security (HEADS) Lab. Her research focuses on hardware security, IoT security, and embedded systems security, with particular expertise in physical unclonable functions (PUF), FPGA-based security, and supply chain risk management. She leads efforts in developing secure boot frameworks, countermeasures against side-channel attacks, and authentication protocols for resource-constrained devices. Her work spans multiple domains including automotive networks (CAN-FD security), FPGA security through logic locking and dynamic reconfiguration, and embedded systems protection against DMA and other hardware-level attacks. Dr. Saqib has published extensively on topics like counterfeit IC detection using machine learning, secure communication frameworks for electronic control units, and hardware-assisted information flow tracking in RISC-V architectures. Her research has been supported by grants such as NSF Student Travel Grants for IEEE HOST conferences. Key contributions include novel authentication protocols based on PUF technology, delay-based machine learning models for attack mitigation, and secure design flows for reconfigurable systems. She actively promotes cybersecurity education through initiatives like the HACE Lab, an online platform for hardware security evaluation.

Ken MaiView profile

Research Professor

• High-Performance Circuit Design
• Secure IC Design
• Radiation Hardening
• +4 more

Ken Mai is a Principal Systems Scientist in the Department of Electrical and Computer Engineering at Carnegie Mellon University (CMU), part of the College of Engineering. He holds a B.S., M.S., and Ph.D. in Electrical Engineering from Stanford University. His research focuses on high-performance circuit design, secure IC design, radiation hardening, reconfigurable computing, and computer architecture. He has received prestigious awards including the NSF CAREER Award and the George Tallman Ladd Research Award. Education: Ph.D., Electrical Engineering, Stanford University, 2005 M.S., Electrical Engineering, Stanford University, 1997 B.S., Electrical Engineering, Stanford University, 1993 Research Interests: Dr. Mai’s work addresses challenges in nanometer-scale CMOS technology, including interconnect delay, leakage, and soft errors. His projects include secure IC design against hardware attacks, robust memory techniques using digital communications, 100GHz logic via cryogenic cooling, and bio-implantable computing platforms. He collaborates with neurosurgeons at the University of Pittsburgh for medical applications. Key Projects: Secure IC Design: Countermeasures against invasive/non-invasive attacks Robust Memory Design: Error correction codes for resilience 100GHz Logic: Cryogenically cooled CMOS for high-speed applications Bio-Implantable Systems: Low-power, high-density computing for medical devices Awards: NSF CAREER Award George Tallman Ladd Research Award Eta Kappa Nu Excellence in Teaching Award Teaching and Advising: He teaches courses like 18-322 (Digital Circuits), 18-617 (Memory Systems), and advises students including Mudit Bhargava and Mark McCartney. His lab, the VLSI Design Group, develops tools and methodologies linking circuit design to architectural design. Contact: Email: kenmai@ece.cmu.edu Website: Carnegie Mellon VLSI Design Group

Carsten TrinitisView profile

Professor

• High Performance Computer Architectures
• Microprocessor Architectures
• Co-design
• +5 more

Prof. Dr. Carsten Trinitis is a full professor at the Chair of Computer Architecture & Parallel Systems within the TUM School of Computation, Information and Technology. Specializing in high-performance computer architecture with a unique focus on spaceflight applications and informatics ethics, he leads the 'Gesellschaft für Informatik und Ethik' (Society for Informatics and Ethics). Ph.D. in Electrical Engineering from TUM (1998) Industry experience before returning to academia Former Assistant Professor in History of Science (2002-2010) at Universität der Bundeswehr München Full Professor of Distributed Computing at University of Bedfordshire (2010-2014) His research spans three major domains: High-Performance Computing: Focused on microprocessor architectures, hardware-oriented optimizations, and co-design approaches. Recent work includes GPU power capping strategies and Data Distribution Service (DDS) middleware enhancements. Space Systems: Pioneering computer architectures for nanosatellites with projects like MOVE-II mission and MicroPython-based satellite control systems. Digital Ethics: Through his 'Gewissensbits' initiative, he explores ethical decision-making frameworks for technology and contributes to the German Informatics Society's ethical guidelines. Key publication trends show interdisciplinary work connecting: HPC systems and edge AI applications FPGA-based verification and RISC-V processors Time series analysis at petascale performance Hardware-software co-design for extreme environments Continued emphasis on ethical computing frameworks Scientific Recognition: TeachInf Award for Outstanding Teaching (2023) Hans Meuer Award for Best Paper (2020) ZARM Master Thesis Awards (2016, 2017) Prof. Trinitis leads multiple research projects including: SEANERGYS (EuroHPC) - Energy-efficient computing systems PlasmaPEPS - Plasma physics simulation environments OpenCUBE - Open computing frameworks for space MUNIQC-ATOMS - Quantum computing integration

• Computing-in-Memory
• Resistive RAM (RRAM) Technology
• Neuromorphic Computing
• +7 more

Dr. Moritz Joseph serves as Professor and Chair of Software for Systems on Silicon at RWTH Aachen University's School of Electrical Engineering and Information Technology. His research group operates within the Institute for Communication Engineering (ICE), focusing on cutting-edge hardware architectures for next-generation computing systems. The chair maintains laboratory facilities in the ICT Cube 1 building at Kopernikusstr. 16 in Aachen, Germany. Professor Joseph's research spans Computing-in-Memory architectures , Resistive RAM technologies , and neuromorphic computing systems . His work addresses critical challenges in hardware acceleration for deep learning, with particular emphasis on reliability, security, and energy efficiency of novel memory-centric computing paradigms. His research bridges computer architecture, hardware security, and machine learning acceleration. Analysis of his recent publications reveals a strong focus on RRAM-based compute-in-memory systems, with increasing attention to security implications of thermal effects and side-channel attacks. His work demonstrates progression from fundamental memory characterization to system-level integration and security analysis, showing consistent innovation in memory-centric computing architectures over the past five years. Professor Joseph actively contributes to the development of simulation frameworks and evaluation methodologies for emerging memory technologies, as evidenced by his work on platforms like CIM-Explorer, Ratatoskr, and gem5 extensions. His research has significant implications for energy-efficient AI hardware and secure computing systems.

Jordi CortadellaView profile

Professor

• Electronic Design Automation (EDA)
• Concurrency Theory
• Asynchronous Circuits
• +6 more

Jordi Cortadella is a Full Professor in the Department of Software at the Universitat Politècnica de Catalunya (UPC), Spain. His academic journey spans decades, with a Ph.D. in Computer Science from UPC (1987) and visiting roles at institutions like UC Berkeley and Intel Corporation. A Fellow of the IEEE (2015) and member of Academia Europaea (2013), he specializes in formal methods, concurrency theory, and asynchronous circuit design. His work bridges theoretical and applied research in EDA tools and VLSI systems. Education M.S. in Computer Science, UPC (1985) Ph.D. in Computer Science, UPC (1987) Research Interests : Cortadella's research focuses on algorithms for electronic design automation, asynchronous circuits, and formal methods. Recent publications explore Petri net decomposition, dataflow circuit verification, and ethical frameworks for research governance. His work impacts both theoretical concurrency models and practical applications like FPGA optimization and energy-efficient design. Scientific Awards : Fellow of the IEEE (2015) Member of Academia Europaea (2013) Distinction for University Research Promotion (Catalan Government, 2003) Descartes Prize Finalist (2002) Best Ph.D. Thesis at UPC (1992) National Award for Best Computer Science Student (1986)

Ataberk OlgunView profile

Lecturer

• Computer Architecture
• Memory Systems
• DRAM Reliability
• +5 more

Ataberk Olgun is a Lecturer at the Department of Information Technology and Electrical Engineering at ETH Zürich, where he conducts research in the SAFARI Research Group under Professor Onur Mutlu. His work focuses on computer architecture with particular emphasis on memory systems, DRAM reliability, and security vulnerabilities such as RowHammer. His educational background includes BSc and MSc degrees from TOBB ETÜ (Ankara University of Economics and Technology) under Professor Oğuz Ergin's supervision. Prior to his doctoral work at ETH Zürich, he worked at Kasirgalabs until 2021, leading the design of a RISC-V system-on-chip manufactured using SKY130 technology, and previously developed authentication methods based on behavioral biometrics with Professor Kemal Bicakci. Olgun's research interests center on designing reliable and energy-efficient memory systems. He has developed FPGA-based testing platforms for DDR3/4 and HBM2 DRAM chips, created end-to-end systems for processing-in-memory techniques, and made significant contributions to understanding and mitigating the RowHammer problem. His work often combines hardware design with system-level considerations to address fundamental challenges in modern memory technology. His publication record shows consistent output in top-tier venues including ACM TACO, USENIX Security, ISCA, MICRO, and HPCA, with a clear trend toward increasingly sophisticated investigations of DRAM vulnerabilities and innovative mitigation strategies. Recent work focuses on fine-grained DRAM architectures, scalable RowHammer mitigation techniques, and experimental characterization of emerging memory technologies. As part of the SAFARI Research Group at ETH Zürich, Olgun collaborates extensively with Professor Onur Mutlu and other researchers on memory systems research. His technical expertise spans FPGA-based prototyping, DRAM characterization, hardware security, and memory controller design. Olgun maintains an active research presence with numerous ongoing projects investigating next-generation memory technologies, security vulnerabilities in modern DRAM, and energy-efficient memory system designs. His work bridges theoretical understanding with practical implementation through FPGA-based experimental platforms.

Renato MancusoView profile

Associate Professor

• Cyber-Physical Systems
• Real-Time Systems
• Embedded Systems
• +5 more

Renato Mancuso is an Associate Professor in the Computer Science Department at Boston University (BU) and director of the BU Cyber-Physical Systems Lab (CPSLab@BU). He is also affiliated with the BU Department of Electrical and Computer Engineering. He received his Ph.D. from the University of Illinois at Urbana-Champaign (2017) and degrees from the University of Rome 'Tor Vergata' (B.S. 2009, M.S. 2012). His research focuses on real-time and embedded systems, including techniques for achieving controllable timeliness in safety-critical applications, FPGA-accelerated systems, and autonomous systems. He pioneers software/hardware techniques for performance profiling and management in hybrid CPU+FPGA platforms, with applications in robotics, aviation, and autonomous ground vehicles. Key research areas include cyber-physical systems, real-time resource management, and black-box workload profiling. His work has received multiple awards, including the NSF CAREER Award (2023) and the 2024 ACM SIGBED Early Career Researcher Award. His research is supported by federal agencies (NSF) and industry partners (Bosch, Red Hat, Cisco, Xilinx). He advises numerous Ph.D. and master’s students and leads initiatives like the BU F1Tenth Autonomous Racing Organization (ACRO). His lab actively recruits students with expertise in robotics, operating systems, virtualization, and FPGA development. Notable contributions include the E-WarP profiling framework, the Omnivisor hypervisor, and innovations in FPGA-based system management. He has authored over 50 peer-reviewed publications and holds patents in embedded systems design.

Ulrich RückertView profile

Professor

• Neuromorphic Computing
• Embedded Systems
• Machine Learning
• +9 more

Prof. Dr.-Ing. Ulrich Rückert is a Professor at the Faculty of Engineering of the University of Bielefeld , where he leads the Cognitronics & Sensor Technology Group and participates in CITEC (Center for Cognitive Interaction Technology). He serves as Vice Rector for Digitalization and Data Infrastructure , driving university-level digital transformation initiatives. Research Focus : Neuromorphic computing, spiking neural networks (SNNs), embedded systems, robotics, UWB localization, and reconfigurable hardware. Projects : Leading federal and EU-funded initiatives like eProcessor (RISC-V multi-core systems), VEDLIoT (efficient deep learning in IoT), and Al4DG (AI in distribution grid control). Teaching & Leadership : Academic advisor for the Master in Biomechatronics , chairs examination boards, and leads the Library Commission . His work integrates neuromorphic hardware with edge computing and real-time systems , supported by grants from the European Union and German Federal Government . Recent publications analyze FPGA-based SNNs , UWB localization , and resource-efficient embedded architectures . Scientific Contributions : Over 200 publications in robotics, neural networks, and hardware-software co-design. Notable collaborations with institutions in Germany, Switzerland, and Italy.

Luca FanucciView profile

Professor

• Integrated Circuit Design
• Embedded Systems
• System-Level Design
• +7 more

Professor Luca Fanucci is a Full Professor of Electronics at the Department of Information Engineering , University of Pisa. He serves as Rector's Delegate for Inclusion of Students with Disabilities and leads research in integrated circuits, embedded systems, and assistive technologies . Institutional roles include membership in the National University Conference of Delegates for Disability (CNUDD) and leadership in the PhD program in Information Engineering. Born: Montecatini Terme (1965) Education: Laurea in Electronic Engineering (1992), PhD in Information Engineering (1996), University of Pisa Professional Journey: ESA research (1992-1996), CNR researcher (1996-2004), University of Pisa faculty (2004-present) His research focuses on: System-level design of integrated circuits and embedded systems Hardware-software co-design for low power consumption Spacecraft and satellite communication systems Medical devices and telemonitoring platforms Assistive technologies for disabilities Recent publications highlight AI in space applications and telemedicine systems . Key projects include the Ingeniars spin-off for satellite communications and the AsTech National Laboratory for assistive technologies. Scientific Recognition : IEEE Fellow (2019) 40+ patents H-index 34 (5000+ citations) He coordinates international conferences (DATE, HiPEAC, Spacewire) and serves as Associate Editor for Technology and Disability and Microprocessors and Microsystems journals.

Johannes PfauView profile

Researcher

• FPGA Architecture
• Reconfigurable Computing
• Digital Beamforming
• +3 more

Dr. Johannes Pfau serves as a Scientific Assistant at the Institute for Information Processing Technology (ITIV) within Karlsruhe Institute of Technology (KIT), working in Prof. Becker's research group. His position combines postdoctoral research in advanced FPGA architectures with teaching responsibilities including System-on-Chip internships and academic advising for specialized engineering tracks. Education: Doctorate (Dissertation) in Electrical Engineering and Information Technology, Karlsruhe Institute of Technology, 2024 Research Interests: Pfau's work centers on reconfigurable computing with three interconnected pillars: (1) Next-generation FPGA architectures using emerging technologies like RFETs that require fundamental toolchain redesigns; (2) Digital beamforming systems for satellite Earth observation that replace analog processing with FPGA-based solutions to enable on-orbit data compression; and (3) High-throughput data acquisition systems for 6G prototyping handling multi-100Gbps streams through RFSoC platforms. His research bridges semiconductor physics, hardware architecture, and practical applications in communications and remote sensing. Publication Trends: Pfau's 15 most recent publications (2021-2024) reveal a strong focus on practical FPGA implementations addressing real-world constraints. His work increasingly integrates power management (7 papers), 6G infrastructure (5 papers), and novel semiconductor technologies (4 papers), with a clear trajectory toward hardware solutions for satellite communications and next-generation wireless systems. The research demonstrates consistent progression from architectural innovations (RFET, V-FPGAs) to applied systems (beamforming, 6G testbeds). Advising and Mentorship: Pfau maintains an active student supervision portfolio with documented guidance of 7+ Bachelor's and Master's theses since 2021. His projects emphasize hands-on hardware development, spanning power management techniques, beamforming filter design, and prosthetic control systems. The academic advising role for specializations 13 and 21 positions him at the intersection of computer science and electrical engineering education. Research Context: As a core member of Prof. Becker's group at ITIV, Pfau contributes to KIT's leadership in reconfigurable systems research. The group maintains strong industry connections through 6G initiatives and satellite technology development, with Pfau's work directly supporting German and European efforts in secure communications infrastructure and Earth observation systems.