Sarah Harris is Professor and Undergraduate Coordinator in the Department of Electrical and Computer Engineering at University of Nevada, Las Vegas. Her research focuses on computer architecture education, FPGA-based systems, and hardware implementations of neural networks. Research areas include: RISC-V architecture education tools FPGA-based hardware design Embedded AI systems Computer engineering pedagogy Her publication portfolio shows strong focus on educational innovation with 7 publications (2021-2024) on RISC-V teaching tools and MOOCs, alongside hardware implementations of neural networks and contributions to bioinformatics tools. Earlier work includes digital design fundamentals and memory systems.
Oliver Bringmann is a full Professor and head of the Chair of Embedded Systems at the University of Tübingen, Germany, and a member of the board of directors at the FZI Research Center for Information Technology. His research integrates embedded-system design, energy-efficient AI accelerators, dependable automotive perception, and medical AI for capsule endoscopy. Education & Career Ph.D. in Computer Science, University of Tübingen, 2001 Diploma in Computer Science, University of Karlsruhe (KIT) Head, Chair of Embedded Systems, University of Tübingen (since 2012) Deputy spokesperson & spokesperson, Dept. of Computer Science, University of Tübingen (2014-2022) Board of Directors, FZI Research Center for Information Technology Research Interests Bringmann’s group pioneers hardware/software co-design for ultra-low-power Edge-AI , developing RISC-V based accelerators, compiler-aware neural-architecture search, and real-time perception systems for autonomous driving and medical devices. Key topics include: Energy-efficient AI architectures (“Edge AI”) and custom accelerator generation Robust collective perception under adverse weather (LiDAR, camera, V2X fusion) Timing/power-predictable embedded software and system-on-chip design automation Hardware-assisted security and safety for automotive & IoT systems AI-driven capsule endoscopy localization and anomaly detection Recent Publication Trends His 2024-2025 articles reveal a strong shift toward robust multimodal perception for automated driving (snow, fog, collective LiDAR fusion) and Edge-AI medical devices (capsule endoscopy with multi-task CNNs). Core contributions span dataset generation (SCOPE, SnowyLane), safety metrics (LSM), and fast performance modeling for DNN accelerators. Professional Service & Projects Executive/Steering Committees: IEEE/ACM DATE, CODES+ISSS, CASES, ITSS conferences EU CATRENE EDA roadmap chapter lead (Embedded Software & ESL-to-RTL) Principal investigator in Scale4Edge, OCEAN12, enerDAG and other national projects on energy-efficient sensorics and secure energy trading. His group maintains extensive collaborations with automotive and semiconductor industry, focusing on dependable, energy-aware embedded intelligence.
Patrick Karl is a Researcher at the Chair of Security in Information Technology (Technische Universität München). He holds an M.Sc. degree and focuses on efficient hardware implementations for post-quantum cryptography , particularly hardware acceleration of digital signature algorithms on RISC-V platforms for embedded systems. His work addresses performance optimization, power/energy efficiency, and countermeasures against physical attacks such as side-channel and fault attacks . His research spans both FPGA prototyping and ASIC design , including tape-outs for security applications. He contributed to NIST submissions like CROSS , LESS , and FuLeeca , and has published extensively on topics including lattice-based cryptography, masked accelerators, and hardware API overhead for lightweight cryptography. Patrick has taught Lab Course ASIC Design of Hardware Accelerators for RISC-V since WS22/23 and Lab Course Crypto Implementation in SS22. His publications (15 most recent) highlight trends in post-quantum cryptographic hardware , RISC-V security , and physical attack countermeasures . He has presented at venues like RISC-V Summit Europe, COSADE, and FDTC.
Dr. Preethi Srivathsa is an Assistant Professor - Senior Scale in the School of Computer Engineering at Manipal Academy of Higher Education (MAHE), Bengaluru. She holds a B.Tech, M.Tech, and Ph.D. (awarded by Presidency University in 2022). Her academic career includes positions at Presidency University (2019-2023) and East Point College of Engineering (2008-2019). Her research focuses on: Computer architecture and low-power hardware design IoT applications and cyber-physical systems Cryptography and blockchain security Machine learning implementations in hardware FPGA-based accelerators and optimization techniques Her publication portfolio shows strong emphasis on hardware-efficient algorithms, cryptographic systems (especially elliptic curve applications in blockchain), and emerging IoT architectures. Recent work integrates machine learning with hardware acceleration for smart home systems and agricultural technology. Awards and recognitions: Best Paper Award at IEEE iSES-2021 for low-power sorter design Infosys Bronze Partner Faculty (2013) She has developed intellectual property including IoT-based monitoring systems and blockchain educational frameworks. Technical skills include Verilog, FPGA design, IoT platforms (Arduino/Raspberry Pi), and multiple programming languages.
Luciano Ost is a Senior Lecturer and Programme Director of the Computer and Electronic Engineering (CEE) Programme at the University of Leicester. He holds a Ph.D. in Computer Science from Pontifical Catholic University of Rio Grande do Sul (PUCRS), Brazil (2010). His research focuses on enhancing reliability, security, and performance of embedded and life-critical systems through innovative hardware/software co-design approaches. Key areas include fault tolerance in neural networks, radiation effects on embedded systems, and real-time control systems. Prior to Leicester, he worked at the University of Montpellier II (France) as an assistant professor and research assistant. He has authored/co-authored over 100 papers and two books, with notable contributions to soft error reliability assessment frameworks (e.g., SOFIA, gem5-FIM) and embedded system security solutions like BIDS for in-vehicle networks. His research spans topics like FPGA-accelerated intrusion detection (BNN-based), radiation resilience in IoT edge devices, and compiler optimization impacts on multicore reliability. He has conducted extensive studies using Geant4 simulations and virtual platforms for fault injection analysis.
Timo Hämäläinen is a Professor of Computer Engineering at Tampere University, leading the Unit of Computing Sciences within the Faculty of Information Technology and Communication Sciences. He is a core member of the System-on-Chip research group and the Computer Engineering Team, actively contributing to the System-on-Chip Hub initiative. His research focuses on System-on-Chip (SoC) design methodologies, FPGA-based high-level synthesis, real-time embedded systems, and open-source hardware-software co-design frameworks like RISC-V and HEVC encoding. He has pioneered work on agile SoC development processes and validation techniques for large-scale hardware systems. Key research areas include: High-level synthesis (HLS) optimization for FPGAs Real-time processor architectures and context-switching latency reduction Formal verification of IP-XACT-compliant SoC designs Resilient RISC-V MPSoC implementations Hardware-accelerated algorithms for signal processing and networking His recent publications (2023-2025) emphasize agile SoC development frameworks, hardware-software co-design for real-time systems, and validation methodologies for large-scale embedded systems. He has contributed to open-source projects like Kvazaar HEVC encoder and the Kactus2 IP-XACT toolchain. Academic advising includes students such as Santéri Mäki-Äijö (formal verification), Arto Oinonen (RISC-V tooling), and Sakari Lahti (processor modeling). His work integrates academic research with industrial collaboration through frameworks like the Fault-slip-Through quality assessment methodology.
Tim Fritzmann is a researcher at the Department of Security in Information Technology (Technische Universität München). His work focuses on post-quantum cryptography, lattice-based algorithms, and secure hardware/software co-design for constrained environments like automotive systems and embedded devices. Post-Quantum Cryptography Lattice-Based Cryptography Hardware/Software Co-Design Error-Correcting Codes RISC-V Architecture ASIC Design His recent publications (2018–2022) highlight advancements in fault attacks, side-channel countermeasures, and efficient implementations of lattice-based protocols for IoT, automotive systems, and FPGA-SoC platforms. Key themes include parameter optimization for decryption reliability, masked accelerators, and instruction-set extensions for quantum-resistant algorithms. Research projects involve collaborations with institutions like the University of Leuven and TU München, emphasizing post-quantum security integration into real-world hardware architectures. No explicit awards or student advisement details are listed publicly.
Manolis G.H. Katevenis is a Professor at the Department of Computer Science, University of Crete, and the founder and Head of the Computer Architecture and VLSI Systems (CARV) Laboratory at the Institute of Computer Science (ICS), Foundation for Research and Technology – Hellas (FORTH) in Heraklion, Crete, Greece. He has held academic positions since 1986 and played a pivotal role in establishing the Computer Science Department at the University of Crete. His research spans computer architecture, interconnection networks, VLSI systems, and high-performance computing, with a strong focus on scalable, low-power, manycore systems and RISC-V. He has led numerous European R&D initiatives, including serving as Coordinator of the ExaNeSt project. PhD in Computer Science, University of California, Berkeley (1983) MSc in Electrical Engineering and Computer Science, University of California, Berkeley (1980) Diploma of Electrical Engineering, National Technical University of Athens (1978) Manolis Katevenis's research focuses on advancing scalable system architectures for high-performance and big data computing. His work in computer architecture includes RISC-V, exascale computing, and manycore systems. He has made foundational contributions to interprocessor communication, particularly through remote-write, remote-DMA, and remote-enqueue mechanisms, and has pioneered innovations in interconnection networks and low-latency network interfaces. His research integrates hardware and software co-design to optimize performance, energy efficiency, and scalability in large-scale computing systems. The recent publications highlight a strong trend in exascale computing, interconnection networks, and FPGA-based prototyping of manycore systems. His work emphasizes scalable, low-power architectures, with recurring themes in congestion management, fair scheduling, crossbar design, and hardware-software integration for HPC. The articles span high-impact journals such as IEEE/ACM Transactions on Networking, IEEE Micro, and Computer Networks, reflecting sustained contributions to computer architecture and networking. ACM Doctoral Dissertation Award (1984) David J. Sakrison Memorial Prize (1983) IBM PhD Fellowship (1981–1983) Greek State Fellowship (1973–1978) Stelios Pichoridis Award for Outstanding University Teaching (2015) Member of Academia Europaea (elected 2012) Award by the Secretary General of the Region of Crete (2003) IEEE Milestone recognition for the RISC Project (2015) Manolis Katevenis has supervised over 50 graduate theses and mentored many prominent Greek computer architects, including recipients of the ACM Maurice Wilkes Award. He has served as Principal Investigator or co-PI in over 30 R&D projects with a total budget exceeding 18 million euros, including major European initiatives such as ExaNeSt (which he coordinated), EuroEXA, EcoScale, SARC, ENCORE, and multiple HiPEAC Network of Excellence projects. His leadership extends to project coordination, architectural design, FPGA prototyping, and systems software development. Katevenis founded and leads the CARV Laboratory at FORTH-ICS, a major research team with 80–100 members focused on computer architecture and VLSI systems. The lab has spun off the Distributed Computing Systems (DCS) Laboratory and is central to European exascale computing efforts, including participation in the European Processor Initiative. CARV has developed large-scale prototypes such as the 768-core ExaNeSt system and the Formic FPGA platform for manycore research.
Dr. Mihai Teodor Lazarescu is an Associate Professor at the Department of Electronics and Telecommunications (DET), Politecnico di Torino , where he contributes to research and teaching activities. He is also a member of the PolitoBIOMed Lab (Biomedical Engineering Lab) and the Ambient Sensing and Processing research group. Scientific Affiliation: IEEE Member (2019-present) Editorial Roles: Guest Editor for SENSORS, ELECTRONICS, and ACM Transactions on Embedded Computing Systems His research interests focus on hardware acceleration for machine learning algorithms, particularly using FPGAs for data center and embedded applications. He works on high-level synthesis optimization flows, capacitive sensor design for indoor monitoring, and low-power embedded systems . His work intersects Internet of Things , Wireless Sensor Networks , and Machine Learning with applications in human localization, environmental monitoring, and industrial automation. Recent publications demonstrate expertise in neural network optimization , DSP resource sharing , and multi-FPGA allocation . His teaching spans Applied Electronics , Digital Electronic Design , and Embedded Systems Optimization across bachelor's and master's programs in Electronic Engineering and Computer Engineering . Patents: Noise cancellation for single-plate capacitive sensors Capacitive sensor for space change detection Projects: Scientific Manager for Horizon 2020-S2RJU project (2018)
Nikela Papadopoulou is a Lecturer (Assistant Professor) in Low Carbon and Sustainable Computing at the University of Glasgow's School of Computing Science. She is affiliated with the GLAsgow Systems Section and focuses on optimizing high-performance computing (HPC) systems for reduced environmental impact, including performance modeling, application optimization, and energy-efficient resource management. Her work also explores co-design strategies for machine learning workloads. Education: PhD in Electrical and Computer Engineering from National Technical University of Athens (NTUA). Postdoctoral research at Chalmers University of Technology (Sweden) and NTUA, contributing to European projects like ACTiCLOUD, EuroEXA, and HiDALGO. Member of ACM and HiPEAC. Research Interests: HPC systems optimization, energy efficiency in computing, sustainable computing practices, machine learning co-design, and parallel algorithm development. Teaching: Currently teaches Systems Programming (COMPSCI4081) and Internet Technology (COMPSCI5012) at the MSc level. Advising: Supervises Shuxuan Li on FPGA-based compiler transformations for sequence models. Active in grant-funded projects related to HPC and sustainable computing. Labs/Teams: Active contributor to the GLAsgow Systems Section, focusing on HPC and low-carbon computing innovations.
Professor Jim Harkin serves as Head of the School of Computing, Engineering and Intelligent Systems at Ulster University's Magee Campus in Derry~Londonderry. He is a prominent member of the Computational Neuroscience and Neuromorphic Engineering team within the Intelligent Systems Research Centre (ISRC), where he leads cutting-edge research bridging biological neural processes with hardware implementations. Harkin's research focuses on developing intelligent embedded systems capable of self-repair under error conditions, drawing inspiration from neural network models. His work explores how computer models of neural networks can be mapped to hardware to build highly efficient and reliable embedded computers. Key innovations include Networks-on-Chip strategies and hardware implementation of self-repairing Spiking Neural Networks. His research spans multiple domains including fault tolerance, neuromorphic computing, and AI hardware acceleration, with applications in healthcare, structural monitoring, and energy systems. Analysis of his recent publications reveals a strong trend toward practical applications of neuromorphic computing, particularly in healthcare monitoring systems, structural health assessment, and energy-efficient computing. His work shows increasing integration of spiking neural networks with real-world hardware implementations, demonstrating a clear trajectory from theoretical models to deployable systems with commercial applications. Harkin has received numerous scientific accolades including the Life and Health Startup Company of the Year 2019 from InventNI Ulster Distinguished Learning Support Fellowship Multiple awards for innovative routing strategies in neural network hardware implementations Professor Harkin has secured significant research funding exceeding £3.5 million from diverse sources including EPSRC, MRC, Innovate UK, HSC R&D, InvestNI, and DEL. His grant portfolio demonstrates strong industry and healthcare sector engagement, particularly through his co-founded startup Respiratory Analytics which focuses on medical analytics. He has supervised numerous research students and has been instrumental in Ulster University's Computer Science submissions to major research assessment exercises including RAE 2008, REF2014, and REF2021. As Head of School and leader within the Intelligent Systems Research Centre, Harkin oversees multiple research teams focusing on computational neuroscience, neuromorphic engineering, and intelligent embedded systems. His lab has developed specialized FPGA-based platforms for simulating and implementing self-repairing neural networks, including the AstroByte multi-FPGA architecture for accelerated simulations of fault-tolerant spiking astrocyte-neuron networks.
Francisco Tirado is a Full Professor of Computer Architecture at Complutense University of Madrid since 1986. He has held leadership roles including Vice-Chancellor for Research (2012-2015), Dean of the Faculty of Physics (1994-2002), and Director of the Complutense Supercomputing Center (2002-2007). He is a founding member of the Spanish Society for Computer Science (SCIE) and Spanish Society for Computer Architecture (SARTECO). His research focuses on power-aware computing, heterogeneous systems, bioinformatics, and hardware design automation. He has authored over 242 publications and supervised 15 PhD theses. His professional service includes chairing 138 international conferences and serving on numerous committees for EUROMICRO, IEEE, and national research agencies. Education: No explicit details provided, but has been active at Complutense University since 1978. Affiliations: Member of COSCE Executive Board (2012), IEEE Senior Member (2005), and EUROMICRO Board (1991-2004). Research Interests: - Optimizing energy efficiency in high-performance computing systems - Design of heterogeneous architectures and accelerators - Bioinformatics applications through hardware/software co-design - Parallel programming models for emerging architectures - Automation tools for FPGA and embedded systems development Conference Contributions: Played multiple roles (General Chair, Program Chair) for major events like ParCo, HPCA, and EUROMICRO PDP conferences. Delivered 64 keynote/plenary lectures globally. Scientific Awards: Doctor 'Honoris Causa' from universities in Spain, Paraguay, and Peru 2013 National Computer Science Award IEEE Senior Membership Advising: Supervised 15 PhD students. Active in technology transfer contracts with industry. Labs/Teams: Founder and leader of the ArTeCS research group at Complutense University, specializing in computer architecture and high-performance computing innovations.
Sebastian Magierowski is an Associate Professor in the Department of Electrical Engineering & Computer Science at York University's Lassonde School of Engineering. He holds a P.Eng designation and has held faculty positions at the University of Calgary (2004–2012) and York University since 2013. His research focuses on semiconductor systems, bioinformatics, and artificial intelligence, with particular emphasis on energy-efficient analog/digital chips, CAD/EDA tools, and applications like mobile DNA sequencing and DNA-based data storage. Dr. Magierowski's academic journey includes a PhD in Electrical Engineering from the University of Toronto (2004). His work bridges electrical engineering and biomedical innovation, with contributions to CMOS-based nanopore DNA sequencing systems, capacitive sensors for DNA storage monitoring, and FPGA-accelerated bioinformatics tools. His research also explores hardware acceleration for embedded systems and novel sensing technologies for point-of-care diagnostics. Key research themes include: Development of semiconductor-based biosensors (e.g., CMOS nanopore systems) Design of compact, portable diagnostic devices Integration of AI and machine learning in bioinformatics pipelines Advances in DNA data storage and retrieval mechanisms His recent publications highlight innovations in low-power circuits for DNA sequencing, thermo-FET sensing systems, and embedded RISC-V multicore architectures for miniature devices. While no awards are explicitly listed, his extensive publication record reflects impactful contributions to interdisciplinary engineering and biomedical research. Dr. Magierowski's work emphasizes cross-disciplinary collaboration, with applications spanning healthcare, environmental monitoring, and data storage. His research group focuses on translating theoretical advancements into practical, scalable technologies for emerging biomedical and computational challenges.
Sebastián Sánchez Prieto is a Professor at the Department of Automatic Control, Universidad de Alcalá, Spain, affiliated with the Space Research Group (SRG-UAH). He holds a Doctorate from the same institution (1998) with a thesis on cosmic ion telescope control systems. His research focuses on space instrumentation, radiation detection systems, on-board data management, and embedded systems for space applications. He has contributed extensively to the Solar Orbiter mission, working on the Energetic Particle Detector (EPD) instrumentation and software validation. His technical expertise spans FPGA-based signal processing, RISC-V processor architectures, and model-driven engineering for space systems. Notable work includes advancing virtualization techniques for mixed-criticality space systems, digital beamforming architectures, and neural network applications in particle trajectory analysis. Publications emphasize cutting-edge topics like fault-tolerant computing in space environments, adaptive signal processing for space communications, and low-power positioning systems. He actively develops educational frameworks integrating on-board data management concepts across interdisciplinary university curricula. His contributions include over 50 peer-reviewed articles addressing hardware-software co-design, space software verification, and radiation effects mitigation. Current research explores AI-driven approaches for space instrumentation data analysis and next-generation on-board computing solutions.
Dionysios Pneumatikatos is a Professor at the School of Electrical and Computer Engineering of the National Technical University of Athens (NTUA) since September 2019. Previously, he served as a Professor and Chair of the Department of Electronic and Computing Engineering at the Technical University of Crete (2000–2019) and is an Associate Researcher at the Foundation for Research and Technology (FORTH) since 1997. His primary affiliations include the Computing Systems Laboratory (CSLab) at NTUA and the Computer Architecture and VLSI Systems (CARV) Laboratory at FORTH. Education: B.Sc. in Computer Science, University of Crete (1989) M.Sc. and Ph.D. in Computer Science, University of Wisconsin–Madison (1991, 1995) Research Interests: Computer Architecture Reconfigurable Computing Hardware Acceleration (e.g., FPGA, RISC-V) Energy-Efficient Systems Reliable System Design Application-Specific Architectures His work focuses on heterogeneous parallel systems , bioinformatics accelerators , and virtualization frameworks for reconfigurable platforms . Recent Projects & Contributions: Coordinator of the FASTER (FP7) project Principal Investigator in EDRA (H2020), EXTRA , and dReDBox Key roles in AXIOM , DeSyRe , and VPLANET These projects explore FPGA-based HPC systems , RISC-V ecosystems , and disaggregated data center architectures . Teaching & Mentorship: Teaches courses on Computer Architecture , Parallel Processing , and Logic Design at NTUA and TU Crete Supervised multiple national/EU projects, fostering interdisciplinary research in embedded and high-performance systems Labs & Networks: Active member of the HiPEAC European Network Program Committee roles at ISCA , FPL , and DATE Led the 21st International Conference on Field-Programmable Logic and Applications (FPL)
