Find Academic Supervisors

• Electronic Design Automation
• Fault Injection Simulation
• RISC-V Processors
• +7 more

Johannes Geier is a Researcher at the Chair of Design Automation at the Technical University of Munich (TUM). His work focuses on electronic design automation, fault injection simulations, and security countermeasures for RISC-V processors. University: Technical University of Munich Department: Chair of Design Automation Email: johannes.geier@tum.de Research Interests Electronic Design Automation (EDA) for analog and digital circuits Fault tolerance and reliability in RISC-V architectures Security analysis of post-quantum cryptographic systems Timing analysis and microfabrication techniques Optical Networks-on-Chip (NoC) and emerging technologies Compiler-assisted hardware security implementations Recent Research Trends Specializes in fault injection methodologies for hardware security validation Develops open-source tools like vRTLmod for RTL simulation acceleration Explores RISC-V vector extensions for post-quantum cryptography Investigates differential fault effect equivalence checks for efficiency Designs compiler-based security countermeasures against instruction skip attacks Works on concurrent multi-node XCP proxy server architectures

Vincent BeroulleView profile

Professor

• Microelectronics
• Hardware Security
• Fault Modeling
• +4 more

Professor Vincent Beroulle at Grenoble Institute of Technology's Esisar campus leads the LCIS laboratory, focusing on security and safety of complex integrated circuits and systems. His work bridges fault modeling, fault injection, and security for IoT and RFID technologies. Education: Engineer Degree (INPG, 1996), Master (University of Montpellier II, 1999), Ph.D. (University of Montpellier II, 2002) Current Role: Director of LCIS Laboratory, Professor in Embedded System Security & Safety Research spans hardware security, fault injection attacks, and vulnerability analysis of embedded systems. Recent work includes clock glitch fault injection studies, lightweight ECC countermeasures for RFID, and aging effects on PUF architectures. His team explores cross-layer methodologies to enhance fault models and security protocols. Supervision includes 12 current and former PhD students tackling topics like secure RFID tags, fault injection countermeasures, and PUF-based security. Projects under ANR, PEPR Cyber, and ERASMUS+ funding drive his lab's innovation in secure embedded design.

Sarah HarrisView profile

Professor

• Computer Architecture
• FPGA Design
• RISC-V Systems
• +3 more

Sarah Harris is Professor and Undergraduate Coordinator in the Department of Electrical and Computer Engineering at University of Nevada, Las Vegas. Her research focuses on computer architecture education, FPGA-based systems, and hardware implementations of neural networks. Research areas include: RISC-V architecture education tools FPGA-based hardware design Embedded AI systems Computer engineering pedagogy Her publication portfolio shows strong focus on educational innovation with 7 publications (2021-2024) on RISC-V teaching tools and MOOCs, alongside hardware implementations of neural networks and contributions to bioinformatics tools. Earlier work includes digital design fundamentals and memory systems.

• Hardware Security
• Side-Channel Attacks
• Cryptographic Circuits
• +3 more

Darshana Jayasinghe is a Postdoctoral Research Associate at the School of Electrical and Information Engineering (EIE) , University of Sydney. He holds a PhD from the University of New South Wales (UNSW), completed in 2017, and worked as a Research Associate there until December 2022. His research focuses on hardware security, particularly side-channel analysis attacks and countermeasures. Education: PhD, University of New South Wales (2017) Research Interests include: Side-channel analysis attacks (Power Analysis, EM Attacks, Fault Injection) Countermeasures (Balancing, Random Execution, Masking) On-chip sensors for FPGA monitoring FPGA reliability under power fluctuations Publication Trends reveal expertise in: Hardware Security (15/15 articles) FPGA Vulnerabilities (10/15 articles) Cryptographic Countermeasures (12/15 articles) Sensor Development (5/15 articles)

Christian FibichView profile

Researcher

• Fault-Tolerant FPGA Design
• Reliability Analysis of SRAM-Based FPGAs
• High-Level Synthesis

Christian Fibich is a Researcher and Lecturer at the Department of Electronic Engineering, University of Applied Sciences Technikum Wien, Austria. He leads the Research Group Embedded Systems, focusing on FPGA reliability and high-level synthesis. His roles include project management for R&D initiatives like VECS (2013-2018), INES (2018-2023), and the 2024 Drohnentechnik integration project. Fibich holds an MSc in Embedded Systems from Technikum Wien and has been active in the field since 2010. Research interests include fault-tolerant FPGA design, reliability analysis of SRAM-based FPGAs, and high-level synthesis optimization. His work emphasizes practical applications of open-source tools and automated design exploration. Recent projects explore temperature-dependent fault effects and drone integration in academic programs. Publications span FPGA reliability, fault injection methods, and embedded systems design, with a focus on open-source IP cores and hardware security. His contributions include Fiji (a fault injection tool) and HLShield (a reliability framework for HLS).

• Neuromorphic Computing
• Spiking Neural Networks
• Bio-inspired Artificial Intelligence
• +8 more

Dr James Knight is a Senior Research Fellow in Informatics at the School of Engineering and Informatics, University of Sussex. He is currently an EPSRC Research Software Engineering Fellow (2022–2026), leading research in neuromorphic computing and spiking neural networks. His work bridges computer science, neuroscience, and robotics, with a focus on bio-inspired artificial intelligence and computational modeling of insect cognition. Education: PhD in Computer Science, University of Manchester (2013–2016) MPhil in Advanced Computer Science, University of Cambridge (2012–2013) BEng in Electronic Engineering, University of Warwick (2003–2006) His research interests center on neuromorphic computing , spiking neural networks , and bio-inspired AI , particularly drawing insights from insect neuroscience to develop efficient and robust machine learning systems. He explores event-based vision, neural hardware acceleration, and computational models of insect navigation and perception. The 15 most recent publications (2024–2025) reflect a strong trend in developing and benchmarking neuromorphic algorithms, including training methods like Eventprop, hardware-software co-design (e.g., FeNN processor), and modeling biological systems such as insect central complex and mushroom bodies. These works span journals like Nature Communications , PLoS Computational Biology , and Neuromorphic Computing and Engineering , as well as IEEE and Springer conferences. Scientific Grants: Unlocking spiking neural networks for machine learning research (EPSRC, 2022–2026) – Principal Investigator ActiveAI – active learning and selective attention for robust, transparent and efficient AI (EPSRC, 2019–2022) – Research Team Member Dr Knight actively collaborates with leading researchers including Thomas Nowotny, Andrew Philippides, and Paul Graham. His work contributes to both theoretical advances in neural computation and practical applications in robotics and AI. He is involved in developing frameworks such as NeuroBench for standardized evaluation of neuromorphic systems. Laboratories and Research Teams: He is part of the neuromorphic computing and computational neuroscience research groups at the University of Sussex, contributing to interdisciplinary projects that integrate software engineering, AI, and biological modeling.

Jim HarkinView profile

Professor

• Embedded Systems
• Neural Networks
• Hardware Systems
• +5 more

Professor Jim Harkin serves as Head of the School of Computing, Engineering and Intelligent Systems at Ulster University's Magee Campus in Derry~Londonderry. He is a prominent member of the Computational Neuroscience and Neuromorphic Engineering team within the Intelligent Systems Research Centre (ISRC), where he leads cutting-edge research bridging biological neural processes with hardware implementations. Harkin's research focuses on developing intelligent embedded systems capable of self-repair under error conditions, drawing inspiration from neural network models. His work explores how computer models of neural networks can be mapped to hardware to build highly efficient and reliable embedded computers. Key innovations include Networks-on-Chip strategies and hardware implementation of self-repairing Spiking Neural Networks. His research spans multiple domains including fault tolerance, neuromorphic computing, and AI hardware acceleration, with applications in healthcare, structural monitoring, and energy systems. Analysis of his recent publications reveals a strong trend toward practical applications of neuromorphic computing, particularly in healthcare monitoring systems, structural health assessment, and energy-efficient computing. His work shows increasing integration of spiking neural networks with real-world hardware implementations, demonstrating a clear trajectory from theoretical models to deployable systems with commercial applications. Harkin has received numerous scientific accolades including the Life and Health Startup Company of the Year 2019 from InventNI Ulster Distinguished Learning Support Fellowship Multiple awards for innovative routing strategies in neural network hardware implementations Professor Harkin has secured significant research funding exceeding £3.5 million from diverse sources including EPSRC, MRC, Innovate UK, HSC R&D, InvestNI, and DEL. His grant portfolio demonstrates strong industry and healthcare sector engagement, particularly through his co-founded startup Respiratory Analytics which focuses on medical analytics. He has supervised numerous research students and has been instrumental in Ulster University's Computer Science submissions to major research assessment exercises including RAE 2008, REF2014, and REF2021. As Head of School and leader within the Intelligent Systems Research Centre, Harkin oversees multiple research teams focusing on computational neuroscience, neuromorphic engineering, and intelligent embedded systems. His lab has developed specialized FPGA-based platforms for simulating and implementing self-repairing neural networks, including the AstroByte multi-FPGA architecture for accelerated simulations of fault-tolerant spiking astrocyte-neuron networks.

• Integrated Circuits
• RF Circuit Design
• Low-Power Electronics
• +3 more

Jean-Baptiste Bégueret is a researcher with extensive contributions to integrated circuits , RF design , and low-power electronics . His work spans analog , digital , and mixed-signal systems.

Luciano OstView profile

Senior Lecturer

• Embedded Systems
• Hardware/Software Co-design
• Cybersecurity
• +7 more

Luciano Ost is a Senior Lecturer and Programme Director of the Computer and Electronic Engineering (CEE) Programme at the University of Leicester. He holds a Ph.D. in Computer Science from Pontifical Catholic University of Rio Grande do Sul (PUCRS), Brazil (2010). His research focuses on enhancing reliability, security, and performance of embedded and life-critical systems through innovative hardware/software co-design approaches. Key areas include fault tolerance in neural networks, radiation effects on embedded systems, and real-time control systems. Prior to Leicester, he worked at the University of Montpellier II (France) as an assistant professor and research assistant. He has authored/co-authored over 100 papers and two books, with notable contributions to soft error reliability assessment frameworks (e.g., SOFIA, gem5-FIM) and embedded system security solutions like BIDS for in-vehicle networks. His research spans topics like FPGA-accelerated intrusion detection (BNN-based), radiation resilience in IoT edge devices, and compiler optimization impacts on multicore reliability. He has conducted extensive studies using Geant4 simulations and virtual platforms for fault injection analysis.

Alexandre JoannouView profile

Researcher

• Computer Architecture
• Hardware Security
• Memory Safety
• +4 more

Dr. Alexandre Joannou is a Senior Research Software Engineer at the Department of Computer Science and Technology, University of Cambridge. His research focuses on secure hardware-software co-design, particularly in the CHERI (Capability Hardware Enhanced RISC Instructions) project. He specializes in computer architecture, memory safety, and RISC-V processors, with a focus on integrating security into low-level system components. His work spans theoretical contributions to capability-based systems and practical implementations in accelerators, GPUs, and embedded devices. Key areas include secure speculation, memory protection, and formal verification of hardware designs. Joannou's research has advanced temporal safety in heaps, compressed capabilities for efficiency, and architectural contracts to prevent vulnerabilities. His publications emphasize hardware security innovations, including CHERI-RISC-V integration, GPGPU memory protection, and randomized testing methodologies. Collaborations involve both academic and industry partners in secure computing ecosystems.

Hesham AlmataryView profile

Researcher

• Computer Security
• Operating Systems
• Computer Architecture
• +3 more

Hesham Almatary is a Researcher at the Department of Computer Science and Technology, University of Cambridge. He holds a PhD from the University of Cambridge on CHERI compartmentalisation for embedded systems. His research focuses on computer security, operating systems, systems software, and computer architecture, with contributions to open-source projects including Linux, seL4, RTEMS, and FreeRTOS. Education: PhD in Computer Science, University of Cambridge (CHERI Compartmentalisation for Embedded Systems) Research Interests: Secure embedded systems and operating systems CHERI architecture and compartmentalization techniques RISC-V processors and hardware validation Memory management and capability-based security Publications: Recent work includes studies on CHERI implementation in MMU-less Linux, embedded system security frameworks (CompartOS), and testing RISC-V processors. His contributions span both theoretical advancements in computer architecture and practical implementations in open-source software. Awards: No scientific awards explicitly mentioned. Advising/Grants: No advisees or grants listed in the provided information.

Omer KhanView profile

Professor

• Computer Architecture
• Parallel Processing
• Graph Intelligence
• +4 more

Dr. Omer Khan is a Professor of Electrical and Computer Engineering at the University of Connecticut (UConn), leading the Computer Architecture Group (CAG) and serving as Associate Director of the Connecticut Advanced Computing Center (CACC). His research focuses on computer architectures for high-performance applications, particularly graph intelligence, parallel processing, and secure processors. He holds a PhD from the University of Massachusetts Amherst and a BSc from Michigan State University. Education: PhD in Electrical and Computer Engineering, University of Massachusetts Amherst, 2009 BSc in Electrical and Computer Engineering, Michigan State University, 2000 Research Interests: Dr. Khan’s work addresses computational challenges in artificial intelligence, particularly graph-based data and multi-objective optimization. He develops architectures that exploit sparsity and parallelism to accelerate graph neural networks, secure processors against side-channel attacks, and ensure resilience in large-scale multicores. His research includes hardware-software co-design for thermal management, confidential computing, and algorithm-architecture co-optimization. Publications: His recent work spans parallel algorithms for graph intelligence (e.g., OPMOS, PruneGNN), secure multicore architectures (IRONHIDE, SSE), and GPU acceleration for GNN training. These contributions highlight advancements in efficiency, security, and scalability of modern computing systems. Awards & Grants: Principal Investigator of an NSF REU Site on Trustable Embedded Systems Security (2021–2025). His work has been supported by grants from NSF and industry partnerships. Advising & Mentoring: Guided over 20 graduate and undergraduate researchers, many of whom have secured roles at top tech firms (e.g., Qualcomm, Meta) or pursued advanced degrees at prestigious institutions. Labs & Teams: Leads the CAG at UConn, collaborating with industry and academic partners to advance next-generation computer architectures.

• Embedded Systems
• AI Algorithms
• FPGA/VHDL Design
• +5 more

Jürgen Wassner is a Professor of Edge Computing and Co-Head of the Competence Center for Intelligent Sensors and Networks at the Lucerne School of Engineering and Architecture (HSLU T&A). He holds a master's degree from Technical University of Dresden and a PhD from ETH Zurich. His career spans industry roles in Silicon Valley Group Inc. and telecommunication R&D before joining academia in 2007. His research focuses on embedded systems, AI at the edge, FPGA/VHDL design, real-time systems, and powerline communication . He leads projects such as 'Visual-Servoing Testbed with AI-Hardware in the Loop' and 'Low-Cost High-Performance Intelligent Camera for Space Debris Mitigation,' collaborating with companies like Diehl Aerospace. Recent publications emphasize wire fault detection using powerline communication, AI-based odor classification systems, and hardware acceleration for CNNs. His work bridges theoretical research with practical applications in avionics, rail freight, and space debris mitigation. Wassner advises Master of Science in Engineering students and has been recognized for his media engagement including a feature in the Luzerner Zeitung. He teaches Digital Design (FPGA, VHDL) and Digital Signal Processing , emphasizing hands-on implementation of cutting-edge systems.

• System-on-Chip (SoC) Design
• FPGA-Based High-Level Synthesis
• Real-Time Embedded Systems
• +5 more

Timo Hämäläinen is a Professor of Computer Engineering at Tampere University, leading the Unit of Computing Sciences within the Faculty of Information Technology and Communication Sciences. He is a core member of the System-on-Chip research group and the Computer Engineering Team, actively contributing to the System-on-Chip Hub initiative. His research focuses on System-on-Chip (SoC) design methodologies, FPGA-based high-level synthesis, real-time embedded systems, and open-source hardware-software co-design frameworks like RISC-V and HEVC encoding. He has pioneered work on agile SoC development processes and validation techniques for large-scale hardware systems. Key research areas include: High-level synthesis (HLS) optimization for FPGAs Real-time processor architectures and context-switching latency reduction Formal verification of IP-XACT-compliant SoC designs Resilient RISC-V MPSoC implementations Hardware-accelerated algorithms for signal processing and networking His recent publications (2023-2025) emphasize agile SoC development frameworks, hardware-software co-design for real-time systems, and validation methodologies for large-scale embedded systems. He has contributed to open-source projects like Kvazaar HEVC encoder and the Kactus2 IP-XACT toolchain. Academic advising includes students such as Santéri Mäki-Äijö (formal verification), Arto Oinonen (RISC-V tooling), and Sakari Lahti (processor modeling). His work integrates academic research with industrial collaboration through frameworks like the Fault-slip-Through quality assessment methodology.

• Computer Architecture
• Parallel Processing
• Networking Systems
• +3 more

Javier Verdu Mula is a Professor at the Departament d'Arquitectura de Computadors (Universitat Politècnica de Catalunya - UPC) and a key researcher at the CRAAX - Centre de Recerca d'Arquitectures Avançades de Xarxes . His work focuses on computer architecture, parallel processing, and networking systems. Fields of Research include RISC-V virtualization, multithreaded processor optimization, and performance analysis of stateful networking applications. Scientific Awards include the BDigital Global Congress (2015) and Wayra Barcelona (2012) recognitions. Collaborations span institutions like Barcelona Supercomputing Center and researchers such as Manuel Alejandro Pajuelo, Mateo Valero Cortes, and Mario Nemirovsky. His recent publications address RISC-V hypervisor extensions, deep packet processing in parallel architectures, and statistical thread assignment models. He also holds patents in hardware virtualization and resource control systems.