Philip Ginzboorg is a Professor of Practice at the Department of Computer Science, Aalto University. His research focuses on advanced security and privacy challenges in modern networking systems, with a particular emphasis on 5G, edge computing, and disruption-tolerant networks. His recent work explores AKMA (Authentication and Key Management for Access) protocols for secure mobility in 5G edge computing environments, privacy-preserving authentication mechanisms , and fragmentation algorithms for disrupted links . Collaborations with Valtteri Niemi, Jörg Ott, and other researchers highlight his interdisciplinary approach. Key publication trends span 5G security , privacy in pervasive networks , DTN (Disruption-Tolerant Networking) , and cryptographic protocols for constrained systems . Notable contributions include defenses against downgrade attacks on identity privacy and novel approaches to IMSI-based routing.
Marco Vacca is an Associate Professor in the Department of Electronics and Telecommunications (DET) at Politecnico di Torino and a member of the Interdepartmental Center PIC4SeR - PoliTO Interdepartmental Centre for Service Robotics. His work bridges electronics, nanotechnology, and computing architecture with a focus on innovative solutions to the memory wall problem. His research spans Logic-in-memory computing, Machine learning hardware acceleration, and Nanocomputing with specific emphasis on circuit architectures for probabilistic computing, magnetic devices, hybrid technologies integration, and CAD tools for emerging technologies. Dr. Vacca leads research in RISC-V extensions, hardware accelerators for AI, and autonomous robot systems for agricultural applications through the VLSILAB research group. Recent publications reveal a strong trend toward solving fundamental computing challenges through nanoscale innovations, particularly in memory-centric architectures, molecular field-coupled computing, and novel transistor technologies. His work demonstrates how logic-in-memory approaches can overcome traditional von Neumann limitations while improving energy efficiency for AI workloads. Editorial board member of ELECTRONICS (2021-2023) Program committee member for Design, Automation and Test in Europe Conference (DATE) 2020-2021 Dr. Vacca supervises PhD student Alessandro Varaldi working on 'Hardware AI Accelerators for Automotive Applications' and has led significant research projects including 'Device for Storage and Processing Data and Related Method' (2020-2021) and 'Quantum Computing and Quantum Communication: State of the Art and Applications in the Telco Sector' (2020). His grant portfolio shows strong industry and competitive funding support. As a core member of the VLSILAB research group, Dr. Vacca contributes to advancing VLSI theory and design applications with particular focus on implementing Big Data, Machine Learning, and Neural Networks in specialized hardware architectures that push the boundaries of conventional computing.
Prof. Dr.-Ing. Holger Blume serves as Vice President for Research and Transfer at Leibniz University Hannover while maintaining his academic position as Professor in the Architectures and Systems Section within the Faculty of Electrical Engineering and Computer Science. He holds multiple leadership positions including Chairperson of the Research Commission and Central Ethics Committee, Executive Board member of eNIFE (Leibniz Research Initiative for Neurosciences), and membership in both the Laboratory of Nano and Quantum Engineering and L3S Research Centre. His research interests span computer architecture, hardware design, signal processing, AI accelerators, hearing aid technology, and biomedical engineering. His work bridges theoretical computer science with practical applications in automotive systems, medical devices, and quantum engineering. Professor Blume's research demonstrates strong interdisciplinary connections between electrical engineering, computer science, and biomedical applications, with particular emphasis on hardware-oriented solutions for real-world problems. Analysis of his recent publications (2023-2025) reveals a strong focus on hardware acceleration for AI and signal processing applications, particularly in automotive radar/LiDAR systems and hearing aid technology. His work shows consistent innovation in RISC-V processor design, specialized hardware for mathematical functions, and biomedical applications of engineering principles. The research demonstrates a clear trajectory toward energy-efficient, specialized computing architectures for specific application domains. As Vice President for Research and Transfer, Professor Blume oversees significant research initiatives at Leibniz University Hannover, which hosts multiple Clusters of Excellence including PhoenixD (Photonics, Optics, and Engineering), QuantumFrontiers, and Hearing4all. The university participates in numerous collaborative research centers and junior research groups funded by DFG, BMBF, and EU programs. Professor Blume is actively involved in multiple research facilities including the Laboratory of Nano and Quantum Engineering and the L3S Research Centre. His work connects with Leibniz University's research focuses on optical technologies, quantum optics and gravitational physics, and biomedical research and technology. His leadership positions indicate strong involvement in shaping the research strategy and ethical framework of the university's scientific endeavors.
Jonathan Balkind is an Assistant Professor in the Department of Computer Science at the University of California, Santa Barbara (UCSB). His research focuses on the intersection of computer architecture, programming languages, and operating systems, with an emphasis on pragmatic system design and open-source hardware. He leads the ArchLab at UCSB and is affiliated with the OpenPiton project, an open-source manycore research framework. Education includes a PhD and MA in Computer Science from Princeton University (adviser: Prof. David Wentzlaff), an MSci in Computing Science from the University of Glasgow (advisers: Prof. Joseph Sventek and Dr. John O'Donnell), and exchange studies at UCSB. His work has been supported by awards such as the NSF Early CAREER Award (2023) and the Open Hardware Trailblazer Fellowship (2022). Research interests span heterogeneous computing, cache-coherent systems, FPGA integration, and domain-specific architectures. Notable projects include the 25-core Piton chip, the CIFER SoC with embedded FPGA, and the DECADES manycore processor. Recent publications address fused-kernel operating systems (Stramash), control logic synthesis, and hyperloop data-center architectures. His awards reflect contributions to open-source hardware and academic mentorship, including Siebel Scholarship (2018), Gordon Y.S. Wu Fellowship (2013–2017), and multiple teaching/research recognitions. He actively collaborates with industry (e.g., Microsoft Research, ARM) and advises on open-source projects.
Wim Dehaene is a Full Professor at KU Leuven's Department of Electrical Engineering (ESAT), Faculty of Engineering Science. His research focuses on advanced digital circuit design, in-memory computing, and biomedical applications. He leads projects like Variability Resilient Design of In-Memory Compute Architectures and DECIBUS: Communication in the Body by Ultrasound . Member of MICAS (Micro Electronics and Sensors) division Head of Electronic Circuits and Systems (ECS) group Active in interdisciplinary education and curriculum development His work bridges flexible electronics, low-voltage design, and AI accelerators, with recent publications on neural network hardware and biomedical wearables. Collaborations span institutions like IEEE and projects involving RISC-V controllers and IGZO TFT-based SRAM. Teaching roles include courses on digital integrated circuits, biomedical measurements, and interdisciplinary design methodologies. He contributes to research training in biomedical technology and participates in IEEE conferences as organizer and speaker.
Miquel Moreto Planas is a Senior Lecturer in the Department of Computer Architecture at the Barcelona School of Informatics, Universitat Politècnica de Catalunya (UPC). He is also affiliated with the Barcelona Supercomputing Center (BSC-CNS), a leading institution in high-performance computing. His academic profile is deeply rooted in computer architecture and high-performance computing, with a strong emphasis on practical and theoretical advancements in multicore systems, memory management, and hardware acceleration. His research interests span a wide range of topics including computer architecture, high-performance computing, multicore and manycore systems, cache and memory management, hardware acceleration for genomics and AI, RISC-V processor design, processing-in-memory, interconnection networks, and real-time systems. These interests are reflected in his extensive publication record and collaborative projects. The most recent articles highlight a significant trend toward interdisciplinary research, particularly the application of advanced computer architecture techniques to bioinformatics and healthcare. Key themes include the acceleration of genomic sequence alignment using novel hardware such as processing-in-memory, the development of benchmarks for ARM-based HPC systems in genomics, and the creation of AI-based 3D decision support tools for neurosurgical applications. His work also continues to advance core computer architecture topics like cache management, power-aware resource allocation in heterogeneous systems, and the design of secure, post-quantum cryptographic hardware based on RISC-V. Fulbright Award 2011 HiPEAC Paper Award HiPEAC Paper Award 2024 HiPEAC Paper Award Moreto has been a principal investigator or key contributor to multiple competitive R&D+i projects, such as the STRATUM project for neurosurgical tools, REDIOH for open hardware, and the Laboratorio Zettaescala de Barcelona. He has advised several doctoral students, including López, G., Kostalampros, I., and Haghi, A., and is a core member of the CAP (High Performance Computing) research group at UPC. His work is characterized by strong collaborations with leading researchers like Mateo Valero, Eduard Ayguadé, and Jesús Labarta, often bridging the gap between UPC and BSC-CNS. His laboratory and team affiliations are centered around the CAP group and the Barcelona Supercomputing Center, where he contributes to cutting-edge research in high-performance and embedded computer architectures. His recent work on the BIMSA accelerator and the STRATUM project demonstrates a clear future direction toward applying high-performance computing solutions to critical problems in genomics and medicine.
Tiago Manuel Ribeiro Gomes is an Assistant Professor at the Department of Industrial Electronics within the School of Engineering at the University of Minho, Portugal. He is also a Senior Researcher at Centro ALGORITMI and a member of both the IE R&D Group and the ESRG R&D Lab. Holding a Ph.D. in Electronics and Computers Engineering, his research focuses on embedded real-time systems, computer architectures, and hardware/software co-design for IoT devices. Academic Degree: Ph.D. in Electronics and Computers Engineering Current Position: Assistant Professor, School of Engineering, University of Minho Gomes has led extensive research in IoT systems over 15 years, particularly in hardware acceleration for automotive LiDAR sensors, secure embedded systems, and efficient OS frameworks for low-end devices. His work includes the EU-funded CROSSCON project and spans hardware-assisted security, dynamic binary translation, and wireless sensor networks. Recent publications highlight his expertise in automotive sensor technology, with articles like FOG-Zip for LiDAR compression, SecureQNN for TinyML security, and Hardware-Assisted Range Image Generation for LiDAR processing. His work bridges IoT, embedded systems, and cybersecurity, focusing on real-time performance and hardware-software co-design. Projects include the development of reliable/secure automotive sensor solutions and EU project CROSSCON. He contributes to open-source frameworks like UTango for IoT security and investigates heterogeneous fault tolerance architectures using Arm/RISC-V processors. Labs: IE R&D Group, ESRG R&D Lab Education: Ph.D. in Electronics and Computers Engineering, Master’s in Telecommunications Engineering (both from University of Minho)
Keiji Kimura is a Professor in the Department of Computer Science and Engineering at Waseda University's Faculty of Science and Engineering, School of Fundamental Science and Engineering. He earned his Doctor of Engineering from Waseda University and has held academic positions at the university since 1999, progressing from Research Associate to Assistant Professor (2004-2005), Associate Professor (2005-2012), and Professor (2012-present). He is affiliated with multiple professional organizations including ACM, IEEE Computer Society, The Institute of Electronics, Information and Communication Engineers, and Information Processing Society of Japan. His research focuses on computer architecture, particularly parallel computing systems and compiler technology. Kimura has made significant contributions to the development of the OSCAR (Optimally Scheduled Advanced Multiprocessor) automatic parallelizing compiler framework. His work spans multiple areas including multicore processor architecture, power reduction techniques for embedded systems, non-volatile memory systems, and parallelization methods for heterogeneous architectures. His research interests specifically include Multiprocessor Architecture and Parallelizing Compiler development, with applications in real-time systems and energy-efficient computing. Analysis of his recent publications reveals a strong focus on practical implementations of parallel computing technologies across diverse hardware platforms including RISC-V, ARM, and heterogeneous multicore systems. His work demonstrates a consistent trajectory from theoretical compiler development toward practical applications in embedded systems, security, and non-volatile memory technologies. The publications show increasing emphasis on RISC-V architecture, persistent memory programming, and power-efficient computing solutions. MEXT Award for Science and Technology (Research category), 2014.04 Ministry of Education, Culture, Sports, Science and Technology (MEXT) Kimura has served on numerous prestigious conference program committees including PACT, IPDPS, HPCA, and LCPC. His research has been supported through collaborations with major technology companies and government initiatives such as the METI/NEDO project entitled "Multicore Technology for Realtime Consumer Electronics." His work with the OSCAR compiler framework has demonstrated significant performance improvements and power reductions in real-world applications. He leads research in the APAL laboratory (http://www.apal.cs.waseda.ac.jp/) at Waseda University, focusing on advanced parallel processing technologies. His team works on compiler-directed approaches to solve challenges in heterogeneous multicore architectures, with particular emphasis on making parallel programming more accessible while optimizing for both performance and power efficiency. Current research directions include RISC-V secure boot verification, non-volatile memory systems, and GPU-based persistent memory solutions.
Frank Hannig is a Professor at the University of Erlangen-Nuremberg, Germany, specializing in computer architecture and high-performance computing. His research focuses on FPGA acceleration, hardware-software co-design, neural network optimization, and embedded systems. He has collaborated extensively with co-authors such as Jürgen Teich and Oliver Reiche, producing over 200 publications since 2001. His work emphasizes domain-specific languages (DSLs) for image processing (e.g., Hipacc) and compiler optimizations for FPGAs. Key contributions include techniques for quantized neural networks on microcontrollers, CGRA toolchain evaluation, and efficient mapping of CNNs onto processor arrays. Hannig also explores energy-efficient architectures and reconfigurable computing for emerging applications like edge AI and automotive systems. Publications span conferences like ASAP, FPL, and ARC, reflecting his interdisciplinary approach to bridging algorithm design and hardware implementation. His research often addresses practical challenges in deploying machine learning models on resource-constrained devices while maintaining performance and energy efficiency.
Sam Amiri is a Lecturer in Microelectronics / Embedded Electronics at Loughborough University. He holds a BSc in Software Engineering (2007, Iran), M.Sc. in Embedded Systems (2010, Masaryk University), and Ph.D. in Electrical/Electronic Engineering (2014, Masaryk University). Prior to his current role, he worked as a Researcher at Queen’s University Belfast (2015-2017) and the University of Bristol (2017-2018). His research focuses on hardware design, embedded systems, signal/image processing, and FPGA-based solutions for real-time systems. Key research areas include intrusion detection systems for vehicular networks using binarized neural networks, RISC-V processor optimization for neural networks, and FPGA-based acceleration of CNN models. His work also explores reliability engineering in wind turbine drivetrains and heterogeneous computing architectures combining FPGAs with CPUs. Publications span topics like embedded cybersecurity, low-power edge computing, and hardware-software co-design for real-time applications. His recent work emphasizes lightweight neural networks on constrained hardware and fault tolerance in aerospace systems. No specific awards or grants are listed in the provided information.
Luca Crocetti is an Assistant Professor at the Department of Information Engineering (DII) of the University of Pisa. His research focuses on hardware security, embedded systems, and VLSI design for applications in Automotive, Space, IoT, and High-Performance Computing. He specializes in cybersecurity modules for automotive systems, space-grade FPGAs, and digital signal processing in satellite communications. His teaching includes electronics laboratory practices and cybersecurity principles, with a recent course on hardware's role in security for the Ph.D. program in Information Engineering. He has authored over 20 publications and holds 3 patents (1 national, 2 international), with notable work on cryptographic cores, secure boot mechanisms, and automotive cybersecurity. His contributions span efficient hardware implementations of AES, SHA-3, and other cryptographic algorithms, emphasizing compliance with standards like CCSDS for space applications. His research trends highlight a focus on hardware-efficient architectures, modular design for scalability, and robust security protocols for trusted environments. Notable publications address cryptographic co-processors for the European Processor Initiative, PUF-based security for RISC-V, and FPGA-based RNGs. While no formal awards are listed, his active role in cutting-edge cybersecurity projects underscores his contributions to embedded and space system security. His teaching and research emphasize hands-on lab experiences and real-world applications of hardware security principles.
Federico Reghenzani is an Assistant Professor at Politecnico di Milano in the Department of Electronics, Information and Bioengineering. His research focuses on computer science, embedded systems, fault tolerance, high-performance computing, real-time systems, and compiler technology. He leads the HEAP Lab where his team investigates reliability engineering and hardware-software co-design for safety-critical applications. Reghenzani's research examines software-based approaches to hardware fault tolerance, compiler technologies for reliability enhancement, and resource management in high-performance computing environments. His work has significant applications in aerospace systems, real-time embedded platforms, and next-generation computing architectures. His publications demonstrate a consistent focus on improving system reliability through compiler techniques, fault injection methodologies, and hardware-software co-design. The research spans theoretical frameworks, practical implementations, and experimental validation across diverse computing environments.
Timothy Jones is a Professor of Computer Architecture and Compilation at the University of Cambridge Computer Laboratory, with a research focus on extracting parallelism (thread-level, data-level, memory-level) through compilers, binary translators, and microarchitectures to enhance performance, energy efficiency, and reliability. He is also a Fellow and 1956 College Lecturer at Gonville and Caius College, serving as joint Director of Studies for Computer Science. Teaching: Advanced Topics in Computer Architecture (MPhil ACS, Part III), Introduction to Computer Architecture (Part IB), Optimising Compilers (Part II) Research Themes: Computer Architecture, Security, Programming Languages, Parallel Computing Contact: Room SC03, Department of Computer Science and Technology, William Gates Building, Cambridge CB3 0FD His recent publications emphasize heterogeneous parallelism, fault tolerance, speculative execution, and security implications in compiler and microarchitecture design. Notable trends include integrating fine-grained security analysis into superscalar cores and optimizing GPU architectures for scalarization and memory bypassing. He is active on Twitter ( @TJonesCL ) and maintains an Erdős Number of 4.
Francesco Regazzoni is a Senior Researcher at the Faculty of Informatics, Università della Svizzera italiana (USI), and affiliated with the Dalle Molle Institute for Artificial Intelligence (IDSIA USI-SUPSI). His work bridges embedded systems, cybersecurity, and artificial intelligence, with a focus on securing hardware and cyber-physical systems. Research Interests: His expertise spans embedded and cyber-physical systems security, side-channel attacks, post-quantum cryptography, hardware trojans, random number generators, and the security of AI and approximate computing. He also contributes to hardware/software co-design and operating systems security. The analysis of his recent publications reveals a consistent focus on hardware and system-level security , particularly in resource-constrained environments like IoT and embedded devices. His work integrates machine learning for attack detection and applies formal methods to ensure trust in hardware. A growing emphasis is placed on securing AI systems from physical and adversarial threats. Scientific Contributions: Over 100 peer-reviewed publications One book and one patent Extensive international collaboration (Belgium, Netherlands, USA, Switzerland, Singapore) Advising and Grants: While specific advisees and grants are not listed, his leadership in funded research projects and involvement with ALaRI and IDSIA suggest active mentorship and project coordination. His work has been supported by industry (e.g., ST Microelectronics, HP), the Swiss National Foundation, and the European Union. Labs and Teams: He is part of the Graph Machine Learning Group (GMLG) at IDSIA, which evolved from the Advanced Learning and Research Institute (ALaRI). This group focuses on graph machine learning, reinforcement learning, and dynamical systems, particularly in non-stationary environments.
Johannes Geier is a Researcher at the Chair of Design Automation at the Technical University of Munich (TUM). His work focuses on electronic design automation, fault injection simulations, and security countermeasures for RISC-V processors. University: Technical University of Munich Department: Chair of Design Automation Email: johannes.geier@tum.de Research Interests Electronic Design Automation (EDA) for analog and digital circuits Fault tolerance and reliability in RISC-V architectures Security analysis of post-quantum cryptographic systems Timing analysis and microfabrication techniques Optical Networks-on-Chip (NoC) and emerging technologies Compiler-assisted hardware security implementations Recent Research Trends Specializes in fault injection methodologies for hardware security validation Develops open-source tools like vRTLmod for RTL simulation acceleration Explores RISC-V vector extensions for post-quantum cryptography Investigates differential fault effect equivalence checks for efficiency Designs compiler-based security countermeasures against instruction skip attacks Works on concurrent multi-node XCP proxy server architectures
