Timothy Harris is an Affiliated Lecturer at the University of Cambridge's Department of Computer Science and Technology, where he jointly teaches courses on multicore semantics and programming. Currently, he works at OpenAI, focusing on performance optimization for GPU inference of large language models, including the Azure OpenAI Service. Previously, he held roles at Microsoft, AWS, Oracle Labs, and was a faculty member at the University of Cambridge (2000–2004). His research spans distributed systems, runtime systems, operating systems, and high-performance computing, with an emphasis on scalability and performance. He contributed to projects like the Xen hypervisor and the Barrelfish research OS. Key research interests include distributed training of PyTorch models in the ONNX runtime, large-scale storage performance with Amazon S3, and runtime systems for in-memory graph analytics. His work often bridges 'big data' and high-performance computing techniques. Notable contributions include the book Transactional Memory (2010) and the Barrelfish OS, alongside numerous publications in top-tier conferences like SOSP, ASPLOS, and EuroSys. He has served as PC chair for ISMM 2025, VEE 2017, and EuroSys 2015, reflecting his leadership in the systems research community. His awards include a Best Paper Award at PACT 2010. Beyond academia, Harris is an avid hiker, aiming to complete the UK coastline, and maintains a photography portfolio at tlhphotography.uk .
Yonghwi Kwon is a Visiting Assistant Professor in the Department of Computer Science at the University of Virginia. His research focuses on software systems security, cyber forensics, and software engineering. He received the CAREER Award for developing dynamic defenses against cyber threats. His work emphasizes securing software from cyber attacks, recovering forensic evidence, and improving software testing and reverse engineering techniques. Key research areas include memory safety mechanisms, automated vulnerability detection in web applications and mobile systems, and forensic analysis of phishing campaigns. He has pioneered frameworks like CMASan for memory allocator-aware sanitization and Racedb for detecting race conditions in database-backed systems. His contributions span cloud security automation, kernel exploitation analysis, and embedded system fuzzing. Notable achievements include the 2025 CAREER Award supporting his dynamic defense research, and impactful publications in areas like Android information leakage detection (DryJIN), Bluetooth protocol fuzzing (BTFuzzer), and autonomous driving bug discovery (Drivefuzz). His work bridges theoretical computer science with practical cybersecurity solutions.
Chester Rebeiro is an Associate Professor at the Department of Computer Science and Engineering within the Indian Institute of Technology Madras . His work spans hardware and software security with a focus on cryptographic implementations and microarchitectural vulnerabilities. Research interests include hardware security, applied cryptography, side channel analysis, and operating system security. He develops frameworks for automatic vulnerability detection and mitigation in cryptographic systems. Editorial Board: Associate Editor at Journal of Hardware and Systems Security (Springer, 2021-2024) Conference Leadership: General Co-Chair for SPACE 2024, Program Co-Chair for ATS 2024, and Program Co-Chair for INDOCRYPT 2023 Professional Activities: Organizer of e-CTF Embedded Capture The Flag and contributor to cybersecurity workshops across India and abroad Scientific contributions highlight two major awards: a Distinguished Paper Award at USENIX Security 2024 and a Best Paper Award at IEEE HOST 2020. His research focuses on practical security solutions for processors and cryptographic systems. Advising includes mentoring 11 PhD students and 7 MS by Research candidates, with notable co-guided projects in fault attack detection and side-channel mitigation. He actively contributes to educational initiatives through courses on Secure Processor Microarchitecture and Operating Systems.
Dr. Andrea Bastoni is a Postdoctoral Researcher and Research Fellow at the Chair of Cyber-Physical Systems in Production Engineering at Technical University of Munich (TUM), Faculty of Mechanical Engineering. He is also the CTO and co-founder of Minerva Systems , developing operating system solutions for AI-ready embedded applications. His expertise spans real-time operating systems, cyber-physical systems, and predictable system design for heterogeneous platforms. His research focuses on enhancing predictability of memory hierarchies in complex SoCs through techniques like memory bandwidth regulation and cache partitioning. This work has industrial applications in safety-critical domains such as avionics and railways, where he contributes to certifiable hypervisors and operating systems. As former Software Architect of the PikeOS hypervisor at SYSGO GmbH (2012-2020), he specialized in DO-178C, IEC 61508, and EN 50128 standards. His academic background includes a Ph.D. in Computer Engineering from the University of Rome Tor Vergata (2007-2011), where he developed LITMUS^RT as part of UNC's Real-Time Systems Group during a visiting researcher period (2009-2010). His publications reflect ongoing work on Multicore Real-Time Scheduling , Mixed-Criticality Task Isolation, and Arm DynamIQ shared unit analysis. He actively participates in program committees for conferences like RTSS, DSN, and DATE.
Nuno Santos is an Associate Professor in the Department of Computer Science and Engineering at Instituto Superior Técnico (IST), University of Lisbon, and a senior researcher at INESC-ID Lisbon. He leads the SysSec team, focusing on systems security and privacy. His research spans secure enclaves, network security, and censorship-resistant systems. Education: Ph.D. in Computer Science (2013) from Max Planck Institute for Software Systems (MPI-SWS) in affiliation with Saarland University. Visiting research stints at Vrije Universiteit Amsterdam (2018) and Technical University of Munich (2024). Research Interests: Systems security, privacy, trusted execution environments (TEEs), network security, censorship resistance, AI security, and secure cloud computing. He has pioneered work on mitigating vulnerabilities in TrustZone-based TEEs and enhancing confidential computing. Publications: Over 30+ peer-reviewed articles in top-tier venues like S&P, USENIX Security, CCS, and NDSS. Recent trends focus on AI-driven security (e.g., automated exploit generation, prompt-to-SQL injections) and confidential computing (e.g., AMD SEV-SNP analysis). Awards: IST Outstanding Teaching Award (2019/2020), 2024 Prémio Científico Universidade de Lisboa/Caixa Geral de Depósitos. Advising & Grants: Supervised MSc theses in areas like AI-powered vishing attacks and confidential VMs. Active in conference organization (e.g., USENIX Security’25 Vice Chair, IEEE EuroSP’26 Co-Chair). Labs/Teams: Leads the SysSec team at INESC-ID Lisbon, collaborating on projects like AnyTEE (TEE framework) and FlowLens (network security tool).
Dr. John Wickerson is an Associate Professor in the Circuits and Systems group at the Department of Electrical and Electronic Engineering, Imperial College London. His research focuses on improving the reliability of high-performance computing through formal methods, with contributions to high-level synthesis, memory models, and concurrency verification. He holds leadership roles including Course Director for the Electrical and Information Engineering degree and Deputy Tutor for PhD students. Research Interests: Formal Verification of Hardware/Software Systems High-Level Synthesis (HLS) and FPGA Compilation Weak Memory Models and Concurrency Semantics Fuzz Testing for Hardware Tools Compiler Optimization and Correctness Digit Elision and Arbitrary-Precision Arithmetic Notable Achievements: Best Paper Award at EuroSys 2024 (database isolation validation) Pioneered formal methods for HLS tools (e.g., QuteFuzz, C4) Co-developed the C4 C compiler concurrency checker Published over 60 peer-reviewed papers across top venues (ASPLOS, PLDI, FPGA) Lab/Team: Part of the Circuits and Systems group at Imperial College, collaborating with industry partners like Kaihong Yann and ARM.
Kyprianos Papadimitriou is a Researcher at the Microprocessor and Hardware Laboratory within the School of Electrical and Computer Engineering at the Technical University of Crete . He holds a PhD in Electronic and Computer Engineering (2012) and has been involved in teaching laboratory courses such as Logic Design , Computer Architecture , and VLSI/ASIC Circuit Design . Research Areas : His work spans Reconfigurable Systems , Hardware Design , Computer Architecture , RFID Systems , and Real-Time Systems . He has developed innovative approaches in FPGA-based dynamic reconfiguration, MPSoC security, and 3D stereo vision for surveillance. Key Trends : Runtime reconfiguration for FPGAs Security frameworks for NoC-based MPSoCs Low-cost embedded vision systems Optimization of reconfiguration overhead Hardware task scheduling methodologies Genetic algorithm implementations on FPGAs Scientific Contributions : 1 USA patent (2005) Co-author of VLSI-SoC 2013 paper nominated for 1st Prize Active member of scientific committees (FPL, ReConFig) Peer reviewer for IEEE, Elsevier, and Springer journals Session chair at IEEE CNS and HPCC conferences Grants & Projects : Participated in competitive European and national programs, serving as scientific manager, coordinator, and technical coordinator. Developed spin-off company (2003-2005) to commercialize master's thesis research. Laboratory & Teaching : Affiliated with the Microprocessor and Hardware Laboratory , focusing on practical training in digital systems, processor-based systems, and VLSI design.
Martin Berzins is a Professor of Computer Science at the University of Utah, affiliated with the School of Computing and the Scientific Computing and Imaging (SCI) Institute. His research focuses on parallel scientific computing, numerical methods for partial differential equations, and high-performance computing frameworks. He is a leading developer of the Uintah framework, a scalable simulation tool used for large-scale engineering and scientific problems. Research Interests : Parallel algorithms, adaptive mesh refinement, material point method (MPM), exascale computing, computational fluid dynamics, and performance portability. His work emphasizes scalable software solutions for complex multiscale and multiphysics simulations, with applications in environmental modeling, explosive detonation analysis, and computational mechanics. Recent articles highlight advancements in Uintah's portability to exascale systems, error estimation in MPM, and high-order numerical methods. Berzins has contributed significantly to the development of task-based parallelism strategies and heterogeneous computing optimizations. His research bridges theoretical numerical analysis with practical large-scale computational challenges. Collaborations include DOE projects on hazard analysis and exascale computing. He has pioneered the integration of runtime systems like Hedgehog with Uintah to enhance scalability on modern architectures. His work ensures computational frameworks remain viable for emerging hardware trends, emphasizing both algorithmic innovation and software engineering rigor.
Herman Bruyninckx is a Part-Time Full Professor at Eindhoven University of Technology (TU/e) in the Mechanical Engineering department, specifically within the Control Systems Technology group and EAISI High Tech Systems initiative. He also serves as a professor (Hoogleraar) at KU Leuven in Belgium. Academic focus on robotics, control systems, and multi-agent coordination Active research in model predictive control , semantic mapping , and dynamic constraint algorithms Recent publications address industrial automation , agro-food robotics , and haptic technology Research Highlights : Developed hybrid decision-making frameworks for multi-agent navigation Innovated swing-free control methods for robotic pick-and-place operations Formulated constrained dynamics algorithms with LQR-Gauss principle integration Created ExoTen-Glove for haptic feedback in virtual environments Collaborative Projects : Coordinated with researchers like René van de Molengraft , Elena Torta , and Koen de Vos Contributed to NWO/TTW FlexCRAFT project for cognitive robotics in agro-food technology
Dr. Yu Huang is an Assistant Professor in the Department of Computer Science at Vanderbilt University's School of Engineering, with a secondary appointment in the Department of Teaching and Learning at the Peabody School of Education. She is affiliated with the Institute for Software Integrated Systems, the Frist Center for Autism and Innovation, the Vanderbilt Lab for Immersive AI Translation (VALIANT), and the Vanderbilt LIVE Learning Innovation Incubator. Her academic journey began with a BS in Aerospace Engineering from Harbin Institute of Technology in China (2011), followed by an MS in Computer Engineering from the University of Virginia (2015), and culminated with a PhD in Computer Science and Engineering from the University of Michigan in 2021 under Professor Westley Weimer. Dr. Huang's research bridges human cognition and machine intelligence to enhance software development. Her work spans software, hardware, AI, medical imaging (fMRI/fNIRS), eye tracking, and mobile sensing through collaborations with Security, Education, Psychology, and Neuroscience researchers. She leads the MIND Lab (Mixed INtelligence Development for programming lab), investigating programming expertise formation, code comprehension processes, cognitive error patterns, and diversity in programming communities. Her innovative approach combines empirical human studies with AI model development to create more effective programming tools. Her recent publications reveal a growing emphasis on leveraging human attention data to improve code language models, analyzing cognitive biases in security contexts, and examining social factors in technical communication. The research shows strong interdisciplinary connections between neuroscience, psychology, and software engineering, with increasing applications of LLMs in developer tooling. Dr. Huang's work consistently demonstrates how understanding human cognition can inform better AI systems for programming tasks. Dr. Huang has received numerous prestigious recognitions including the 2025 ICPC Vaclav Rajlich Early Career Achievement Award and three ACM SIGSOFT Distinguished Paper Awards (ICSE 2019, FSE 2023, ICSE 2024). Her lab has earned the Best Presentation Award at GI2024, while her students have received the Richard Bennett/Dorothy Danforth Compton Prize scholarship and the C. F. Chen Best Paper award. She actively mentors a diverse team of graduate students (Yifan Zhang, Zach Karas, Zihan Fang, Yueke Zhang, Jiahao Zhang) and undergraduate researchers, with many former students advancing to top institutions (Stanford, Harvard, Duke, UC Berkeley) and organizations (NASA JPL). Her research is supported by a 4-year NSF grant, GitHub Tech for Social Good funding, and the Provost's Faculty Immersion Vanderbilt Grant, enabling comprehensive studies of human-AI collaboration in software engineering. The MIND Lab maintains a strong collaborative culture, frequently working with Professor Kevin Leach's research group and organizing retreats to locations like Radnor State Park and the Great Smoky Mountains. This environment fosters innovation at the intersection of human cognition and software engineering while supporting the professional development of emerging researchers in the field.
Prof. Jörg Henkel serves as Professor and Head of the Chair for Embedded Systems (CES) at Karlsruhe Institute of Technology (KIT), Germany. Previously a Senior Research Staff Member at NEC Laboratories Princeton, he holds a PhD from Braunschweig University (Summa cum Laude) and directs major research initiatives including the DFG's SPP 1500 program on 'Dependable Embedded Systems'. Research Focus: His work centers on embedded systems dependability , low-power design , and adaptive computing architectures . Through the SPP 1500 program and TR89 Collaborative Research Center, he pioneers fault-tolerance techniques and runtime adaptation for safety-critical applications, addressing energy efficiency challenges in hardware/software co-design. Scientific Recognition: IEEE Fellow (for contributions to low-power dependable embedded systems) Multiple Best Paper Awards (DATE 2008, ICCAD 2009, Codes+ISSS 2011/2014/2015) DAC 2014 Designer Track Best Poster Award DATE 2013 Best IP Award Leadership & Service: As Editor-in-Chief of IEEE Design&Test Magazine and former ACM TECS EiC, he shapes scholarly discourse. He has chaired premier conferences (ICCAD 2012/2013, ESWeek 2016) and delivered 10+ keynotes on embedded systems reliability. His DFG-coordinated projects secure substantial funding for national collaborative research. Technical Infrastructure: Leads the Chair for Embedded Systems (CES) within KIT's Institute of Technical Informatics, driving innovation in hardware/software co-design and invasive computing through the TR89 consortium.
Chang Xu is a Professor and Ph.D. supervisor at Nanjing University, affiliated with the State Key Laboratory for Novel Software Technology, School of Computer Science, and Institute of Computer Software (ICS). He has been a full-time faculty member since 2010, when he joined as an associate professor and was later promoted to full professor in 2015. Education: Ph.D. from The Hong Kong University of Science and Technology (HKUST) in 2008 (advisor: Prof. S.C. Cheung) M.Eng. from Institute of Software, Chinese Academy of Sciences (ISCAS) in 2003 B.Eng. from University of Science and Technology of China (USTC) in 2000 Research Interests: Professor Xu's research focuses on big data software engineering, intelligent software testing and analysis, and adaptive and autonomous software systems. His recent work centers on constructing and providing runtime support for intelligent software in open environments, with emphasis on inconsistency detection and resolution for environments, and quality assurance for adaptive, concurrent, learning-based, smartphone-based, and spreadsheet-based applications. His work bridges theoretical foundations with practical applications in software engineering, particularly in program analysis, software testing, and self-adaptive systems. Scientific Awards: ACM SIGSOFT Distinguished Paper Award from ICSE 2025 Best Student Paper Award from EUROSYS 2025 ACM Distinguished Member in 2024 Best Paper Award from SOSP 2023 Best Paper Candidate from ISSRE 2022 Yangtze River Scholar by the Ministry of Education in 2021 Multiple ACM SIGSOFT Distinguished Paper Awards from conferences including ASE, ICSE National Science and Technology Progress Award (Second Class) in 2011 Academic Service and Advising: Professor Xu has served on numerous program committees for top software engineering conferences including ICSE, ASE, ESEC/FSE, and ISSTA. He is an editorial board member for several journals including Journal of Computer Science and Technology and Frontiers of Computer Science. He has supervised numerous Ph.D. and MSc students, with research topics spanning program analysis, software testing, self-adaptive systems, and more. His students have gone on to successful careers in both academia and industry. Research Groups: Professor Xu is associated with the SPAR research group at Nanjing University and the CASTLE research group at HKUST, focusing on software analysis, reliability, and testing.
Kimia Zamiri Azar serves as an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Central Florida, focusing on hardware security and verification methodologies. Her research bridges theoretical formal methods with practical security implementations in semiconductor design and testing. Her educational background includes: Ph.D. in Electrical and Computer Engineering, George Mason University (2021) Postdoctoral Research, University of Florida Dr. Azar's research spans hardware security with emphasis on system-level verification, VLSI design-for-trust, and advanced IC testing. She pioneers techniques in logic locking, secure heterogeneous integration, and IC supply chain security, developing frameworks for authenticated encryption in Systems-in-Package and runtime security monitoring. Her work integrates formal verification with innovative testing methodologies to address hardware trust challenges across the semiconductor lifecycle. Analysis of her recent publications reveals two dominant trends: (1) Application of large language models (LLMs) to hardware design tasks including high-level synthesis code generation and RTL optimization, and (2) Advancement of secure heterogeneous integration techniques for System-in-Package architectures with focus on counterfeit prevention and split-test security protocols. These directions address critical gaps in hardware trustworthiness amid increasingly complex semiconductor supply chains. Her scientific contributions have earned significant recognition: Best Paper Award at ICCAD 2019 Best Paper Award at ISVLSI 2020 Best Paper Award at ICCAD 2020 Best Paper Award at IEEE DCAS 2020 Best Paper Award at HOST 2022 Best Paper Award at DATE 2023 Dr. Azar secures substantial research funding from premier agencies including NSF, SRC, DARPA, AFRL, DoD (NG), and Microsemi. Her grants support projects spanning hardware security validation frameworks, secure heterogeneous integration, and AI-augmented verification methodologies. She actively mentors students in her research group, guiding publications in top venues like IEEE D&T, IEEE TC, and DAC while fostering industry-academic collaborations. Her work directly impacts semiconductor security standards through patented innovations and open-source verification tools. As an active IEEE and ACM member, she contributes to community advancement through conference organization (HOST, DATE), journal editorial roles, and workshop leadership on hardware security standards. Her research group collaborates with semiconductor industry leaders to translate theoretical security frameworks into practical design-for-trust methodologies for next-generation integrated circuits.
Mike Papadakis is an Associate Professor at the University of Luxembourg's Interdisciplinary Centre for Security, Reliability and Trust (SnT), where he leads the SerVal research group. His research focuses on software engineering, software security, and artificial intelligence. He holds a PhD in Software Testing and Verification from Athens University of Economics and Business, with an MSc and BSc from the same institution. His research explores mutation testing, machine learning applications in software development, and test optimization. Recent publications demonstrate a strong emphasis on AI robustness, flaky test analysis, and automated debugging techniques. Notable achievements include the IEEE TCSE Rising Star Award (2020) and 12 additional research awards. He has published over 100 peer-reviewed articles and delivered more than 30 invited talks globally.
Nikos Hardavellas is a Professor of Computer Science and Electrical and Computer Engineering at Northwestern University, affiliated with the McCormick School of Engineering. He leads the Parallel Architecture Group at Northwestern (PARAG@N), focusing on energy-efficient parallel computing and quantum systems. His research spans quantum computing systems, fault-tolerant quantum error management, memory-centric architectures, and photonics-based interconnects. Education: Ph.D. Computer Science, Carnegie Mellon University (2009) M.S. Computer Science, Carnegie Mellon University (2006) M.S. Computer Science, University of Rochester (1997) B.S. Computer Science, University of Crete (1995) Research Interests: Quantum system software stack and error mitigation Memory-centric computing and programmable memory systems Energy-efficient architectures and dark silicon Photonics and optical interconnects Parallel systems and compiler-hardware co-design Key Contributions: Developed SupermarQ, a scalable quantum benchmark suite Pioneered optical cache hierarchies (Pho$) and energy-proportional photonic networks Advanced compiler-driven virtual memory systems (CARAT) and MPI autotuning (ACCLAiM) Awards & Honors: NSF CAREER Award (2015) Future CRA Leader (2024) Best Paper Awards at HPCA (2022) and ISLPED (2021 nomination) Test-of-Time Award at EDBT (2019) Grants & Service: Secured $4.8M in research funding from NSF, industry partners, and university initiatives Executive Committee member of Northwestern’s INQUIRE Institute for Quantum Research General Co-chair of IEEE/ACM MICRO 2022 Extensive service on departmental committees and thesis advisory boards Labs & Teams: Directs PARAG@N, collaborating on quantum computing, photonics, and energy-efficient architectures. Engages with industry partners like AMD, Intel, and Synopsys.
