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Antonio González is a full Professor at the Barcelona School of Informatics (FIB), Universitat Politècnica de Catalunya (UPC), where he is affiliated with the Department of Computer Architecture. He leads the Microarchitecture and Compilers (ARCO) research group, focusing on robust and energy-efficient computing systems, including general-purpose processors, GPUs, and cognitive computing architectures. His research spans computer architecture, microarchitecture, compilers, GPU design, and deep learning acceleration, with a strong emphasis on energy efficiency and memory optimization. His work integrates hardware and compiler techniques to enhance performance in modern computing systems. The recent publications highlight a strong trend in energy-efficient DNN acceleration, GPU microarchitecture, memory systems, and near-data processing. His team explores novel quantization methods, adaptive caching, and architectural extensions for vision and AI workloads, published in top-tier venues such as MICRO, ISCA, and IEEE/ACM journals. ACM Fellow (2020) ICREA Academia Award (2014, 2019, 2024) UPC Duran Farell Award (2008) HiPEAC 2024 Paper Award (twice) González has supervised several PhD students and leads competitive R&D+i projects, including those funded by ICREA and the European Research Council. His research group collaborates extensively within UPC and with international institutions. He is actively involved in advancing computer architecture through innovation in simulation, hardware design, and AI acceleration. He is a member of IEEE and ACM, and his work continues to influence both academic and industrial developments in high-performance and energy-efficient computing.

• Computer Architecture
• Microarchitecture
• Compilers
• +7 more

Mateo Valero Cortés is a renowned Professor of Computer Architecture at the Polytechnic University of Catalonia and Director of the Barcelona Supercomputing Center (BSC). He has held academic and leadership roles since 1974, advancing high-performance computing (HPC) and computer architecture research. His work includes pioneering contributions to vector architectures, multithreading, and instruction-level parallelism. Education includes a Telecommunications Engineering degree from the Polytechnic University of Madrid (1974) and a PhD in Telecommunications Engineering from the Polytechnic University of Catalonia (1980). His research spans over 700 publications, focusing on HPC systems, parallel computing, and supercomputing infrastructure. Key research interests include vector processing, super-scalar processors, and task-based programming models. Recent work emphasizes scalable architectures for exascale computing and energy-efficient hardware-software co-design. Notable achievements include the Eckert-Mauchly Prize (highest in computer architecture), Seymour Cray Award, and Charles Babbage Prize. He has led initiatives like the Spanish Supercomputing Network (RES) and PRACE (European HPC partnership). Academic affiliations include the Royal Academy of Engineering of Spain, ACM Fellow, and IEEE Fellow. He has received 13 honorary doctorates and awards such as Mexico’s Order of the Aztec Eagle. Current projects include the Mont-Blanc HPC prototype and ERC-funded research on multi-core chip design. His BSC oversees over 300 researchers and manages MareNostrum supercomputers.

• Computer Architecture
• High-Performance Computing
• Parallel Computing
• +3 more

Alberto Ros is a Full Professor at the University of Murcia , Spain, in the Computer Engineering Department (DITEC) . His work focuses on cache coherence , memory hierarchy designs , memory consistency , and processor microarchitecture , with over 100 peer-reviewed publications. Dr. Ros earned his MS (2004) and PhD (2009) in Computer Science from the University of Murcia. He interned at the School of Informatics, University of Edinburgh , and held postdoctoral positions at the Technical University of Valencia and Uppsala University . He is an IEEE Senior Member . Research interests include optimizing hardware for multicore systems. His work spans cache coherence protocols, transactional memory, speculative execution, and data/instruction prefetching techniques. He led the ERC Consolidator Grant (2018) and ERC Proof of Concept Grant (2023) to improve multicore architecture performance. Recent publications emphasize hardware transactional memory efficiency, speculative execution, and secure cache systems. Notable works include cache locking, memory dependency prediction, and fine-grain coherence protocols. Scientific awards : Inducted into the MICRO Hall of Fame ISCA Hall of Fame 27 HiPEAC paper awards (MICRO, ISCA, HPCA, ASPLOS) Winner, ML-based Data Prefetching Competition Winner, 1st Instruction Prefetching Championship IEEE MICRO TopPicks for ISCA'17, MICRO'21 (honorable), MICRO'16 (honorable) Best paper awards at HiPC'16, FORTE'16 Honorable mention at HPCA'24 Nomination at ISCA'22 Grants as Principal Investigator include ERC Proof of Concept (2023) ERC Consolidator (2018) Europe Excellence (2018) Seneca Foundation, Young Leaders in Research (2014) . Dr. Ros is affiliated with the Computer Architecture and Parallel Systems Group (CAPS) at the University of Murcia and previously with UPMARC at Uppsala University.

• Computer Architecture
• Parallel Processing
• Multicore Processors
• +5 more

Antonio Maria Gonzalez Colas is a Full Professor at the Universitat Politècnica de Catalunya (UPC), affiliated with the Department of Computer Architecture within the Faculty of Computer Science of Barcelona (FIB). He leads the ARCO research group focused on Microarchitecture and Compilers and is actively engaged in high-impact research in computer architecture, GPUs, and energy-efficient computing. His collaborations extend to the Barcelona Supercomputing Center and various national and European research initiatives. Research Interests: His primary research areas include computer architecture, microarchitecture, compilers, GPUs, and processor design. He focuses on energy-efficient computing, deep neural network (DNN) accelerators, GPU simulation and optimization, memory systems, and architectural support for machine learning and autonomous systems. His work often integrates compiler techniques with hardware design for performance and efficiency. Scientific Production Trends: His recent publications demonstrate a strong focus on energy-efficient hardware for AI workloads, particularly DNN and speech recognition acceleration, GPU architectural innovations, memory optimization, and real-time rendering. He frequently publishes in top-tier venues such as ISCA, MICRO, HPCA, and IEEE/ACM journals. ICREA Academia Award 2024 HiPEAC 2024 Paper Award ACM Senior Member (2020) Advising and Grants: He has advised numerous PhD students whose theses cover topics like energy-efficient architectures for autonomous driving, speech recognition, and neural networks. He leads competitive R&D projects, including an ERC Advanced Grant and projects funded by the Spanish National Program and the ICREA Academia program, focusing on domain-specific architectures and cognitive computing units. Labs and Teams: He is the principal investigator of the ARCO (Microarchitecture and Compilers) research group at UPC, a leading team in computer architecture research in Spain. The group is part of a larger collaborative network within UPC and with international partners.

• Computer Architecture
• Microarchitecture
• Compilers
• +7 more

Georgios Portokalidis is an Associate Research Professor at IMDEA Software Institute and Visiting Research Professor at Stevens Institute of Technology. He leads research in software systems security with focus on binary analysis, software hardening, and operating system security. His research develops practical defenses against software vulnerabilities through techniques like binary debloating, system call filtering, and hardware-assisted security. Current projects explore Rust language security, processor-assisted protection mechanisms, and vulnerability mitigation through code reduction. Publication trends show evolution from foundational binary analysis to applied security hardening, with recent emphasis on Rust security, hardware-assisted defenses, and real-world system protection. Work demonstrates consistent focus on practical, deployable security solutions. He has supervised numerous PhD students and postdocs, currently mentoring researchers at IMDEA. His group investigates binary analysis, software debloating, and system hardening techniques. Major grants include DARPA YFA (2021-2023) and ONR funding (2017-2022) supporting adaptive binary debloating research. Leads the systems security research group at IMDEA Software Institute, collaborating with international partners. Maintains active research partnerships and regularly contributes to top security conferences as program committee member.

• Systems Security
• Binary Analysis
• Software Hardening
• +1 more

Roger Espasa Sans is a senior academic and researcher at the Universitat Politècnica de Catalunya (UPC), affiliated with the Faculty of Informatics of Barcelona (FIB) and the Department of Computer Architecture. He has made significant contributions to computer architecture, particularly in vector processing, GPU design, and performance optimization. Universitat Politècnica de Catalunya (UPC) Faculty of Informatics of Barcelona (FIB) Department of Computer Architecture His research focuses on advanced computer architecture, including vector and superscalar processors, memory systems, instruction-level and data-level parallelism, GPU microarchitecture, and performance modeling. His work bridges theoretical design and practical implementation, especially in high-performance and embedded systems. The recent articles highlight a strong trend in GPU and shader optimization, memory redundancy elimination, and performance modeling. His publications span prestigious venues such as IEEE Microarchitecture Symposium, IEEE HPCA, and The Visual Computer, indicating sustained impact in the field of computer systems and architecture. Premiada (Awarded activity) Roger Espasa Sans has advised several doctoral students, including Manel Fernandez Gomez and Francisca Quintana Domínguez, contributing to the next generation of computer architects. His collaborative network is extensive, involving key figures like Mateo Valero and international institutions. While specific grants are not listed, his prolific output suggests sustained funding. He has contributed to major research groups such as CAP (High Performance Computing Group). He is a core member of the CAP - Grup de Computació d'Altes Prestacions (High Performance Computing Group), and has also been associated with PM - Programming Models and ARCO - Microarchitecture and Compilers. His work often involves simulation frameworks like JINKS and Asim, indicating a strong focus on performance evaluation and modeling.

• Computer Architecture
• Vector Processors
• GPU Microarchitecture
• +9 more

Manuel Eugenio Acacio Sanchez is a Professor in the Department of Computer Engineering and Technology at the University of Murcia's Faculty of Informatics. His research focuses on computer architecture, parallel systems, cache coherence, and hardware transactional memory. He earned his Ph.D. from the University of Murcia in 2003 with a thesis on directory-based coherence protocols for distributed-shared memory multiprocessors. Doctorate: Universidad de Murcia (2003) Academic Rank: Professor Research Interests include Hardware transactional memory Cache coherence protocols GPU and DNN accelerators Energy-efficient computing Parallel architectures Recent Article Trends emphasize cycle-level simulation tools (e.g., STONNE), hardware transactional memory optimizations, and neural network accelerator design. His work bridges microarchitectural improvements and application-specific efficiency in multicore systems. Labs & Teams : Affiliated with the Computer Architecture and Parallel Systems research group, previously part of the Architecture and Parallel Computing group.

• Computer Architecture
• Parallel Computing
• Cache Coherence
• +5 more

Alberto Ros Bardisa is a Professor at the Department of Computer Engineering and Technology within the Faculty of Informatics at the University of Murcia. He holds a Doctorate from the same university, completing his thesis on Efficient and Scalable Cache Coherence for Many-Core Chip Multiprocessors in 2009. His research focuses on computer architecture , with particular emphasis on cache coherence protocols , hardware transactional memory , speculative execution , and many-core systems . He has contributed to optimizing memory subsystems, concurrency management, and scalability in parallel computing environments. His work often bridges hardware-software co-design to enhance performance and security in modern architectures. Dr. Ros Bardisa is affiliated with the Computer Architecture and Parallel Systems research group and previously contributed to the Architecture and Parallel Computing group. His publications (over 130+ listed) reflect a sustained focus on advancing cache efficiency, transactional memory systems, and speculative execution techniques. His current work explores innovative solutions for fine-grain coherence , secure prefetching , and atomic operation optimization , with recent contributions in 2025 addressing novel protocols like WoperTM and MASCOT.

• Computer Architecture
• Parallel Computing
• Hardware Optimization
• +6 more

Antonio González Colás is a Full Professor at the Universitat Politècnica de Catalunya (UPC), affiliated with the Facultat d'Informàtica de Barcelona (FIB) and the Department of Computer Architecture. He leads the ARCO research group (Microarchitecture and Compilers) and focuses on advanced computer architecture, including GPUs, compilers, and embedded systems. In 2024, he received the ICREA Acadèmia distinction for his research on future computer systems integrating cognitive tasks and autonomous decision-making. His work emphasizes energy-efficient architectures, memory optimization, and hardware acceleration for AI and real-time applications. He holds a Doctorate in Computer Science and has over 1000+ publications, including top-tier journals and conferences. His research spans topics like GPU microarchitecture, compiler-assisted caching, DNN acceleration, and autonomous driving hardware. Major awards include the HiPEAC 2024 Paper Award and EU-funded projects under Horizon 2020. He advises numerous PhD students on topics such as point cloud processing for autonomous systems, GPU rendering optimizations, and neural network efficiency. His contributions bridge theoretical computer architecture with practical hardware-software co-design, addressing challenges in modern computing systems.

• Computer Architecture
• Compilers
• GPUs
• +4 more

Antonio Flores Gil is an Assistant Professor at the Computer Engineering Department within the University of Murcia (Spain). Contact: aflores@um.es, Phone: +34 868 884638. Research Interests : Processor microarchitecture Multicore systems Energy-efficient architectures His publications focus on heterogeneous interconnects , energy consumption reduction , and message management optimization in tiled CMP architectures. Key topics include network-on-chip design, address compression, and hardware prefetching techniques. Groups : ACCA Group (Advanced Communication and Computer Architecture) GACOP (Parallel Computing and Architecture Group, Univ. Murcia)

• Processor microarchitecture
• Multicore systems
• Energy-efficient architectures

Jan Reineke is a Professor of Computer Science at Saarland University , where he leads research at the intersection of hardware and software. His work focuses on timing-predictable microarchitectures, real-time systems, and hardware-software security contracts. Affiliation: Saarland University (since 2012) Previous: Postdoctoral scholar at UC Berkeley (2009-2011) Research Interests include static program analysis, real-time systems, computer architecture, and hardware-related security issues. His group develops tools like LLVMTA , uops.info , and Spectector for cache analysis, microarchitectural profiling, and speculative execution security. Design of timing-predictable processors (RTSS 2018, RTSS 2019) Exact LRU cache analysis (CAV 2017, POPL 2019, RTSS 2019) Detection of speculative information flows (S&P 2020, S&P 2021) Quantitative cache analysis frameworks (RTAS 2025) Recent Articles span cache timing analysis, speculative execution vulnerabilities, and performance modeling. Keywords include Real-Time Systems , Security , Computer Architecture , and Static Analysis , with sub-fields covering cache persistence, hardware-software contracts, throughput prediction, and formal verification of side-channels. Scientific Awards include an ERC Advanced Grant (2021) , multiple best paper awards (RTAS 2025, DATE 2024, CCS 2023), and the Intel Early Career Faculty Honor Program (2012). Advising and Grants : He actively recruits PhD students and postdocs for hardware-software security research, supported by the ERC grant. His lab's alumni include Dr. Sebastian Hahn, and he has hosted numerous student assistants. Labs and Teams : He leads the Real-Time and Embedded Systems Lab at Saarland Informatics Campus, collaborating on projects like uops.info (Intel microarchitectural profiling) and chi (cache hierarchy inference).

• static analysis
• real-time systems
• computer architecture
• +1 more

Alexandra Jimborean is a Ramón y Cajal researcher at the University of Murcia and affiliated Associate Professor at Uppsala University. She holds a PhD from the University of Strasbourg and specializes in compile-time code analysis, optimization, and software-hardware co-designs for performance and energy efficiency. Research focuses on: Instruction prefetching and speculative execution mechanisms Compiler-assisted code optimization techniques Hardware-software co-design for secure and efficient processors Dynamic program analysis frameworks Significant contributions include the development of the DAEDAL and Clairvoyance compiler technologies, commercialized through the EtaScale startup. Holds leadership roles in major conferences including Program Chair for CGO 2019 and CC 2020.

• Compiler Design
• Hardware-Software Co-Design
• Code Optimization
• +5 more

Juan Luis Aragon Alcaraz is a Full Professor in Computer Architecture at the University of Murcia (Spain), affiliated with the Faculty of Informatics and the Department of Computer Engineering and Technology. He obtained his PhD in Computer Engineering from the University of Murcia in 2003 and held a postdoctoral position as a Visiting Assistant Professor and Researcher at the University of California, Irvine. He has held visiting researcher positions at EPFL (2013) and Princeton University (2015–2022). His research focuses on computer architecture, emphasizing heterogeneous parallel systems, GPUs, memory hierarchies, and energy-efficient microarchitecture design. He has advised 7 PhD theses and co-authored over 60 publications in top-tier conferences and journals. His work includes contributions to GPU-accelerated medical imaging, energy-efficient graphics pipelines, and hardware-software co-design for parallel systems. Key research trends in his articles include optimizing GPU performance for real-time applications, energy efficiency in graphics rendering, and scalable latency tolerance in manycore systems. His patents include innovations in presbyopia correction devices leveraging GPU and FPGA technologies. Dr. Aragón has taught numerous courses in computer architecture and design, including Computer Architecture and Organization, Advanced Aspects in Multicore Architectures, and Embedded Systems Technologies. His labs and collaborations span academic-industrial partnerships, emphasizing practical applications of his theoretical contributions.

• Computer Architecture
• Heterogeneous Parallel Systems
• GPU Computing
• +4 more

Lesly-Ann Daniel is an Assistant Professor at EURECOM in the software and system security (S3) group , specializing in formal methods for low-level security . Her research spans binary analysis, symbolic execution, and hardware-software co-designs for microarchitectural security. PhD in Computer Science (2021) from CEA List , supervised by Sébastien Bardin and Tamara Rezk Postdoctoral researcher at DistriNet, KU Leuven (2021-2025) Co-developer of tools Binsec/Rel and Binsec/Haunted for binary-level security analysis Her research focuses on applying formal methods to detect vulnerabilities in cryptographic code, mitigate microarchitectural side-channels , and enhance security through RISC-V extensions . Key projects include ProSpeCT for secure speculation and Architectural Mimicry for control-flow linearization. Notable awards include the FWO Junior postdoctoral fellowship , PhD thesis award from Université Côte d’Azur , and the L’Oréal-UNESCO Jeunes Talents France fellowship. She serves on program committees for CCS, EuroS&P, and PriSC workshops.

• Formal Methods
• Low-Level Security
• Binary Analysis
• +5 more

Eduard Ayguadé serves as Full Professor in the Department of Computer Architecture at Polytechnic University of Catalonia (UPC) since 1997 and Associate Director for Research in the Computer Sciences Department at Barcelona Supercomputing Center (BSC-CNS), driving high-performance computing initiatives across both institutions. His academic credentials include: Engineering Degree in Telecommunications (1986), Universitat Politècnica de Catalunya Ph.D. in Computer Science (1989), Universitat Politècnica de Catalunya Research spans Processor Microarchitecture , Multicore Architectures , and Parallel Programming Models with architectural optimization, yielding over 250 publications. His work emphasizes bridging theoretical models with practical hardware implementation through European Union projects and industry collaborations. Scientific recognition includes leadership roles at BSC-CNS but no specific awards are documented in source materials. Grant activity encompasses multiple EU-funded research programs and corporate partnerships, though advisory details for students remain unspecified. His operational scope integrates UPC's academic framework with BSC-CNS's supercomputing infrastructure for large-scale computational science. As Associate Director at Europe's premier supercomputing facility, he shapes national research strategies and international HPC collaborations while maintaining active teaching in computer organization and architecture.

• Computer Architecture
• Processor Microarchitecture
• Multicore Architectures
• +2 more