Find Academic Supervisors

• System Security
• Automatic Software Testing
• Threat Mitigation
• +6 more

Dr. Flavio Toffalini serves as Assistant Professor of Cybersecurity at Ruhr University Bochum (RUB) since September 2024, holding the Chair for Automated Security Analysis. His research group focuses on advancing system security through innovative approaches to software testing and trusted computing. Dr. Toffalini completed his Ph.D. at Singapore University of Technology and Design (SUTD) in 2021 under Professor Jianying Zhou, followed by postdoctoral research at EPFL's HexHive group with Professor Mathias Payer. His educational background includes a Master's degree from the University of Verona (2015) focused on web security. His research centers on system security with emphasis on automatic software testing (particularly fuzzing), threat mitigation, and trusted execution environments (SGX, TrustZone). Current projects explore browser/interpreter testing, memory safety mechanisms, and compiler-assisted security hardening. He actively develops novel fuzzing techniques to uncover deep vulnerabilities in complex systems. Analysis of his 2023-2025 publications reveals dominant themes in JavaScript engine security (DUMPLING), adaptive fuzzing (TuneFuzz), and trusted computing hardening (TLBlur). His work bridges theoretical security concepts with practical implementations, often yielding tools adopted by the security community. Notable scientific recognition includes: Distinguished Paper award at NDSS 2025 for JavaScript engine fuzzing research Distinguished Paper award at NDSS 2025 for type confusion mitigation Best Paper award at ACNS 2022 for IoT attestation systems Dr. Toffalini currently supervises three Ph.D. students (Tobias Wienand at RUB, Nicolas Badoux and Han Zheng at EPFL) and has guided multiple MSc theses. His research is supported through projects in software analysis, vulnerability detection, and system security, with active recruitment for students specializing in fuzzing and trusted computing. He leads the Automated Security Analysis research group at RUB, maintaining strong collaborations with EPFL's HexHive group. The team actively develops tools for interpreter testing, reverse engineering, and trusted execution environment security, with current projects focusing on extending fuzzing to new programming languages and mitigating microarchitectural vulnerabilities.

Mengjia YanView profile

Associate Professor

• Computer Architecture
• Security
• Hardware Security
• +4 more

Mengjia Yan is an Associate Professor in the Electrical Engineering and Computer Science (EECS) Department at MIT, affiliated with the Computer Science and Artificial Intelligence Laboratory (CSAIL). Her research focuses on computer architecture and security, particularly side-channel attacks and defenses. She leads the MATCHA group (microarchitecture attacks and challenges), exploring vulnerabilities in microarchitecture and designing robust defenses. Educated at Zhejiang University (B.S.) and the University of Illinois at Urbana-Champaign (UIUC, Ph.D.), she joined MIT after completing her PhD under Prof. Josep Torrellas. Her work bridges hardware security, speculative execution, and machine learning, with notable contributions like PACMAN (ARM pointer authentication attacks) and Oreo (ASLR protection). Teaching includes courses on computer system architecture (6.5900/6.823) and secure hardware design (6.5950/6.888). She has advised numerous students, including Rhodes Scholars and recipients of fellowships like NSF and NDSEG. Awarded the Intel Rising Star Faculty Award (2022), NSF CAREER Award (2021), and multiple best paper awards, she also co-organizes conferences like PLARCH and MAD. Current projects include SecureLoop (DNN accelerator security) and formal verification frameworks for secure processors. Labs/Teams: MATCHA Group at MIT CSAIL. Active in academic service, serving on program committees for ASPLOS, ISCA, and MICRO.

• Computer Architecture
• GPU Optimization
• Machine Learning Acceleration
• +4 more

Dr. T Vijaykumar is a Professor in the Department of Electrical and Computer Engineering at Purdue University. His research focuses on computer architecture, GPU optimization, machine learning acceleration, and high-performance computing. He leads projects involving hardware-software co-design for energy-efficient systems and secure speculative execution techniques. His work spans innovations in GPU concurrency, sparse matrix processing, and distributed training frameworks for neural networks. He has contributed to advancements in memory systems, including PIM architectures and address translation optimizations. Recent projects include Proteus (model confidentiality) and Disorf (mobile 3D reconstruction). Key research themes include accelerating irregular computational graphs, secure hardware design, and efficient data movement in disaggregated systems. His publications reflect a strong emphasis on practical implementations with real-world applications in robotics, genomics, and cloud computing. Dr. Vijaykumar has received institutional awards for his contributions to computer architecture and holds patents in areas like microfluidics and data center congestion control. He collaborates with industry on GPU kernel design and memory consistency verification frameworks like QED.

• Computer Architecture
• High-Performance Computing
• Memory Systems
• +3 more

Per Stenstrom is a Professor of Computer Engineering at Chalmers University of Technology, Sweden since 1995. His research focuses on computer architecture, particularly high-performance memory systems and energy-efficient computing. He has authored/co-authored four textbooks, over 200 publications, 20 patents, and supervised approximately 25 PhD students. Awarded ACM Fellow and IEEE Fellow. Member of Academia Europaea and the Royal Swedish Academy of Engineering Sciences. Co-founder of the HiPEAC Network of Excellence. Served as Editor or Associate Editor for journals like ACM Transactions on Architecture and Code Optimization and IEEE Transactions on Computers . Program Chair for major conferences including ISCA, HPCA, IPDPS, and ACM International Conference on Supercomputing. His research innovations include cache compression techniques, memory optimization strategies, and energy-aware resource management in multicore systems. Ongoing work emphasizes secure and scalable cache partitioning, hybrid memory systems, and defense mechanisms against microarchitectural attacks.

• Embedded Systems
• Hardware Security
• Memory Systems
• +3 more

Jun Yang is a Professor at the Swanson School of Engineering, University of Pittsburgh. His research focuses on embedded systems, hardware security, memory systems, and processor microarchitecture. He has made significant contributions to GPU architecture, quantum computing, and secure memory management. Key honors include the NSF Faculty Early Career Development Award (2008) and Best Paper awards at ISLPED 2013 and ICCD 2013. His work bridges theoretical computer science with practical hardware implementations, addressing challenges in modern computing systems. Research Interests: Embedded Systems & Hardware Security: Developing robust systems against side-channel and memory vulnerabilities. Quantum Computing: Optimizing quantum circuit evaluation on photonic and hybrid platforms. Memory Systems: Innovations in GPU page management, TLB optimization, and storage deduplication. Publications span high-impact areas like multi-GPU systems, quantum resource management, and covert channel mitigation. His work frequently appears in top-tier conferences such as HPCA, ISCA, and ASPLOS.

• Cryptography
• Post-Quantum Cryptography
• Cryptographic Engineering
• +4 more

Peter Schwabe is a scientific director at the Max Planck Institute for Security and Privacy (MPI-SP) in Bochum, Germany, and a part-time professor for cryptographic engineering in the Digital Security Group at Radboud University in Nijmegen, The Netherlands. He has held these positions while leading significant research initiatives in post-quantum cryptography and high-assurance cryptographic implementations. His research interests center on post-quantum cryptography, cryptographic engineering, and high-assurance crypto software. Schwabe's work focuses on developing and verifying cryptographic implementations that are resistant to side-channel attacks while maintaining high performance. He has made significant contributions to lattice-based cryptography, hash-based signatures, and the standardization of post-quantum cryptographic algorithms. His research bridges theoretical cryptography with practical implementation concerns, particularly for resource-constrained environments. Analysis of Schwabe's recent publications reveals a strong focus on post-quantum cryptography standardization, formal verification of cryptographic implementations, and protection against side-channel attacks. His work spans theoretical advances in cryptographic primitives, practical implementations for real-world systems, and tools for verifying the security properties of cryptographic code. A significant portion of his recent work relates to the CRYSTALS-Kyber standard selected by NIST, including formal verification of its security properties and implementation correctness. Schwabe has served as an elected member of the IACR Board of Directors, member of the IACR CHES Steering Committee, and member of the IACR RWC Steering Committee. He is also a member of the advisory boards of Bitmark Inc., PQShield, Neutrality, and SciEngines, demonstrating his influence in both academic and industry cryptographic communities. As an advisor, Schwabe has supervised numerous Ph.D. students working on various aspects of cryptography, including post-quantum cryptography, side-channel resistance, and formal verification of cryptographic implementations. His work on the EPOQUE project (Engineering post-quantum cryptography), funded by an ERC Starting grant from October 2018 to December 2023, demonstrates his leadership in advancing post-quantum cryptographic research. Schwabe leads research efforts at the intersection of formal methods and practical cryptography, with a particular emphasis on creating high-assurance cryptographic implementations that can withstand both theoretical and practical attacks. His work often involves collaboration with international teams across academia and industry to advance the state of the art in cryptographic engineering.

Boris GrotView profile

Professor

• System architectures for datacenters
• Processor architecture and microarchitecture
• Memory systems and interconnection networks
• +3 more

Boris Grot is a Professor holding the Personal Chair of Computer Systems and Architecture in the School of Informatics at the University of Edinburgh, where he leads research on optimizing large-scale datacenter efficiency through hardware-level innovations in server architectures, memory systems, and interconnect networks. His academic background includes a PhD in Computer Science from The University of Texas at Austin (thesis: scalability and quality-of-service in on-chip networks) followed by post-doctoral research at EPFL's Parallel Systems Architecture Lab. Research focuses on critical infrastructure challenges driven by three converging factors: mobile/embedded system constraints (battery, thermal, form factor), massive-data applications (search, social networking), and enterprise cloud migration. Key problem domains include: Re-inventing server architectures for specialized datacenter workloads Overcoming semiconductor voltage scaling limitations Addressing the 1.3% global energy footprint of datacenters (growing rapidly) Designing football-field-scale facilities handling 5-20 MW power loads He directs the EASE Lab investigating these challenges, emphasizing the economic and environmental urgency as datacenter deployment accelerates worldwide. No scientific awards or student advisees were specified in the source material, and grant details remain undocumented in the provided text.

T N. VijaykumarView profile

Professor

• Computer Architecture
• Machine Learning
• High-Performance Computing
• +7 more

T. N. Vijaykumar is a Professor of Electrical and Computer Engineering at Purdue University, with a courtesy appointment in Computer Science. He joined the university in 2003. His research focuses on computer architecture, machine learning acceleration, high-performance computing, and hardware-software co-design. He holds degrees from Birla Institute of Technology and Science (BE, MSc) and the University of Wisconsin (MS, PhD in Computer Science). Education: B.E. (Hons), Electrical and Electronics Engineering, Birla Institute of Technology and Science (1990) M.Sc. (Tech), Computer Science, Birla Institute of Technology and Science (1992) M.S. and Ph.D., Computer Science, University of Wisconsin (1997) His research interests span GPU architectures , memory systems , neural network acceleration , and secure computing . Recent work includes optimizing sparse tensor processing, secure speculative execution, and distributed training frameworks for mobile robotics. Publications highlight contributions to GPU kernel concurrency, neural radiance fields, and memory consistency verification. His work often bridges hardware design and software efficiency, with applications in data centers and edge computing. Notable grants include projects like QED (scalable hardware memory verification) and ESPIM (sparse processing-in-memory for ML inference). He has also contributed to frameworks like Disorf for real-time rendering in robotics. Labs/Teams: Active involvement in Purdue’s Computer Science and ECE departments, with collaborations on AI hardware and systems research.

Joseph RussellView profile

Associate Professor

• Computer Architecture
• Microprocessor Design
• Power-Aware Computing
• +3 more

Russ Joseph is an Associate Professor in both the Department of Electrical and Computer Engineering and the Department of Computer Science at Northwestern University. He holds a Ph.D. in Electrical Engineering from Princeton University (201?), an M.A. in Electrical Engineering from Princeton, and a B.S. in Electrical and Computer Engineering from Carnegie Mellon University. His research focuses on computer architecture innovations, particularly in microprocessor design for reliability, variability tolerance, and power efficiency. Current projects include co-designed systems software for multi-core architectures, variability-tolerant architectures, and dynamic power management solutions. Education highlights include Princeton University (Ph.D., M.A. in Electrical Engineering) and Carnegie Mellon University (B.S. in ECE). His research explores adaptive clock management, compiler-assisted timing speculation, and embedded system design. Notable contributions include the NCPU architecture and Cocoa cache compression techniques. Teaching responsibilities include courses on computer engineering fundamentals and parallel architectures. Research interests emphasize hardware-software co-optimization, ultra-dynamic clock management, and energy-efficient computing. Projects address challenges in multi-core resource management, thermal efficiency, and parameter variation mitigation. His work bridges theoretical computer architecture with practical embedded system applications.

Mark SmothermanView profile

Associate Professor

• Computer Architecture
• Computer Systems
• Reliability Modeling
• +5 more

Mark Smotherman is an Associate Professor in the School of Computing at Clemson University, specializing in computer architecture, reliability modeling, and computer science education. He has held roles such as Associate Director of the School of Computing and Director of Graduate Affairs. He earned his Ph.D. in Computer Science from the University of North Carolina at Chapel Hill and a B.S. in Physics from Middle Tennessee State University. His research focuses on computer architecture history, superscalar processors, reliability analysis, and educational methodologies. Notable contributions include the Hybrid Automated Reliability Predictor (HARP) and work on IBM's ACS project. He has received awards like NASA Langley's Space Act Award (1997) for HARP's impact. Smotherman teaches courses like Operating Systems (CPSC/ECE 3220) and Computer Systems Organization (CPSC 3300), and has advised numerous graduate students. He has contributed to over 100 publications and served on committees for conferences like MICRO and ACSAC. His work bridges historical computing insights with modern systems design.

• Computer Architecture
• Memory Systems
• Hardware/OS Interaction
• +7 more

Vasileios Karakostas is an Assistant Professor at the Department of Informatics and Telecommunications, National and Kapodistrian University of Athens. He is a member of the Computer Architecture Lab and focuses on computer architecture, memory systems, and resource management. Previously, he was a postdoctoral researcher at the National Technical University of Athens' Computing Systems Lab. He holds a PhD in Computer Architecture from Universitat Politècnica de Catalunya and Barcelona Supercomputing Center. Education: Ph.D. in Computer Architecture, Universitat Politècnica de Catalunya (2016) M.Sc. in Computer Architecture, Networks, and Systems, UPC (2012) B.Eng. in Electrical and Computer Engineering, NTUA (2009) Research Interests: Memory systems (virtual memory, NVM) Hardware/OS interaction Resource management in data centers Parallel systems and serverless computing RISC-V architectures and cloud infrastructure Projects: Active in Horizon Europe projects Vitamin-V, Neuropuls, and REBECCA. Previously contributed to DAPHNE and ACTiCLOUD (EU H2020). Awards: 2024: Distinguished Artifact Award (ASPLOS) 2011: Best Paper Award (ICPE) Selected for IEEE Micro's Top Picks (2015, 2016) Teaching: Courses include Logic Design, Parallel Systems, and Large-scale Computing Systems at undergraduate and graduate levels. Labs/Teams: Leads research in the Computer Architecture Lab, collaborating on resilient architectures and cloud computing innovations.

• Computer Architecture
• Reconfigurable Computing
• Application Acceleration
• +5 more

Professor Dionisios Pnevmatikatos holds the position of Professor at the School of Electrical and Computer Engineering, National Technical University of Athens (NTUA), where he leads research in Computer Architecture and Reconfigurable Computing. He previously served as a Professor at the Technical University of Crete (TUC) from 2000 to 2019, directing the Microprocessor and Hardware Laboratory (MHL) and chairing the department. His academic journey includes a B.Sc. from the University of Crete (1989), M.Sc. and Ph.D. from the University of Wisconsin-Madison (1991 and 1995). Research Interests: Focuses on Computer Architecture, Reconfigurable Computing, Application Acceleration, Custom Architectures, and Hardware Acceleration of Bioinformatics Algorithms. His work spans FPGA-based systems, parallel computing, and energy-efficient designs. Key Projects: Coordinator of FASTER (EU FP7), Principal Investigator in DeSyRe, AXIOM, dRedBox, and EDRAH2020 projects. Active in EU initiatives like H2020 OPTIMA and Vitamin-V for RISC-V ecosystems. Leadership roles in conferences include SAMOS 2018 and FPL 2011 program chairs. Teaching: Courses include Computer Architecture, Digital Systems Design, and Parallel Processing Systems at NTUA. Former roles include teaching at University of Crete and TUC. Labs: Affiliated with Computing Systems Laboratory (CSLab) at NTUA and FORTH-ICS since 1997. Involved in prototyping manycore architectures and network processors.

Phil GibbonsView profile

Professor

• Big Data
• Parallel Computing
• Databases
• +5 more

Phil Gibbons is a Professor in the Electrical & Computer Engineering and Computer Science Departments at Carnegie Mellon University. He holds a Ph.D. from UC Berkeley (1989) and has extensive industry experience at AT&T Bell Labs, Lucent Bell Labs, and Intel Research. His research focuses on parallel computing, distributed systems, databases, and machine learning, with a emphasis on algorithmic and systems-level innovations. He has led major initiatives like the Intel Science and Technology Center for Cloud Computing and contributed to projects such as IrisNet (a planetary-scale sensor network). Education : Ph.D. in Computer Science, University of California at Berkeley (1989) Research Interests : Gibbons' work spans big data analytics , high-performance computing , and cloud systems . He develops scalable algorithms and systems for emerging memory technologies, distributed ML, and robotics. Notable contributions include processing-in-memory (PIM) optimizations, pipeline parallelism for DNN training, and system architectures for robotic processors. Awards : IEEE Fellow (2014) ACM Fellow (2006) ACM Paris Kanellakis Theory and Practice Award (2019) Best Paper Award at NSDI 2006 Grants & Leadership : Co-PI of the $15M Intel STC for Cloud Computing (2011-2015) Editor-in-Chief of ACM Transactions on Parallel Computing (2012-2018) Leadership roles in conferences like SPAA, EuroSys, and MLSys Teams & Labs : Active in robotics computing (RobotPerf benchmark), distributed ML systems, and hardware-software co-design initiatives.

Daniel JimenezView profile

Professor

• Computer Architecture
• Microarchitecture
• Branch Prediction
• +5 more

Daniel A. Jimenez is a Professor in the Department of Computer Science and Engineering at Texas A&M University . His research focuses on microarchitecture , interactions between compilers and microarchitectural design, and innovations in branch prediction and cache management . Educational Background: Ph.D. in Computer Sciences, Department of Computer Sciences, University of Texas at Austin M.S. in Computer Science, Division of Computer Science, University of Texas at San Antonio B.S. in Computer Science and Systems Design, Division of Mathematics, Computer Science, and Statistics, University of Texas at San Antonio Daniel is known for inventing the perceptron branch predictor and has significantly influenced research in neural branch prediction and machine learning applications in computer architecture . His work has been recognized with multiple best paper awards and inductions into prestigious computer architecture hall of fames . Selected Scientific Awards: IEEE Computer Society B. Ramakrishna Rau Award (2021) IEEE Fellow (2021) ACM Distinguished Scientist (2012) HPCA Test of Time Award (2019) Best Paper Award at MICRO (2022) NSF CAREER Award (2006) Inducted into ISCA, MICRO, and HPCA Halls of Fame His publications span key conferences like MICRO, ISCA, and ASPLOS, emphasizing topics such as branch prediction accuracy , cache replacement strategies , and memory hierarchy optimizations . Daniel is currently on sabbatical leave and will not be accepting new students for Fall 2024 or Spring 2025.

• Computer Architecture
• Machine Learning
• Data Storage Systems
• +5 more

Youtao Zhang is a Professor at the Swanson School of Engineering, University of Pittsburgh. His research focuses on computer architecture, machine learning, quantum computing, and data storage systems. He has contributed to advancements in secure non-volatile memories, GPU optimization, and healthcare informatics through deep learning applications. His work addresses challenges in hardware security, memory management, and efficient quantum circuit simulation. Key research areas include: Hardware Security and Covert Channels Quantum Computing Algorithms and Hardware Storage Systems Optimization GPU Acceleration and Parallel Computing Medical Imaging and Healthcare AI Recent publications emphasize innovations in hybrid storage deduplication, quantum circuit evaluation, and adversarial defense in vision transformers. His work bridges theoretical computer science with practical applications in emerging technologies.