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Michael FranzView profile

Professor

• Software Systems
• Compiler Design
• Virtual Machine
• +9 more

Professor Michael Franz is a Distinguished Professor and ICS Alumni Professor in the Donald Bren School of Information and Computer Sciences at the University of California, Irvine. He also holds a courtesy appointment in the Department of Electrical Engineering and Computer Science in the Henry Samueli School of Engineering. Franz directs UCI's Secure Systems and Software Laboratory and is a Fellow of AAAS, ACM, IEEE, and an Inaugural Fellow of IFIP. His educational background includes: Doctor of Technical Sciences in Computer Science from ETH Zurich (advisor: Niklaus Wirth) Dipl. Informatik-Ingenieur ETH degree from ETH Zurich Professor Franz pioneered mobile code and dynamic compilation research, creating early just-in-time compilation systems and co-inventing trace compilation technology that became Firefox's JavaScript engine. His current research focuses on Software Systems, particularly compiler and virtual machine techniques for making software safer, faster, or both. His work spans Computer Security, Trustworthy Computing, and Software Engineering, with recent emphasis on multivariant execution, automated software diversity, and probabilistic memory safety. Franz's research bridges theoretical foundations with practical applications, resulting in technologies deployed in major software systems used by hundreds of millions. His publication record demonstrates consistent leadership in security and systems research, with recent work focusing on survivable systems, binary analysis, and cross-platform security solutions. The publications reveal an evolution from foundational compiler techniques to sophisticated security mechanisms addressing real-world vulnerabilities, with strong emphasis on practical implementation and measurable impact. Professor Franz has received numerous prestigious awards: ACM Charles P. 'Chuck' Thacker Breakthrough in Computing Award (2020) Humboldt Research Award (2019) Distinguished Professor at UCI (2022) UCI's 'Innovator of the Year Award' (2018) Fellowships from all four major computing professional organizations Multiple Best Paper Awards at top-tier conferences As an advisor, Franz has graduated over 40 Ph.D. students, with recent graduates including Mitchel Dickerson and André Rösti. His research group has secured over $24 million in competitive grants (more than $16 million as sole PI) and received over $1 million in unrestricted industry gifts. Franz maintains strong industry connections, with many former students now at Google, Apple, and Meta, and his research directly influences commercial technologies. Leading the Secure Systems and Software Laboratory, Franz fosters a collaborative environment focused on developing innovative security solutions. The lab maintains global research partnerships and continues to advance areas like multivariant execution systems, automated software diversity, and practical security mechanisms. Current projects emphasize developing systems that maintain functionality even when compromised, addressing the evolving landscape of cyber threats with scientifically rigorous approaches.

Luca CassanoView profile

Associate Professor

• Hardware Security
• RISC-V Processors
• Deep Learning Reliability
• +3 more

Luca Cassano is an Associate Professor at the Department of Electronics, Informatics and Bioengineering (DEIB) at Politecnico di Milano, Italy. He leads the Hardware Forge research group, focusing on hardware security, RISC-V processors, and reliability of deep learning systems. He earned his Ph.D. in Information Engineering from the University of Pisa (2013), with prior postdoctoral research at CNR and Politecnico di Milano. His research spans hardware Trojans, microarchitectural attacks (e.g., Spectre/Meltdown), fault-tolerant design, and radiation-hardened systems. Notable achievements include winning the TTTC's E. J. McCluskey Doctoral Thesis Award (2014) and multiple best paper awards at IEEE conferences. He teaches courses on hardware accelerators and computer fundamentals, and collaborates with industry partners like TDS-Space and ESA on satellite systems and secure RISC-V cores. Research interests include: Hardware Security (Trojans, Side-Channel Attacks) Secure RISC-V Processor Design Deep Learning Reliability Fault-Tolerant Systems Selected articles highlight work on benchmarking deep learning resilience, transient execution attacks on RISC-V, and radiation effects mitigation. His work bridges theory and practice, addressing challenges in embedded systems, space computing, and cybersecurity. Grants and collaborations emphasize applied research in dependable and secure embedded systems.

Utpal BoraView profile

Researcher

• Computer Architecture
• Programming Languages
• Semantics
• +3 more

Utpal Bora is a Researcher at the University of Cambridge's Department of Computer Science and Technology. His research focuses on Programming Languages, Semantics, Verification, and Computer Architecture with an emphasis on static analysis of parallel programs, compiler optimization techniques, and performance analysis. He has contributed to projects such as LLOR (automated OpenMP program repair) and Llov (static data-race detection for OpenMP). His work bridges compiler design, parallel computing, and formal methods to improve software reliability and hardware efficiency. Research Interests: Static Analysis of Parallel Programs Compiler Optimization (LLVM) Data-Race Detection in OpenMP Instruction-Level Parallelism (ILP) Performance Modeling (CPI Analysis) Formal Verification of Concurrent Systems Recent work trends show a focus on enhancing parallel programming correctness through automated repair and static analysis tools, alongside optimizing code execution via compiler-level transformations and hardware architecture improvements. His contributions address critical challenges in parallel computing scalability and compiler-driven performance enhancement.

Dmitry EvtyushkinView profile

Associate Professor

• Computer Systems Security
• Microarchitecture Security
• Side-Channel Attacks
• +5 more

Dmitry Evtyushkin is an Associate Professor in the Department of Computer Science at William & Mary. He holds a Ph.D. in Computer Science from Binghamton University, advised by Prof. Dmitry Ponomarev (Binghamton) and Prof. Nael Abu-Ghazaleh (UC Riverside). His research focuses on microarchitecture security, including side/covert channels, isolated execution mechanisms, and secure hardware design. He is particularly known for pioneering work on 'microarchitectural weird machines' to explore hidden CPU vulnerabilities and developing defenses against branch predictor exploits. His research is supported by grants such as the NSF CAREER Award (2022), Coastal Virginia Center for Cyber Innovation (2022), and Intel Side Channel Academic Programme (2018-21). Current projects include secure branch predictor designs, mitigating transient execution attacks, and uncovering novel vulnerabilities in CPU interconnects and memory controllers. Education: Ph.D. in Computer Science, Binghamton University Grants: NSF CAREER, NSF CRII, Intel SCAP, Qualcomm gifts Labs/Teams: Research group at William & Mary focusing on hardware security His work bridges microarchitecture and cybersecurity, aiming to enhance system security without compromising performance.

• Computer Science Education
• Programming Education
• Computer Architecture
• +4 more

Sohum Sohoni is a Professor in the School of Computing and Augmented Intelligence within the Ira A. Fulton Schools of Engineering at Arizona State University. His research spans computer science education, programming pedagogy, computer architecture, and image quality assessment with GPU acceleration. He has developed innovative educational approaches for computer architecture courses using the PLP instruction set architecture and has contributed significantly to understanding programming education through analysis of error messages and embedded questions. His research interests focus on Computer Science Education , particularly programming education techniques, computer architecture pedagogy, and engineering education methods. He has made substantial contributions to understanding how students learn programming concepts, develop effective debugging skills, and comprehend computer architecture principles. His work bridges theoretical computer science concepts with practical educational applications, emphasizing hands-on learning experiences and innovative assessment methods. His publication trends reveal a strong focus on computer science education research with particular emphasis on programming education (2015-2018), computer architecture education using PLP (2014-2017), and image quality assessment with GPU acceleration (2012-2018). His work consistently combines theoretical computer science concepts with practical educational applications, demonstrating his commitment to improving how computing concepts are taught and learned. His advising work includes mentoring students like Christopher Mar, Harsha B. M. Kadekar, Shaowen Lu, Thien D. Phan, and Vignesh Kannan, who have co-authored publications with him across various computing education topics. His research has been supported through various educational technology projects focused on online learning environments, software engineering education, and computer architecture instruction. He has been actively involved in developing virtualized learning environments for IoT education, creating innovative approaches for software engineering education, and designing effective methods for teaching computer architecture concepts. His work demonstrates a consistent commitment to improving computing education through evidence-based pedagogical approaches and technological innovation.

• Computer Architecture
• Heterogeneous Parallel Systems
• GPU Computing
• +4 more

Juan Luis Aragon Alcaraz is a Full Professor in Computer Architecture at the University of Murcia (Spain), affiliated with the Faculty of Informatics and the Department of Computer Engineering and Technology. He obtained his PhD in Computer Engineering from the University of Murcia in 2003 and held a postdoctoral position as a Visiting Assistant Professor and Researcher at the University of California, Irvine. He has held visiting researcher positions at EPFL (2013) and Princeton University (2015–2022). His research focuses on computer architecture, emphasizing heterogeneous parallel systems, GPUs, memory hierarchies, and energy-efficient microarchitecture design. He has advised 7 PhD theses and co-authored over 60 publications in top-tier conferences and journals. His work includes contributions to GPU-accelerated medical imaging, energy-efficient graphics pipelines, and hardware-software co-design for parallel systems. Key research trends in his articles include optimizing GPU performance for real-time applications, energy efficiency in graphics rendering, and scalable latency tolerance in manycore systems. His patents include innovations in presbyopia correction devices leveraging GPU and FPGA technologies. Dr. Aragón has taught numerous courses in computer architecture and design, including Computer Architecture and Organization, Advanced Aspects in Multicore Architectures, and Embedded Systems Technologies. His labs and collaborations span academic-industrial partnerships, emphasizing practical applications of his theoretical contributions.

Sander StuijkView profile

Associate Professor

• Embedded Systems
• Signal Processing
• Multi-Core Architectures
• +3 more

Sander Stuijk is an associate professor at the Department of Electrical Engineering of Eindhoven University of Technology, chairing the Electronic Systems (ES) group. His research focuses on design methodologies for embedded signal processing applications in high-tech systems like industrial manufacturing, automotive, and healthcare. He develops high-level compilation strategies for heterogeneous multi-core platforms, with interests in efficient code generation and resource allocation. Prof. Stuijk holds leadership roles including chairing the ES group, serving on the board of 4TU.NIRICT (a Dutch ICT research consortium), and coordinating the Embedded Systems master program. He contributes to national ICT initiatives through ICT Next Generation, a network for mid-career academics. He also chaired the Department Council (2016-2018) and participates in TPC activities. His research spans streaming applications, real-time systems, and multi-processor architectures. Notable projects include the PROMES initiative (programming embedded multi-media systems) and the MNEMEE project (automated MPSoC design). His work emphasizes predictable and energy-efficient computing, with applications in healthcare monitoring (e.g., remote PPG, thermal imaging) and reconfigurable systems. Prof. Stuijk has advised numerous PhD/Master students and led projects like FORSEE, VSM, and SenSafety. His publications include over 70 journal/conference papers, covering topics like neuromorphic computing, GPU optimization, and medical signal processing. He actively engages in academic service, including organizing SCOPES workshops and serving on editorial boards.

• Computer Architecture
• Reliable Computer Design
• Fault Detection and Recovery
• +3 more

Gülay YALÇIN is an Assistant Professor at Abdullah Gul University since 2016. She holds a Ph.D. in Computer Architecture from Universitat Politècnica de Catalunya (2014), an MS in Computer Engineering from TOBB University (2007), and a BS in Computer Engineering from Hacettepe University (2003). Her research focuses on reliable computer design, fault detection, parallel architectures, and low-power systems. She has led projects like ParaDIME (2012-2015) and Velox (2008-2011), advancing energy-efficient computing and transactional memory. Education: Ph.D., Universitat Politècnica de Catalunya, Department of Computer Architecture (2008-2014) M.S., TOBB University of Economics and Technology, Computer Engineering (2007) B.S., Hacettepe University, Computer Engineering (2003) Research Interests: Her work spans fault-tolerant computing, energy-efficient designs, hardware transactional memory, and parallel architectures. She has contributed to error detection techniques leveraging comparators, voltage scaling for reliability, and novel cache designs like Flexicache. Key Projects: ParaDIME (2012-2015): Energy minimization in data centers. Shortlisted for the 2016 Innovation Radar Prize. Velox (2008-2011): Transactional memory for multi-core systems. Reliable Embedded Processors (2007-2008): Fault mitigation in embedded systems. Teaching: She teaches undergraduate courses on 'Exploring Profession' and graduate courses on 'Computer Architecture.' Advising: Currently advising M.S. student Albert Njoroge Kahira on reliable microarchitecture design. Labs/Teams: Active in the Barcelona Supercomputing Center (BSC) during her postdoc (2014-2015) and as a graduate researcher (2009-2014).

Christian EichlerView profile

Researcher

• Real-Time Systems
• Cyber-Physical Systems
• Embedded Systems
• +5 more

Christian Eichler is a researcher at Friedrich-Alexander University Erlangen-Nuremberg, affiliated with the Department of Computer Science (INF) and the Chair of Computer Science 4 (System Software). His work focuses on real-time systems, embedded computing, and cyber-physical systems. His research in real-time and embedded systems includes invasive computing frameworks, deterministic I/O management, and energy-constrained system analysis. He has contributed to tools like TASKers and GenEE for benchmarking and timing analysis of real-time software. His publications from 2017-2022 span conferences like HICSS, CCS, ISORC, and workshops on benchmarking, invasive computing, and cyber-physical systems. Key co-authors include Wolfgang Schröder-Preikschat and other researchers from FAU and international institutions.

Marco GuarnieriView profile

Associate Professor

• Security and Privacy
• Program Verification
• Programming Languages
• +3 more

Marco Guarnieri is an Associate Professor at the IMDEA Software Institute in Spain. His research focuses on the design, analysis, and implementation of secure systems, with particular emphasis on security at the hardware-software boundary. His work addresses microarchitectural attacks (e.g., Spectre), secure compilation, hardware verification, and database security. Education PhD in Computer Science, ETH Zurich (2017) MSc in Computer Engineering, Università degli Studi di Bergamo (2012) BSc in Computer Engineering, Università degli Studi di Bergamo (2010) Research Focus Guarnieri's research spans several interconnected areas: Hardware-Software Security: Developing foundations for reasoning about security at the hardware-software boundary Microarchitectural Attacks: Analysis and mitigation of speculative execution attacks Formal Methods: Application of verification techniques to security problems Secure Compilation: Ensuring compiler-generated code maintains security guarantees Database Security: Information flow control and access mechanisms Research Trends His recent publications demonstrate a strong focus on hardware-software co-design for security, with increasing emphasis on formal verification of processor security (especially RISC-V), automated testing of speculation countermeasures, and leakage contract frameworks. His work consistently bridges theoretical foundations with practical implementations. Awards and Honors Best Paper Award at CCS 2024 Distinguished Paper Award at CCS 2023 Distinguished Paper Award at CCS 2022 Best Paper Award at S&P 2021 Research Leadership Guarnieri leads research projects on secure speculation and hardware-software contracts. He actively recruits research interns, PhD students, and postdocs to work on security at the hardware-software interface. His group develops tools like SPECTECTOR for detecting speculative information flows and LeaVe for verifying processor security.

K. G. KarthikeyanView profile

Associate Professor

• Computer Architecture
• Machine Learning
• Parallel Computing
• +3 more

K. G. Karthikeyan is an Associate Professor in the Department of Civil and Environmental Engineering at the University of Wisconsin-Madison. His research focuses on cutting-edge advancements in computer architecture, machine learning, and hardware acceleration. Primary Affiliation: Civil and Environmental Engineering Additional Affiliation: Environmental Chemistry and Technology His work spans multiple domains including: Computer architecture optimization GPU acceleration techniques Dataflow processing models Transformer efficiency improvements Moore's Law alternatives Hardware-software co-design Research trends from his publications show a strong emphasis on: Breaking traditional computing limitations Developing energy-efficient architectures Creating flexible acceleration frameworks Advancing deep learning hardware Exploring von Neumann alternatives Pioneering open-source computing platforms

• Hardware Security
• Cryptography
• Fault Attacks
• +7 more

Sayandeep Saha is an Assistant Professor in the Department of Computer Science and Engineering at Indian Institute of Technology Bombay. His research focuses on Hardware Security and Cryptography, with emphasis on Fault Attacks, Side-Channel Attacks, and Post-Quantum Cryptography. He leads the SHarC research group and actively collaborates with international institutions. Education: PhD in Computer Science and Engineering from Indian Institute of Technology Kharagpur Postdoctoral Experience: NTU Singapore (2022-2023), UCLouvain Belgium (2023-2024) His research explores hardware vulnerabilities in cryptographic systems, covering: Fault Attacks on Symmetric and Post-Quantum Cryptosystems Side-Channel Analysis of Power/EM Radiation Microarchitectural Attacks (Spectre/Meltdown variants) Countermeasure Development and Formal Verification Recent research trends include Rowhammer attacks, randomized cache designs, and fault propagation in cryptographic circuits. His work has been recognized in top conferences like ICCAD, USENIX Security, and CHES. Awards: Top Picks in Hardware and Embedded Security 2024 (EUROCRYPT 2020 paper) He is currently hiring Project Research Assistants for the RISC-V-based SISHAM project and supervises PhD students in hardware security research.

• Cybersecurity
• Formal Verification
• Software Engineering for Distributed Systems
• +2 more

Roberto Guanciale is a Lecturer at KTH Royal Institute of Technology , affiliated with the Department of Theoretical Computer Science under the School of Electrical Engineering and Computer Science. He teaches and examines courses such as Cybersecurity Overview , Software Security , Applied Cryptography , and Degree Projects focusing on cybersecurity, communication systems, and distributed software engineering. His research interests lie in cybersecurity , formal verification , and software engineering for distributed systems . His recent publications address formal methods for securing P4 programs, symbolic execution for binary verification, and flow security in microarchitectures. These works emphasize rigorous mathematical approaches to network and hardware security. Teaching Roles: Cybersecurity Overview Course (DD2391) - Course Manager The Role of the Cybersecurity Engineer (DD2303) - Teacher Software Security (DD2460) - Teacher Project in Cybersecurity (DD2394) - Examiner and Course Coordinator

Mengjia YanView profile

Associate Professor

• Computer Architecture
• Security
• Hardware Security
• +4 more

Mengjia Yan is an Associate Professor in the Electrical Engineering and Computer Science (EECS) Department at MIT, affiliated with the Computer Science and Artificial Intelligence Laboratory (CSAIL). Her research focuses on computer architecture and security, particularly side-channel attacks and defenses. She leads the MATCHA group (microarchitecture attacks and challenges), exploring vulnerabilities in microarchitecture and designing robust defenses. Educated at Zhejiang University (B.S.) and the University of Illinois at Urbana-Champaign (UIUC, Ph.D.), she joined MIT after completing her PhD under Prof. Josep Torrellas. Her work bridges hardware security, speculative execution, and machine learning, with notable contributions like PACMAN (ARM pointer authentication attacks) and Oreo (ASLR protection). Teaching includes courses on computer system architecture (6.5900/6.823) and secure hardware design (6.5950/6.888). She has advised numerous students, including Rhodes Scholars and recipients of fellowships like NSF and NDSEG. Awarded the Intel Rising Star Faculty Award (2022), NSF CAREER Award (2021), and multiple best paper awards, she also co-organizes conferences like PLARCH and MAD. Current projects include SecureLoop (DNN accelerator security) and formal verification frameworks for secure processors. Labs/Teams: MATCHA Group at MIT CSAIL. Active in academic service, serving on program committees for ASPLOS, ISCA, and MICRO.

Boris GrotView profile

Professor

• System architectures for datacenters
• Processor architecture and microarchitecture
• Memory systems and interconnection networks
• +3 more

Boris Grot is a Professor holding the Personal Chair of Computer Systems and Architecture in the School of Informatics at the University of Edinburgh, where he leads research on optimizing large-scale datacenter efficiency through hardware-level innovations in server architectures, memory systems, and interconnect networks. His academic background includes a PhD in Computer Science from The University of Texas at Austin (thesis: scalability and quality-of-service in on-chip networks) followed by post-doctoral research at EPFL's Parallel Systems Architecture Lab. Research focuses on critical infrastructure challenges driven by three converging factors: mobile/embedded system constraints (battery, thermal, form factor), massive-data applications (search, social networking), and enterprise cloud migration. Key problem domains include: Re-inventing server architectures for specialized datacenter workloads Overcoming semiconductor voltage scaling limitations Addressing the 1.3% global energy footprint of datacenters (growing rapidly) Designing football-field-scale facilities handling 5-20 MW power loads He directs the EASE Lab investigating these challenges, emphasizing the economic and environmental urgency as datacenter deployment accelerates worldwide. No scientific awards or student advisees were specified in the source material, and grant details remain undocumented in the provided text.