Hanjun Kim is a researcher at Yonsei University, focusing on compiler design, machine learning optimization, and hardware-aware programming techniques. His work bridges theoretical research with practical implementations in embedded systems and security domains. Research Interests Compiler-driven optimization for PIM (Processing-in-Memory) architectures Homomorphic encryption compiler design Parallel computing for DNN/LLM inference Network function program analysis Recent research trends include: application of compiler techniques to optimize resource utilization in heterogeneous computing environments, particularly for AI workloads and secure computation. His publications demonstrate expertise in tackling performance bottlenecks through architectural and compiler co-design. Conference Service 2025 SPLASH OOPSLA Review Committee 2025 LCTES Program Committee 2024 CGO Program Committee 2023 LCTES Program Committee 2022 CGO Organization Committee 2020 LCTES Program Committee
Jignesh Patel is a Professor in the Computer Science Department at Carnegie Mellon University, specializing in database systems and data-intensive computing. His research focuses on hardware-software synergy for high-performance databases and democratizing data analytics through no-code interfaces. He co-founded DataChat, a startup focused on intuitive data analytics platforms. He holds fellowships from AAAS, ACM, and IEEE, along with teaching awards. His work emphasizes building systems that leverage novel hardware and user-friendly interfaces. Research interests include scalable data platforms, LLM-based query interfaces, and optimizing database performance through hardware collaboration. Notable projects include the Quickstep data platform and the Ava conversational interface. Awards: Fellow of AAAS, ACM, IEEE; Multiple Teaching Awards Labs/Teams: CRISP (Intelligent Storage and Processing), DataChat startup
Charles McGuffey is an Assistant Professor in the Computer Science Department at Reed College, part of the Division of Mathematical and Natural Sciences. He joined Reed in 2021 following a Ph.D. in Computer Science from Carnegie Mellon University and dual bachelor’s degrees in Computer Engineering and Computer Science from Clarkson University. Education: Ph.D. in Computer Science (Carnegie Mellon University, 2021); B.S. in Computer Engineering and Computer Science (Clarkson University, 2016). His research focuses on computer systems and algorithm design, particularly hardware-software interactions for performance optimization. Key areas include Processing-in-Memory (PIM) , caching techniques, memory hierarchy management, and non-volatile memory systems. He explores understudied aspects of computer design to enhance practical efficiency. Recent publications emphasize kd-trees , trie structures , and algorithms for asymmetric memory systems. Topics like spatial locality , granularity change , and writeback-aware caching reflect his work on memory-centric computing. He engages in summer research projects supported by Reed’s Summer Scholarship Fund, focusing on innovative computer systems and algorithm development.
Sai Manoj Pudukotai Dinakarrao is an Assistant Professor in the Department of Electrical and Computer Engineering at George Mason University's College of Engineering and Computing. He leads the HArt (Hardware and AI Research) Group, focusing on cutting-edge research at the intersection of hardware security and artificial intelligence. His educational journey includes a BTech in Electronics and Communication Engineering from Jawaharlal Nehru Technological University (2010), an MTech in Information Technology from International Institute of Information Technology Bangalore (2012), and a PhD in Electrical Engineering from Nanyang Technological University, Singapore (2015). Following his doctoral studies, he completed post-doctoral research at TU Wien, Vienna (2015-2017) and George Mason University (2017-2018). Dr. Dinakarrao's research spans hardware security, adversarial machine learning, IoT networks, and deep learning in resource-constrained environments. His work integrates hardware design with AI techniques to address security challenges in computing systems, with particular focus on side-channel attack detection, malware detection in IoT networks, on-chip security, and hardware accelerator design for machine learning applications. His research has resulted in numerous publications in top-tier conferences and journals including IEEE Transactions, ACM conferences, and Design Automation Conference. Analysis of his recent publications reveals a strong trend toward hardware security solutions using machine learning techniques. His work increasingly focuses on Processing-in-Memory architectures, energy-efficient security solutions for IoT devices, and innovative approaches to hardware Trojan detection. Many publications demonstrate interdisciplinary collaboration across electrical engineering, computer science, and cybersecurity domains. Young Research Fellow Award at Design Automation Conference (DAC) 2013 Best paper award at International Conference on Data Mining (ICDM) 2019 Best paper award at International Conference on Consumer Electronics (ICCE) 2020 Best paper nomination at International Conference on Computer-Aided Design (ICCAD) 2019 Best paper nomination at Design Automation and Test in Europe (DATE) 2018 Dr. Dinakarrao has successfully mentored numerous PhD and MS students, with alumni securing positions at AMD-Xilinx, US Government agencies, and academic institutions. His research has been supported by significant grants from NSF, DARPA, and Virginia Commonwealth Cyber Initiative. Current projects include securing supply chains with UVA, developing novel architectures for machine learning acceleration, and creating energy-preserving cryptography protocols. The HArt Group maintains active collaborations with industry partners including AMD-Xilinx and government agencies. The lab focuses on practical implementations of theoretical security concepts, with particular emphasis on creating deployable security solutions for real-world hardware systems. Current research directions include intermittent computing with energy harvesting, hardware fuzzing techniques, and robust machine learning models resistant to adversarial attacks.
Dr. Huan Hu is an Assistant Professor at the School of Microelectronics, Southern University of Science and Technology (SUSTech), Shenzhen, China. He holds a Ph.D. from Washington State University (2021) and has worked in industry at Skyworks Solutions and Biotronik/MSEI on low-power circuits for IoT and biomedical applications. Education: Ph.D., Washington State University, 2021 M.S., Oregon State University, 2015 B.S., University of Electronic Science and Technology of China, 2013 His research focuses on ultra-low power analog/mixed-signal integrated circuits for biomedical wearable/implantable devices and artificial intelligence of things, including applications in sensor interfaces, energy-efficient radios, and in-memory computing architectures. Recent publications highlight advancements in time-domain processing , biofuel cell integration , and injection-locked transmitters for IoT and biomedical applications, with awards including Shenzhen Overseas High-level Talent (2022) and IEEE RFIC Best Student Paper Award Nomination (2020). Scientific Awards: Shenzhen Overseas High-level Talent (Class C), 2022 RFIC Best Student Paper Award Nomination, 2020 Alaska Airline Travel Award, 2018 WSU Grand Challenges Fellowship, 2016-2017 OSU Laurels Scholarship, 2014-2015 He seeks motivated researchers for Research Assistant Professor , Postdoctoral Fellow , and Graduate Student positions in his group. Visit his lab page for details.
Dr. Sihang Liu is an Assistant Professor in the School of Computer Science at the University of Waterloo. Prior to this role, he served as a visiting faculty member at SystemsResearch@Google. He holds a PhD from the University of Virginia, where his research was supported by the Google Fellowship Award. His academic career has been marked by contributions to computer architecture, systems, and persistent memory technologies. Dr. Liu's research interests span computer architecture, systems, and cybersecurity, with a focus on persistent memory systems, energy-efficient computing, and data center optimization. His work bridges hardware-software co-design and explores challenges in scalable computing, fault tolerance, and sustainable AI systems. His recent publications highlight advancements in adaptive memory tiering (HybridTier), carbon intensity forecasting (EnsembleCI), and securing persistent memory (Side-Channel Attacks on Optane). These contributions underscore his commitment to addressing critical issues in modern computing systems' performance, security, and environmental impact. Awards: Google Fellowship Award (PhD), NVMW Memorable Paper Award Finalist (2019), 2019 MICRO Top Picks Honorable Mention Professional Service: Program committees for ISCA, MICRO, ASPLOS; Artifact evaluation roles in leading conferences As an advisor, Dr. Liu mentors a diverse group of students, including current PhD candidates Henry Tian and Desen Sun, and numerous undergraduates. His lab focuses on innovation in sustainable computing and resilient systems design.
Jose Luis Abellan Miguel is a Ramón y Cajal Fellow and Tenure-Track Associate Professor at the University of Murcia's Department of Computer Engineering and Technology. He leads the EcoArTech team and is a European R3 researcher. Previously, he held roles at the University of Ferrara, Boston University, and Universidad Católica de Murcia. His research focuses on GPU architectures, accelerators for machine learning, and privacy-preserving computing, particularly Fully Homomorphic Encryption (FHE). He has authored over 70 peer-reviewed publications and contributed to conferences like ISCA, HPCA, and MICRO. Education: Bachelor's, Master's, and PhD in Computer Science and Engineering (University of Murcia, 2007–2012) Research Interests: Abellan's work emphasizes architectural enhancements for GPU systems, customized accelerators for ML and FHE, and efficient synchronization/communication in many-core architectures. His contributions include tools like MGPU-Sim and STONNE for simulation, and frameworks like FIDESlib for FHE on GPUs. Recognition: HiPEAC Paper Awards (2011, 2019–2024) Top Picks in Hardware and Embedded Security 2024 European R3 Certificate (2024) Editorial roles at ACM TACO and Frontiers in Electronics Grants & Leadership: Recipient of a Ramón y Cajal fellowship and a Consolidación Investigadora grant. He chairs sessions at conferences like ISPASS and serves on TPCs for venues including DATE, HPCA, and MICRO. His lab collaborates with institutions like Georgia Tech, Northeastern University, and Intel. Labs/Teams: He leads the EcoArTech team, focusing on next-gen computing systems via architectural simulators. Collaborators include researchers from MIT, Boston University, and industry partners like NVIDIA and Intel.
Minxuan Zhou is an Assistant Professor of Computer Science at Illinois Institute of Technology. His research focuses on systems, high-performance computing, and parallel computing with an emphasis on processing-in-memory (PIM) acceleration, fully homomorphic encryption (FHE), and hyperdimensional computing. He holds a Ph.D. and M.S. in Computer Science from the University of California San Diego, and a B.S. in Computer Science and Technology from Beihang University. His work spans hardware-software co-design, cryptographic acceleration, and energy-efficient computing systems. Research Interests Processing-in-Memory (PIM) architectures for accelerating machine learning and graph processing Hardware acceleration for secure computation (FHE) Hyperdimensional computing frameworks for edge AI Thermal-aware design and memory optimization in 3D systems Recent Research Trends Recent publications emphasize co-optimization techniques for PIM architectures, FHE hardware acceleration, and privacy-preserving machine learning. His work often bridges theoretical algorithm design with practical hardware implementations using novel memory technologies like ReRAM and 3D-stacked memory. Grants & Labs Engaged in cutting-edge research through collaborations on projects involving PIM accelerators and encrypted computation systems. His lab focuses on developing full-stack solutions for next-generation computing architectures.
Prof. Bongjin Kim is an Associate Professor in the School of Electrical Engineering at KAIST. Previously, he held a position as Assistant Professor at UCSB. His research focuses on secure hardware design, machine learning, and alternative computing architectures, including Ising machines and processing-in-memory systems. He leads the Kim Circuit Research Lab, which designs novel VLSI circuits for AI, robotics, and optimization problems. Education: PhD, University of Minnesota (ECE); MS, Pohang University of Science and Technology (ECE). He has advised over 20 graduate and undergraduate students, with notable advisees including Dr. Jooyoung Bae (PhD 2025) and Dr. Yihao Wu (PhD 2025). His work has been recognized with awards such as the NSF CAREER Award (2023) and the NRF Outstanding Young Scientist Grant (2025). Recent research includes developing a 28nm Ising machine for combinatorial optimization (A-SSCC 2024), a scalable bit-serial accelerator for PDEs (TCAS-I 2024), and a reconfigurable compute-in-memory macro (JSSC 2024). He serves on technical committees for ISSCC, A-SSCC, and ESSERC, and chairs sessions at ESSERC 2025 and A-SSCC 2025. Lab activities include the Basic Research Lab (NRF-funded) for Ising Foundation Model development and the C2 research project on ML ASIC accelerators. His group collaborates with institutions like SLAC, IME (A*STAR), and KAIST, fabricating over 30 test chips using 28nm/65nm processes.
Trevor Mudge is a Professor in the Department of Computer Science and Engineering at the University of Michigan. His work focuses on domain-specific architectures, reconfigurable computing, and energy-efficient processors. He leads a research group emphasizing collaborative innovation, with weekly meetings to discuss progress and foster interdisciplinary collaborations with institutions like MIT and Technion. His research interests include hardware-software co-design, near-memory processing, and accelerators for graph analytics and machine learning. He advocates for student autonomy in research direction, encouraging them to explore novel ideas while providing mentorship through frequent one-on-one interactions and 'extreme editing' sessions for manuscript refinement. Dr. Mudge actively supports student internships aligned with their research, particularly in industry partnerships that enhance their academic work. His publications reflect a strong emphasis on specialized architectures for wireless communication, sparse matrix computations, and low-power embedded systems. His group's approach to advising prioritizes flexibility, with communication channels like email, Slack, and virtual whiteboards enabling continuous feedback. Vacations and time away are accommodated with advance notice, emphasizing student well-being and productivity balance.
Ryan Lively is a Professor in the Department of Chemical and Biomolecular Engineering at Georgia Institute of Technology's College of Engineering, specializing in energy-efficient separation processes using advanced membranes and nanoporous materials. His research focuses on addressing global energy challenges through innovative materials and modular device design. B.S. (2006) Georgia Institute of Technology Ph.D. (2011) Georgia Institute of Technology Research interests include: Membrane and adsorbent development for carbon capture 3D-printed separation devices Polymer of intrinsic microporosity (PIM) modifications Natural gas liquid fractionation and solvent recovery Mechanistic studies of gas transport in hybrid membranes Techno-economic analysis of carbon capture systems Recent publications span 2025 and 2024 , with emphasis on: Direct air capture (DAC) optimization Organic solvent reverse osmosis (OSRO) systems Hybrid membrane synthesis techniques Computational modeling of transport phenomena Porous liquid material design 3D printing for contactor fabrication Scientific recognition includes: 2024 Stratis V. Sotirchos Memorial Award As advisor to PhD students and postdocs including Mingyu Song, Pavithra Shyam, and Younhwa Kim, Lively leads the Lively Lab at Georgia Tech. The lab operates advanced facilities for hollow fiber spinning, BET surface area analysis, membrane testing, and cyclic adsorption processes, while participating in the Georgia Tech Leadership Challenge and AIChE conferences.
Overview Pim Huijnen is an Assistant Professor in Digital Cultural History at the Department of History and Art History, Faculty of Humanities at Utrecht University. His research focuses on applying computational methods to study the history of science, ideas, and popular culture. He specializes in conceptual history, digital text analysis, and the intersection of scientific discourse with political and commercial domains. Research Interests Computational analysis of historical sources (newspapers, texts) Conceptual shifts in scientific discourse Temporal patterns in public and political discourse Digital humanities methodologies He is affiliated with the Utrecht Centre for Digital Humanities and actively involved in projects like Looking Back in Newspapers and ShiCo (visualizing shifting concepts over time). As vice-editor-in-chief of BMGN-LCHR and board member of the Royal Netherlands Historical Society, he contributes to academic governance and scholarly communication. Teaching Teaches courses on digital humanities, historical methodology, and digital pedagogy. Supervises theses in digital history, media history, and science communication. Key Projects Develops tools for text mining and temporal analysis Investigates replication practices in historical research Pioneers digital literacy frameworks for humanities education
Sarma Vrudhula is a Professor at the School of Computing and Augmented Intelligence, Arizona State University (ASU). He holds a Ph.D. in Electrical Engineering from the University of Southern California (1985). Previously, he was a professor at the University of Arizona and served as the founding director of the NSF UA/ASU Center for Low Power Electronics. He is an IEEE Fellow recognized for contributions to low-power and energy-efficient digital circuit design. Educations: Ph.D. Electrical Engineering, University of Southern California (1985) M.S. Electrical Engineering, University of Southern California (1980) Bachelor's in Mathematics (Computer Science and Mathematical Statistics), University of Waterloo, Canada (1976) Research Interests: His work focuses on design automation, energy management in digital systems, statistical analysis of process variations, threshold logic circuits, and emerging technologies. He has pioneered methodologies for low-power VLSI design, thermal management of multi-core processors, and hardware implementations of threshold logic using spintronic devices. Publications: His recent research includes scalable energy-efficient architectures for AI, in-memory computing, and reconfigurable threshold logic gates. Key topics span energy efficiency in edge computing, neuromorphic systems, and sustainable VLSI design. Awards: IEEE Fellow (2005) Best Paper Award (2008) for macro cell characterization methodology Service & Grants: He led the NSF IUCRC Consortium for Embedded Systems and served on editorial boards. His grants include projects on threshold logic synthesis, energy-aware embedded systems, and hardware acceleration for neural networks. Courses Taught: Algorithmic Foundations of CAD for Digital Systems Computer Architecture Discrete Mathematics for Engineers
Amer Qouneh serves as an Associate Professor in the Department of Electrical and Computer Engineering at Western New England University, where his research centers on computer architecture, high-performance computing, data centers, Internet of Things (IoT), and embedded systems with emphasis on energy efficiency and practical implementations. Education: Ph.D. in Computer Engineering, University of Florida, 2014 M.S. in Computer Engineering, University of Florida, 2010 M.S. in Computer Science, University of Wisconsin-Milwaukee, 2007 M.S. in Electrical Engineering, Fairleigh Dickinson University, 1988 B.S. in Electrical Engineering, Fairleigh Dickinson University, 1985 Dr. Qouneh's research integrates theoretical innovation with real-world applications across multiple domains. His computer architecture work addresses thermal resilience in photonic networks and processing-in-memory systems, while his data center research focuses on renewable energy integration, resource allocation, and containerization. In IoT and embedded systems, he develops practical solutions like solar array trackers and edge-based machine learning deployments, demonstrating a commitment to sustainable and accessible technology education. Publication analysis from 2009-2022 reveals a strategic evolution from foundational work in transactional memory and containerization toward advanced energy-efficient architectures. His recent output emphasizes IoT educational integration and embedded AI applications, maintaining consistent contributions to top venues like IEEE Transactions on Parallel and Distributed Systems while adapting to emerging computational challenges in green computing and edge intelligence. Dr. Qouneh actively mentors undergraduate researchers, evidenced by multiple co-authored conference papers on IoT implementations and curriculum development. His scholarly impact spans both technical innovation in data center optimization and educational leadership in modernizing engineering curricula for emerging technologies.
Vijaykrishnan Narayanan is a Distinguished Professor in the Department of Computer Science and Engineering at Pennsylvania State University . His research focuses on ferroelectric memory systems , energy-efficient computing , and neuromorphic engineering , with applications in deep learning , edge computing , and secure hardware design . He leads projects such as EFRI BRAID (Neuroscience-Inspired Visual Analytics) and FuSe-TG (Heterogeneous Ferroelectronics for Big Data Analytics). Research Interests Compute-in-Memory (CIM) architectures Ferroelectric Field-effect Transistors (FeFETs) Low-power VLSI design Hardware security mechanisms Scientific Contributions Over 707 research outputs and 26 grants Key contributor to UN Sustainable Development Goals via energy-efficient computing NSF grants for projects like Ferro-CoDE (combinatorial optimization) and INSECT NET (entomology-computer science collaborations)
