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Kanad Basu is an Associate Professor in the Department of Electrical, Computer, and Systems Engineering at The University of Texas at Dallas, Jonsson School of Engineering and Computer Science. He leads the Trustworthy and Intelligent Embedded Systems (TIES) lab, focusing on hardware security, reliability, and emerging computing paradigms. His research spans AI hardware, quantum computing, functional safety, and hardware-based security validation. Research Interests: His work emphasizes improving the trustworthiness of modern hardware systems. Key areas include hardware security (e.g., side-channel analysis, hardware trojans), functional safety in AI accelerators, quantum computing security and verification, and post-silicon validation techniques. He combines formal methods, machine learning, and hardware design to address vulnerabilities in SoCs, DNN accelerators, and quantum systems. Publication Trends: Recent publications (2023–2025) show a strong focus on interdisciplinary research, integrating AI/ML with hardware security, quantum computing, and functional safety. There is a growing emphasis on using large language models for assertion generation, symbolic execution for hardware fuzzing, and graph neural networks for quantum circuit analysis. His work frequently appears in top venues like DAC, DATE, HOST, ISVLSI, and IEEE journals. Scientific Awards: NSF CAREER Award, 2025 IEEE Top Picks in Test and Reliability, 2024 and 2023 Multiple Hack@DAC Prizes (2nd and 3rd) Best Paper Award at VLSI Design 2011 Assistant Professor Award at UTD Jonsson School, 2024 Nominated for Blavatnik Awards for Young Scientists, 2019 Advising and Grants: Dr. Basu has mentored numerous PhD, MS, and undergraduate students, many of whom have published in top-tier venues. He leads the TIES lab, which has received significant recognition, including the NSF CAREER Award. He actively collaborates across disciplines, advising students on topics ranging from quantum computing to AI hardware and functional safety. His lab produces high-impact research with real-world applications in automotive, cloud, and embedded systems. Labs and Teams: He leads the Trustworthy and Intelligent Embedded Systems (TIES) lab at UT Dallas, which fosters innovation in hardware security and reliability. The lab has produced award-winning work, including second prize at HACK@DAC 2025. He also serves on technical committees for IEEE DATE and HOST, and acts as Hardware Hacking Chair for IEEE HOST, indicating strong leadership in the hardware security community.

• Hardware Security
• System Security
• Hardware Reliability
• +10 more

Mohammad Karim, PhD, is a Professor in the Department of Electrical & Computer Engineering at the University of Massachusetts Dartmouth (UMass Dartmouth), affiliated with the College of Engineering. He previously held leadership roles including Provost, Executive Vice Chancellor for Academic Affairs, and Chief Operating Officer at UMass Dartmouth. His career includes serving as Vice President of Research at Old Dominion University (2004–2013), Dean of Engineering at City College of New York (2000–2004), and Head of Electrical and Computer Engineering at the University of Tennessee (1998–2000). He is an elected fellow of multiple prestigious organizations, including IEEE, OSA, and SPIE. Dr. Karim holds a BS Honors in Physics from the University of Dhaka (1976) and MS in Physics (1978) and MS/PhD in Electrical Engineering (1979/1981) from the University of Alabama. His research focuses on optical computing, pattern recognition, electro-optical systems, and sensors, with funding from agencies like the Office of Naval Research and NASA. He has authored 19 books, over 365 papers, and 13 book chapters, and served as guest editor for 36 journal special issues. His awards include Fellowships from IEEE, OSA, and the Bangladesh Academy of Sciences. He mentors students in MS/PhD programs and advises on research proposals. His work spans academic leadership, technical innovation, and interdisciplinary collaboration in engineering and optics.

• Optical Computing
• Information Processing
• Pattern/Target Recognition
• +5 more

Alan Mantooth is a Distinguished Professor holding the Twenty-First Century Research Leadership Chair in Engineering within the Department of Electrical Engineering at the University of Arkansas, Fayetteville. He serves as Director of the National Center for Reliable Electric Power Transmission (NCREPT), Executive Director for GRAPES (NSF I/UCRC) and SEEDS (DoE Center), and Deputy Director of the NSF Engineering Research Center for Power Optimization of Electro-Thermal Systems (POETS). His educational background includes: B.S. in Electrical Engineering, University of Arkansas M.S. in Electrical Engineering, University of Arkansas Ph.D. in Electrical Engineering, Georgia Institute of Technology Dr. Mantooth's research centers on analog/mixed-signal IC design, power electronics CAD, and semiconductor device modeling with emphasis on harsh-environment applications. His pioneering work in silicon carbide (SiC) and gallium nitride (GaN) power systems has enabled high-temperature operation for electric vehicles and renewable energy infrastructure, significantly advancing reliability in extreme conditions. His 2025 publications reveal strong trends toward AI-driven power electronics (e.g., SolarFormer++ for PV profiling), wide-bandgap device modeling (β-Ga2O3, SiC), and innovative packaging solutions. Key themes include reliability engineering for extreme environments, multi-physics optimization, and explainable AI for safety-critical power systems. Major scientific recognition includes: IEEE Fellow (2009) for power electronic device modeling Three R&D 100 Awards (2009, 2014, 2016) for SiC power modules IEEE Power Electronics Society Technical Achievement Award (2019) Multiple university teaching/research awards including SEC Faculty Achievement Award (2015) As an exceptional mentor (UA Outstanding Mentor 2006-2008), he co-founded Lynguent and Ozark Integrated Circuits. His centers NCREPT, GRAPES, and SEEDS have secured major funding from NSF, DoE, and industry partners, supporting over 350 refereed publications and numerous patents. Current research focuses on AI-enhanced power electronics, recyclable packaging, and next-generation wide-bandgap device characterization. He leads the NCREPT test facility and multi-institutional teams developing grid-connected power electronic systems, secure energy delivery architectures, and thermal management solutions for high-power-density applications, with direct impact on electric transportation and renewable energy integration.

• Analog and Mixed-Signal IC Design
• Power Electronics
• Semiconductor Device Modeling
• +3 more

Jing-Yang Jou is the current President and K.T. Li Chair Professor at National Central University in Taiwan. He holds MS (1983) and PhD (1985) degrees in Computer Science from the University of Illinois. His research focuses on logic synthesis, physical synthesis, design verification, CAD for low-power systems, and Network-on-Chips (NoC). With over 200 technical publications, he has made significant contributions to digital circuit design automation. Former Deputy Minister of National Science Council, Taiwan (2010-2012) Vice Chancellor for Academic Affairs, University System of Taiwan (2007-2010) Executive Director of National SoC Program (2007-2010) Director General of National Chip Implementation Center (2004-2007) Recipient of prestigious awards including IEEE Fellow distinction and multiple industry-academia collaboration recognitions. His career includes roles at AT&T Bell Laboratories (1986-1994) and GTE Laboratories (1985-1986). Research emphasizes bridging theoretical computer science with practical semiconductor design challenges.

• Computer-Aided Design (CAD)
• Digital Circuit Design
• Low Power Design
• +4 more

Dr. Bill D Carroll is a Professor of Computer Science and Engineering at The University of Texas at Arlington (UTA), where he has served since 1981. He previously held roles at Auburn University and visiting positions at UC Berkeley and the University of Washington. His academic leadership includes serving as Dean of UTA's College of Engineering from 2000 to 2011, during which the college saw significant growth in enrollment, research expenditures, and faculty. He is a Life Fellow of the IEEE and a licensed professional engineer in Texas and Alabama. Education: PhD, Electrical Engineering, University of Texas at Austin (1969) MS, Electrical Engineering, University of Texas at Austin (1966) BS, Electrical Engineering, University of Texas at Austin (1964) Research Interests: Cyber-physical systems IoT System-on-Chip (SoC) design Technology in education Online education Key Awards: Academy of Distinguished Service Leaders (2022) Academy of Distinguished Teachers (2021) IEEE Third Millennium Medal (2000) IEEE Fellow (1988) Grants & Service: Directed federal grants including NSF-funded projects on parallel processing and software tools. Chaired numerous committees at UTA, including the Faculty Senate and ABET accreditation efforts. Contributed to national initiatives like the IEEE’s accreditation policies and Texas engineering education standards. Teaching & Mentorship: Developed courses in digital logic design, system-on-chip design, and professional practices. Advised over 20 graduate students, including PhD and master’s candidates.

• Cyber-physical systems
• IoT
• System on Chip (SoC)
• +5 more

Sai Manoj Pudukotai Dinakarrao is an Assistant Professor in the Department of Electrical and Computer Engineering at George Mason University's College of Engineering and Computing. He leads the HArt (Hardware and AI Research) Group, focusing on cutting-edge research at the intersection of hardware security and artificial intelligence. His educational journey includes a BTech in Electronics and Communication Engineering from Jawaharlal Nehru Technological University (2010), an MTech in Information Technology from International Institute of Information Technology Bangalore (2012), and a PhD in Electrical Engineering from Nanyang Technological University, Singapore (2015). Following his doctoral studies, he completed post-doctoral research at TU Wien, Vienna (2015-2017) and George Mason University (2017-2018). Dr. Dinakarrao's research spans hardware security, adversarial machine learning, IoT networks, and deep learning in resource-constrained environments. His work integrates hardware design with AI techniques to address security challenges in computing systems, with particular focus on side-channel attack detection, malware detection in IoT networks, on-chip security, and hardware accelerator design for machine learning applications. His research has resulted in numerous publications in top-tier conferences and journals including IEEE Transactions, ACM conferences, and Design Automation Conference. Analysis of his recent publications reveals a strong trend toward hardware security solutions using machine learning techniques. His work increasingly focuses on Processing-in-Memory architectures, energy-efficient security solutions for IoT devices, and innovative approaches to hardware Trojan detection. Many publications demonstrate interdisciplinary collaboration across electrical engineering, computer science, and cybersecurity domains. Young Research Fellow Award at Design Automation Conference (DAC) 2013 Best paper award at International Conference on Data Mining (ICDM) 2019 Best paper award at International Conference on Consumer Electronics (ICCE) 2020 Best paper nomination at International Conference on Computer-Aided Design (ICCAD) 2019 Best paper nomination at Design Automation and Test in Europe (DATE) 2018 Dr. Dinakarrao has successfully mentored numerous PhD and MS students, with alumni securing positions at AMD-Xilinx, US Government agencies, and academic institutions. His research has been supported by significant grants from NSF, DARPA, and Virginia Commonwealth Cyber Initiative. Current projects include securing supply chains with UVA, developing novel architectures for machine learning acceleration, and creating energy-preserving cryptography protocols. The HArt Group maintains active collaborations with industry partners including AMD-Xilinx and government agencies. The lab focuses on practical implementations of theoretical security concepts, with particular emphasis on creating deployable security solutions for real-world hardware systems. Current research directions include intermittent computing with energy harvesting, hardware fuzzing techniques, and robust machine learning models resistant to adversarial attacks.

• Hardware security
• Adversarial machine learning
• Internet of Things networks
• +9 more

Xuan Zhang serves as Associate Professor in Electrical and Computer Engineering at Northeastern University, leading the Sensory AI Lab since joining in January 2024. Her research bridges computer architecture, integrated circuits, and artificial intelligence to develop miniaturized AI systems for autonomous physical platforms. She earned her PhD in Electrical and Computer Engineering from Cornell University in 2012. Her educational background forms the foundation for her interdisciplinary work spanning hardware and software co-design. Dr. Zhang's research focuses on artificial intelligence hardware, machine vision sensors, and security for autonomous systems. She pioneers techniques for efficient in-sensor computing, analog circuit optimization via machine learning, and hardware-level privacy preservation. Her work addresses critical challenges in energy efficiency, robustness, and security for edge AI deployment, particularly in resource-constrained environments like medical devices and autonomous vehicles. Analysis of her 2023-2025 publications reveals three dominant trends: (1) hardware-accelerated privacy mechanisms for sensors, (2) machine learning-driven analog circuit design automation, and (3) energy-efficient architectures for neural network inference. These works consistently target real-world applications in healthcare, autonomous systems, and semiconductor design. Her accolades include the prestigious NSF CAREER Award (2020) and leadership in a $10 million federal semiconductor initiative. She contributes to national efforts in AI-powered chip design through the National Center for the Advancement of Semiconductor Technology. Dr. Zhang advises graduate researchers in the Sensory AI Lab, securing significant funding for projects spanning hardware security, in-sensor computing, and autonomous system assurance. Her lab collaborates with federal agencies and industry partners on cutting-edge semiconductor research. The Sensory AI Lab operates at the hardware-software interface, developing novel architectures for intelligent edge devices. Current projects include optical privacy preservation, robust analog design tools, and energy modeling frameworks for in-sensor visual computing systems.

• Artificial Intelligence Hardware
• Machine Vision Sensors
• Electronic Design Automation
• +3 more

Satwik Patnaik is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Delaware. His research focuses on strengthening hardware security through CAD tools, leveraging machine learning, and exploring emerging technologies. He holds a Ph.D. in Electrical Engineering from New York University (2020) and was a postdoctoral researcher at Texas A&M University (2020–2021). Education: Ph.D., Electrical Engineering, Tandon School of Engineering, New York University (2020) Postdoctoral Research, Texas A&M University (2020–2021) Research Interests: VLSI design, hardware security (e.g., logic locking, side-channel attacks), computer-aided design (CAD), and applications of machine learning in securing global semiconductor supply chains. His work emphasizes 3D integration, emerging devices (e.g., ferroelectric tunnel junctions), and reinforcement learning for adversarial testing. Key Contributions: Developed tools like SecureX, VIGILANT, and Titan. Published over 48 peer-reviewed articles in top venues (e.g., ICCAD, IEEE Transactions). Co-organized global competitions like HeLLO-CTF 2021 and AI vs. Humans 2022. Served as security track chair for ACM CADAthlon (2022) and technical program committee member for ICCAD, ASP-DAC, etc. Awards: ACM/SIGDA Bronze Medal (2018) Best Paper Award at ARC 2017 Third Place at ARC 2021 Expertise: Integrates hardware design, security, and AI to address vulnerabilities in semiconductor supply chains. Active in standardizing secure CAD flows and educating the next generation of hardware security researchers.

• VLSI Design
• Hardware Security
• Computer-Aided Design (CAD)
• +3 more

Naghmeh Karimi is an Associate Professor in the Department of Computer Science and Electrical Engineering at the University of Maryland Baltimore County (UMBC), where she has held this position since 2023, after serving as an Assistant Professor from 2017 to 2023. She is a recipient of the NSF CAREER Award (2020) and the Best Paper Award (2019). Her research focuses on hardware security, trustworthiness, and reliability of integrated circuits, with a particular emphasis on cryptographic devices, PUF-based authentication, and aging-related vulnerabilities. She directs the SECure, REliable and Trusted Systems (SECRETS) Lab at UMBC, which explores topics including hardware security countermeasures, fault tolerance, and AI-driven security solutions. Prior to UMBC, she was affiliated with Rutgers University, New York University, Duke University, and Yale University. Her research interests span hardware security, design-for-trust, fault tolerance, AI for security, and VLSI design. Recent work emphasizes aging effects on cryptographic circuits, PUF resilience, and digital sensor-based failure detection. Her publications address challenges in side-channel attacks, fault injection, and secure IoT frameworks. Dr. Karimi’s work is supported by sponsors, and she actively mentors Ph.D. students in hardware security and reliability. Her lab offers openings for self-motivated researchers in these areas.

• Hardware Security
• Design-for-Trust
• Fault Tolerance
• +9 more

Dr. Dinesh Bhatia is a Professor in the Department of Electrical and Computer Engineering at the University of Texas at Dallas (UTD), affiliated with the Erik Jonsson School of Engineering and Computer Science. He currently serves as the Department Head (2024–Present). His academic journey includes roles such as Associate Professor at UTD (2000–2010) and Professor at the University of Cincinnati (1997–2000). He holds a Ph.D. in Computer Science from UTD (1990), an M.S. in Computer Science (1987), and a B.E. in Electrical Engineering (1985). His research focuses on reconfigurable computing, FPGA architecture, medical electronics, and AI-driven systems. Key areas include FPGA CAD tools, VLSI physical design, biomedical devices, and energy-efficient embedded systems. Notable achievements include the IEEE Circuits and Systems Society Distinguished Lecturer designation (2007) and the William H. Middendorf Award for Research Excellence (1995). Dr. Bhatia has advised students like Shankar Balachandaran and Karthik Gajjalapurna, contributing to award-winning theses. His work integrates machine learning with FPGA design, medical device innovation, and energy harvesting for sensor networks. He has published over 100 articles, emphasizing FPGA optimization, biomedical applications, and AI acceleration.

• Reconfigurable Computing
• FPGA Architecture
• Medical Electronics
• +5 more

Jia Wang is an Associate Professor in the Department of Electrical and Computer Engineering at Illinois Institute of Technology (IIT), affiliated with the Armour College of Engineering. He joined IIT in 2008 after completing his Ph.D. in EECS from Northwestern University. His research focuses on VLSI design automation, embedded systems, and algorithm design, with particular emphasis on power grid analysis, cloud computing security, and hardware-software co-design. Education: B.S., Electronic Engineering, Tsinghua University (2002) M.S., Electrical and Computer Engineering, Northwestern University (2005) Ph.D., Electrical Engineering and Computer Science, Northwestern University (2008) Research Interests: Dr. Wang’s work addresses challenges in VLSI design automation, including sequential optimization, floorplanning, and design for manufacturability. He explores synthesis techniques for embedded systems and distributed systems, and develops algorithms for secure cloud computing and energy-efficient systems. Key areas include power grid verification, secure outsourcing of computations, and scalable simulation methods. Courses Taught: ECE 429: Introduction to VLSI Design ECE 587: Hardware/Software Co-Design ECE 449: Object-Oriented Programming and Computer Simulation ECE 586: Fault Detection in Digital Circuits ECE 473: Cloud Computing and Cloud Native Systems Professional Contributions: He leads the ACG Floorplanner project , a widely referenced tool for floorplan optimization. His research has been published in top-tier journals and conferences such as IEEE Transactions on Computer-Aided Design, DAC, and ICCAD. He actively contributes to education through curricula development in VLSI, cybersecurity, and cloud computing.

• VLSI Design Automation
• Embedded Systems
• Algorithm Design
• +4 more

Carl Sechen is a Professor in the Electrical & Computer Engineering Department at the University of Texas at Dallas (UT Dallas), affiliated with the Erik Jonsson School of Engineering and Computer Science. His research focuses on design and computer-aided design (CAD) of digital/analog integrated circuits, with a strong emphasis on secure ICs and transistor-level programmable fabrics. He leads projects like the TRAP fabric, which achieves 10X logic density over traditional FPGAs while enabling secure hardware through IC redaction. Education: Ph.D. (1987, UC Berkeley), M.S. (1977, MIT), B.E.E. (1975, University of Minnesota). Awards include IEEE Fellow (2002), UTD Distinguished Teaching Award (2014), and multiple Semiconductor Research Corporation awards. His work bridges theoretical CAD advancements with practical hardware security solutions. Research Highlights: Secure IC design, transistor-level programmability, FPGA architecture, hardware security. Key Projects: TRAP fabric development, anti-reverse engineering techniques, low-power design methodologies. Awards: Over 20+ honors including best paper awards at PRIME (2017) and DATE (nominated 2017). Publications span journals like IEEE Transactions on CAD and conferences such as DATE, ISCAS, and VTS. Current work emphasizes secure hardware through obfuscation and programmable logic innovations.

• Digital Integrated Circuits
• Analog Integrated Circuits
• Computer-Aided Design (CAD)
• +5 more

Matthew R. Guthaus is a Professor in the Electrical and Computer Engineering Department at the University of California Santa Cruz's Baskin School of Engineering. With an active research career spanning over two decades, his work focuses on VLSI design, Electronic Design Automation, and memory systems. His research interests include VLSI Design, Computer-Aided Design, Electronic Design Automation, Memory Design, Clock Distribution, Resonant Clocking, and Machine Learning for EDA. Guthaus has made significant contributions to open-source EDA tools, most notably OpenRAM, which has become an important resource for memory compiler development in academia and industry. Analysis of his recent publications (2021-2025) reveals a strategic evolution in his research, incorporating machine learning techniques into traditional EDA problems while maintaining strong foundations in circuit design. His work spans from fundamental circuit design to high-level system considerations, with particular emphasis on open-source frameworks that enable broader collaboration in the semiconductor community. Guthaus has been actively involved in national initiatives addressing semiconductor research and workforce development, as evidenced by his contributions to NSF workshops on integrated circuits. His recent publications show continued innovation in memory design, clock distribution, and the application of AI to traditional EDA challenges. His research has practical applications in low-power circuit design, high-performance computing systems, and the growing field of neuromorphic computing. The consistent publication record through 2025 demonstrates ongoing active research and leadership in the EDA community.

• VLSI Design
• Computer-Aided Design
• Electronic Design Automation
• +4 more

Waseem Abbas serves as an Assistant Professor in the Department of Systems Engineering and Management at the Erik Jonsson School of Engineering and Computer Science, The University of Texas at Dallas. His academic focus centers on theoretical and applied networked systems research with critical infrastructure applications. His research program investigates network control systems and cyber-physical systems with emphasis on resilience and robustness against faults and strategic attacks. Key methodologies include graph theory (graph coloring, domination) and game theory applied to distributed control architectures. Primary application domains encompass robotic networks, sensor networks, transportation systems, and power grids where global behavior must emerge from local interactions. Specific contributions address robustness, controllability, optimal resource allocation, energy-efficient scheduling, intrusion detection, coverage problems, and resilient sensor placement. Analysis of his 2022-2024 publications reveals concentrated innovation in resilient consensus algorithms for Byzantine fault tolerance, structural controllability using zero forcing sets, and robust network design for critical infrastructure. His work increasingly integrates graph neural networks with control theory while maintaining strong theoretical foundations in graph-based security methods, demonstrating consistent advancement in networked system resilience.

• Network Control Systems
• Cyber-Physical Systems
• Multiagent Systems
• +5 more

Ramesh Karri is a Professor and Chair of the Electrical and Computer Engineering Department at New York University Tandon School of Engineering. He co-founded the NYU Center for Cyber Security (CCS) in 2009 and co-directed it from 2016-2024. He is also a Fellow of the IEEE and has led initiatives such as the Embedded Systems Challenge (ESC), a red-blue team cybersecurity competition. Education: Ph.D. in Computer Science and Engineering, University of California, San Diego (1993) B.E. in Electrical and Computer Engineering, Andhra University (1985) Research Focus: His work centers on hardware cybersecurity, including trustworthy integrated circuits, cyber-physical systems, nano-enabled security, and biochip security. He pioneered security-aware CAD tools and has developed metrics for hardware trojan detection through initiatives like the Trust-Hub. Awards & Leadership: Recipient of the Humboldt Fellowship and NSF CAREER Award Editor-in-Chief of ACM Journal of Emerging Computing Technologies Leadership roles at IEEE conferences (ICCD, HOST, DFTS) Grants & Labs: Directs the Center for Advanced Technology in Telecommunications (CATT) and NYU CCS. His labs focus on additive manufacturing security, digital microfluidic systems, and AI-driven hardware design.

• Hardware Cybersecurity
• Trustworthy Integrated Circuits
• Cyber-Physical Systems Security
• +6 more