Professor Noh Jae-chun serves in the Department of Computer Engineering at Sejong University, South Korea, leading research in systems engineering with a focus on modern computing infrastructure. His research program centers on four critical domains of computer systems: Cloud Computing and Virtualization techniques for resource optimization Distributed and Parallel File Systems architecture for scalable storage solutions Big Data Platform Construction methodologies for data-intensive applications SSD (Solid State Drive) technologies and performance optimization He directs the Systems Engineering Lab where active development occurs in these areas, maintaining regular laboratory interview hours on Tuesdays and Thursdays from 2:00 PM to 4:00 PM for student collaboration and research discussions.
Garth Gibson is a Professor in the Computer Science Department and Department of Electrical and Computer Engineering at Carnegie Mellon University's School of Computer Science. He serves as Co-Director of the Master of Computational Data Science program and as Associate Dean for Master's Programs. Gibson has been a faculty member at CMU since 1991, after receiving his Ph.D. and M.Sc. in Computer Science from the University of California at Berkeley and a Bachelor of Mathematics in Computer Science and Applied Mathematics from the University of Waterloo. Gibson's research focuses on large-scale parallelism in computer systems, secondary memory system technologies and optimization, scalable file and key-value storage systems, scalable machine learning, and systematic testing for large scale systems. His work bridges theoretical concepts with practical implementations, with a strong emphasis on shepherding technological advances from academic research to commercial reality. He has made significant contributions to RAID technology, network-attached secure disks (NASD), and parallel file systems that have shaped industry standards and products. Gibson's recent publications reveal a strong trend toward data-intensive scalable computing, with increasing focus on machine learning systems, distributed storage solutions, and high-performance computing infrastructure. His research has evolved from foundational storage technologies to address the challenges of petascale and exascale computing environments, with particular attention to the intersection of storage systems and machine learning workloads. The papers demonstrate a consistent theme of addressing system scalability challenges through innovative architectural approaches. Scientific Awards: 2014 Fellow of the IEEE for contributions to the performance and reliability of transformative storage systems 2012 Fellow of the ACM for contributions to the performance and reliability of storage systems 2012 Jean-Claude Laprie Award in Dependable Computing Industrial/Commercial Product Impact Category 2011 SIGOPS Hall of Fame for the SIGMOD88 RAID paper 1999 Reynold B. Johnson Information Storage Award 1999 Allan Newell Award for Research Excellence 1998 Test of Time Award 1991 A.C.M. Doctoral Dissertation Award (tied for second) Gibson has advised numerous graduate students who have gone on to influential positions in both academia and industry, including Swapnil Patil who won first place in the 2010 ACM Graduate Student Research Competition. He has secured significant research funding through initiatives like the DOE Petascale Data Storage Institute and the Intel Science and Technology Center for Cloud Computing. His research has been supported by collaborations with national laboratories including Los Alamos, Sandia, Oak Ridge, Pacific Northwest, and Lawrence Berkeley. Gibson founded CMU's Parallel Data Laboratory (PDL) in 1993, which has grown into a vibrant research community comprising 6-9 faculty members, 2-3 dozen students, and 4-10 staff. The PDL operates with guidance from the Parallel Data Consortium, which includes 15-25 companies interested in parallel data systems. He also founded Panasas Inc. in 1999, a scalable storage cluster company that has deployed technology in national laboratories, energy sectors, and other high-performance computing environments. More recently, Gibson established the Big Learning research group and created the Systems Major curriculum within CMU's Master of Computational Data Science program.
Tej Chajed is an Assistant Professor in the Department of Computer Sciences at the University of Wisconsin-Madison, focusing on formal verification of systems software. His research bridges theoretical foundations and practical implementations to ensure software correctness in concurrent and crash-safe systems. Research interests include formal verification, concurrency, crash safety, and programming languages, particularly using Coq, Perennial, and Goose frameworks. He has contributed to systems like DaisyNFS, a verified file system with sequential reasoning, and Verus, a foundation for systems verification. His work appears in top venues like SOSP, OSDI, and PLDI. 2025: Dafny PC Member 2024: PLDI Committee Member, CoqPL Co-chair 2023: CoqPL Co-chair, POPL Program Committee He actively mentors students and develops tools for systems verification education, including extensive Coq-based course materials.
Greg Ganger is the Jatras Professor of Electrical and Computer Engineering at Carnegie Mellon University and Director of the Parallel Data Lab (PDL). His research focuses on computer systems, including cloud computing, storage systems, distributed systems, and machine learning infrastructure. He holds a Ph.D. in Computer Science and Engineering from the University of Michigan and completed postdoctoral work at MIT. Education: Ph.D., M.S., and B.S. in Computer Science from the University of Michigan (1991–1995). Research Interests: Ganger leads projects in cloud computing, storage/file systems, operating systems, and systems for big data and large-scale machine learning. Recent work includes optimizing cloud resource scheduling, developing sustainable storage solutions, and improving ML cluster efficiency. The PDL explores storage system architecture, file systems, and leveraging new storage technologies like non-volatile memory (NVM). Awards: 2021 OSDI Best Paper, 2021 SOSP Best Paper, 2021 SoCC Test of Time Award, and 2021 R&D 100 Award. His team's work on Kangaroo caching and MACARON cloud caching exemplifies cutting-edge contributions. Advising & Grants: Advises graduate students in ECE and Computer Science. Active in grants related to distributed storage, cloud systems, and ML infrastructure. Collaborates with industry partners like Los Alamos National Lab on storage systems. Labs/Teams: Directs the Parallel Data Lab (PDL), a leading research group in storage and distributed systems. Collaborates with CMU’s CyLab on security aspects of storage systems and ML infrastructure.
Xiaojun Ruan is an Associate Professor in the Department of Computer Science at California State University, East Bay. He holds a Ph.D. in Computer Science from Auburn University (2011) and a B.E. in Computer Science and Technology from Shandong University (2005). His primary research focuses on energy-efficient systems, cloud computing optimization, storage systems, and security-aware resource management. He has extensive experience in thermal modeling, parallel I/O performance, and distributed deep learning frameworks. Dr. Ruan’s work emphasizes balancing energy efficiency, reliability, and performance in storage and cloud environments. Notable projects include DuoFS (hybrid storage system), energy-aware VM allocation strategies, and securing cloud infrastructure against co-residence attacks. His research bridges hardware-software co-design principles with practical system optimizations. His publications span topics from NVMe SSD performance optimization to text augmentation for spam detection, reflecting a blend of storage systems and machine learning applications. He has actively contributed to improving Shuffle I/O in big data processing, thermal management in clusters, and secure virtualization techniques. Dr. Ruan collaborates on interdisciplinary projects involving distributed computing, cybersecurity, and real-time systems. His lab focuses on deploying energy-efficient solutions while maintaining robust reliability, evidenced by over 50 peer-reviewed articles and ongoing contributions to academic conferences.
Dr. Wanja Hofer is a former research staff member at the Department of Computer Science 4 (Distributed Systems and Operating Systems) at Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU). She specialized in embedded systems, real-time operating systems, and aspect-oriented programming. Her research focused on optimizing hardware-centric systems like Sloth and CiAO, addressing challenges in interrupt handling, scheduling, and software product line variability. Her academic journey includes a PhD in 2014 titled Sloth: The Virtue and Vice of Latency Hiding in Hardware-Centric Operating Systems . She contributed to key projects such as Sloth (time-triggered RTOS) and CiAO (aspect-oriented OS family), emphasizing scalability and configurability for automotive and embedded domains. Hofer also held roles like Web chair for EuroSys 2009 and co-maintained the EuroSys Research Directory. Her teaching involved Basics of Systems Programming in C and OS-related seminars. She advised over 15 graduate students on topics ranging from MPU-based task isolation to filesystem-level variability management. Notable contributions include hardware-accelerated interrupt handling, aspect-oriented OS design, and embedded system energy optimization. Hofer currently works at Brose Fahrzeugteile, applying her expertise in embedded systems and real-time computing to automotive technologies. Her work bridges academic innovation with industrial applications, particularly in safety-critical and resource-constrained environments.
James Tuck is a Professor and Senior Associate Department Head for Undergraduate Affairs in the Department of Electrical and Computer Engineering at NC State University. He holds a BE from Vanderbilt University, and MS and PhD from the University of Illinois at Urbana-Champaign. His research focuses on computer architecture, compiler design, and DNA-based data storage, with notable contributions to chip multiprocessors and speculative execution. He has been recognized with two IEEE Micro Top Picks Paper Awards and the William F. Lane Outstanding Teaching Award. Education: Ph.D. in Computer Science, University of Illinois at Urbana-Champaign (2007) MS in Electrical and Computer Engineering, University of Illinois at Urbana-Champaign (2003) BE in Computer Engineering, Vanderbilt University (1999) Research Interests: Computer Architecture and Systems Compiler Design for Multiprocessors Hardware Support for Speculative Execution Advances in DNA Data Storage Non-Volatile Memory Systems Recent work emphasizes DNA storage scalability and security, including frameworks like FrameD and innovations in nanopore decoding. His articles span hardware optimization, persistent memory security, and biochemical storage solutions. Awards highlight both technical and pedagogical excellence. Advising and Grants: Leadership in Undergraduate Engineering Affairs NSF grants for DNA storage and memory systems Labs/Teams: Member of Undergraduate Affairs Team in NC State ECE Collaborations with Chemical and Biomolecular Engineering
Willy Zwaenepoel is a Professor and Dean of the Faculty of Engineering at the University of Sydney. He holds a B.S. from the University of Gent and M.S./Ph.D. from Stanford University. Previously, he served as Dean of the School of Computer and Communication Sciences at EPFL and was a faculty member at Rice University. His expertise spans operating systems, distributed systems, and high-performance computing. Education: B.S., University of Ghent, Belgium (1979) M.S., Stanford University (1980) Ph.D., Stanford University (1984) Research Interests: Dr. Zwaenepoel focuses on distributed systems, operating systems, and their applications in database replication, virtual machine performance, and software update mechanisms. His work includes foundational contributions to distributed shared memory (e.g., Treadmarks) and startups like iMimic Networking. Awards: ACM Fellow (2000) IEEE Fellow (1998) Fellow of the Australian Academy of Technical Sciences and Engineering (2020) Recipient of the IEEE Tsutomu Kanai Award (2007) Key Contributions: His research addresses challenges in distributed systems performance, such as latency reduction in key-value stores and efficient graph processing. Current projects explore I/O optimization in virtualized environments and causal consistency for geo-replicated systems. Students/Advising: Advises Ph.D. students and postdocs, including William in database replication. His mentorship led to the Rice University Teaching Award (2000).
Antonio Maria Gonzalez Colas is a Full Professor at the Universitat Politècnica de Catalunya (UPC), affiliated with the Department of Computer Architecture within the Faculty of Computer Science of Barcelona (FIB). He leads the ARCO research group focused on Microarchitecture and Compilers and is actively engaged in high-impact research in computer architecture, GPUs, and energy-efficient computing. His collaborations extend to the Barcelona Supercomputing Center and various national and European research initiatives. Research Interests: His primary research areas include computer architecture, microarchitecture, compilers, GPUs, and processor design. He focuses on energy-efficient computing, deep neural network (DNN) accelerators, GPU simulation and optimization, memory systems, and architectural support for machine learning and autonomous systems. His work often integrates compiler techniques with hardware design for performance and efficiency. Scientific Production Trends: His recent publications demonstrate a strong focus on energy-efficient hardware for AI workloads, particularly DNN and speech recognition acceleration, GPU architectural innovations, memory optimization, and real-time rendering. He frequently publishes in top-tier venues such as ISCA, MICRO, HPCA, and IEEE/ACM journals. ICREA Academia Award 2024 HiPEAC 2024 Paper Award ACM Senior Member (2020) Advising and Grants: He has advised numerous PhD students whose theses cover topics like energy-efficient architectures for autonomous driving, speech recognition, and neural networks. He leads competitive R&D projects, including an ERC Advanced Grant and projects funded by the Spanish National Program and the ICREA Academia program, focusing on domain-specific architectures and cognitive computing units. Labs and Teams: He is the principal investigator of the ARCO (Microarchitecture and Compilers) research group at UPC, a leading team in computer architecture research in Spain. The group is part of a larger collaborative network within UPC and with international partners.
Giorgio Scorzelli is a researcher at the University of Utah, serving as Director of Software Development for the Center for Extreme Data Management, Analysis, and Visualization (CEDMAV) and the National Science Data Fabric (NSDF) . He specializes in extreme data management, scientific visualization, and computational topology, with a focus on scalable solutions for climate science, materials science, and neuroscience datasets. His work emphasizes democratizing data access through platforms like OpenVisus , enabling efficient analysis of petascale and exascale data. Key contributions include orchestrating cyberinfrastructure, optimizing parallel I/O, and developing real-time visualization systems for heterogeneous resources. Notable scientific contributions include the NSF Grant #2127548 for NSDF development . His projects integrate cloud computing, geo-distributed storage, and FAIR digital objects to lower barriers to data democratization. Giorgio's research spans multi-resolution algorithms , computational topology , and 3D geometric modeling , with applications in infrastructure security, archaeological reconstruction, and biomedical imaging. His work bridges abstract mathematical frameworks (e.g., Boolean algebras, chain complexes) with practical software solutions.
Nicholas Wright serves as the NERSC Chief Architect and Advanced Technologies Group Lead at Lawrence Berkeley National Laboratory's National Energy Research Scientific Computing Center (NERSC) since 2009. He holds a PhD in Chemistry from the University of Durham, United Kingdom. Role: Focuses on evaluating emerging technologies for scientific computing Key Contributions: Chief architect for NERSC-10 procurement (2026), optimized Perlmutter machine architecture His research explores performance analysis of HPC applications and architectural evaluation for future technologies. Recent publications address: GPU frequency optimization using DNN-based models FPGA acceleration for HPC workloads Quantum computing cost scaling Disaggregated memory system evaluation Scientific workflow characterization Scientific awards include: Co-investigator on SDCI HPC Improvement grant (2007-2012) His work bridges computer architecture and energy-efficient computing through rigorous performance modeling and technology evaluation for NERSC's diverse scientific users.
Marco Aldinucci is a Full Professor and Head of the Parallel Computing group at the University of Torino's Computer Science Department. He leads the HPC Key Technologies and Tools (HPC-KTT) national lab under CINI, involving 38 Italian universities. His expertise spans parallel programming models, HPC systems, federated learning, and energy-efficient computing. Aldinucci has secured over €10M in EU research funding, contributed to frameworks like Fastflow and Streamflow, and pioneered initiatives like the HPC4AI lab and the CINI HPC-KTT lab. His research focuses on advancing exascale computing, cloud-HPC integration, and AI-driven medical solutions. Notable projects include the Gaia AVU-GSR solver for exascale systems and the DeepHealth Toolkit for medical AI. He has held governance roles in EuroHPC and chairs the Observatory on Trends and Applications of Supercomputing in Italy. Aldinucci’s publications (150+) address parallel algorithms, distributed learning, and sustainable HPC infrastructure. His work has been recognized with awards from HPC Advisory Council, NVIDIA, IBM, and Autodesk. Current initiatives include the Software & Integration lab at the Italian National HPC Centre (ICSC) and leadership in the OpenScience working group at Torino. His advising includes Iacopo Colonelli, whose thesis won CINI’s 2023 best award. He actively engages in EU projects, workflow systems, and standards for hybrid computing environments. Aldinucci’s labs and collaborations drive innovations in HPC portability, energy efficiency, and AI scalability.
Michael A. Bender is the John L. Hennessy Chaired Professor of Computer Science at Stony Brook University. His work spans both theoretical and applied domains in algorithms, data structures, and storage systems. He co-founded Tokutek, Inc., a database company acquired by Percona in 2015, and has held visiting positions at MIT and King's College London. Education: PhD in Computer Science from Harvard University (1998), DEA and Magistère in Computer Science from École Normale Supérieure de Lyon (1993), BA in Applied Mathematics from Harvard (1992). His research focuses on cache-oblivious algorithms , I/O-efficient computing , parallel systems , and scheduling . His work addresses scalability in large-scale data management and computational geometry, with applications in bioinformatics and robotics. The 15 most recent publications highlight advancements in list labeling , hash table design , graph algorithms , and memory optimization . These papers reflect his commitment to solving practical problems with rigorous algorithmic approaches. Awards include: PODS Best Paper Award (2024) ASPLOS Distinguished Paper Award (2023) USENIX FAST Best Paper Award (2016) Chancellor's Award for Excellence in Teaching (2015) R&D 100 Award (2006) He has led the Stony Brook Computer Science Honors Program and advised graduate students in algorithmic research. His grants portfolio includes 39 funded projects, emphasizing algorithm engineering and systems optimization.
Bruce Jacob is a Professor in the Cyber Science Department within the School of Engineering, Computing, and Weapons at the United States Naval Academy, where he joined in Fall 2022. Prior to USNA, he served as a professor of Electrical & Computer Engineering at the University of Maryland for 25 years, establishing himself as a leading expert in memory systems and computer architecture. Dr. Jacob received his A.B. in Mathematics from Harvard in 1988 and his Ph.D. in Computer Science & Engineering from The University of Michigan in 1997. Before graduate school, he worked in Boston start-ups as a software engineer at Boston Technology and later as chief engineer and system architect at Priority Call Management, which was successfully acquired in the late 1990s. His research focuses on memory systems, computer architecture, and memory devices, with significant contributions to memory system design across industry and government sectors. Jacob has designed computer-system architectures and memory-system architectures for major organizations including Micron (Hybrid Memory Cube DRAM architecture), Cray (Black Widow memory system), Northrop Grumman (experimental ultra-low-power datacenter), and the European Commission (1024-core Teraflux chip). His work spans resistive memory systems, non-volatile memory, memory simulation, and hardware security. His publication record demonstrates consistent leadership in memory systems research, with recent work focusing on ReRAM development, trusted execution environments for in-storage computing, and advanced memory simulation techniques. His research shows a clear trajectory toward monolithic memory integration, 3D stacking, and addressing the semantic gap between software and memory systems. Fellow of the IEEE Patent in memory-systems design Three patents in electric guitar circuit design Featured in Washington Post, Los Angeles Times, Chronicle of Higher Education, and NPR for guitar-related innovations Jacob has written two textbooks on computer memory systems and numerous articles spanning memory systems, computer design, embedded systems, operating system design, and even ventured into astrophysics and algorithmic composition. His DRAMsim memory simulator has become an industry standard tool. His practical industry experience complements his academic work, having consulted for major technology companies on memory system design challenges.
Sarah Neuwirth is a tenured Professor for Computer Science at Johannes Gutenberg University Mainz (JGU) and a Visiting Researcher at the Jülich Supercomputing Centre. She manages JGU's High Performance Computing (HPC) division, coordinates regional/national HPC activities, and represents JGU in NHR, Gauss-Allianz, and HPC committees. Education : PhD (Dr. rer. nat.) in Computer Science (2018), Heidelberg University Diplom in Computer Science (2012), University of Mannheim Bachelor of Science in Computer Science (2010), University of Mannheim Research Interests : Parallel File and Storage Systems Modular Supercomputing (resource disaggregation/virtualization) Performance Engineering High Performance Computing Networking Reproducible Benchmarking Parallel I/O Publications Trends : Her work focuses on HPC performance modeling, parallel I/O optimization, modular supercomputing, network characterization, and reproducible benchmarks. Key themes include resource disaggregation, automated workflows, and data-intensive distributed applications. Scientific Awards : 2023 PRACE Ada Lovelace Award for HPC ZONTA Science Award 2019 Grants & Leadership : She leads the High Performance Computing division at JGU, participated in European DEEP projects, and serves on SC conference committees.
