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Miquel Moreto Planas is a Senior Lecturer in the Department of Computer Architecture at the Barcelona School of Informatics, Universitat Politècnica de Catalunya (UPC). He is also affiliated with the Barcelona Supercomputing Center (BSC-CNS), a leading institution in high-performance computing. His academic profile is deeply rooted in computer architecture and high-performance computing, with a strong emphasis on practical and theoretical advancements in multicore systems, memory management, and hardware acceleration. His research interests span a wide range of topics including computer architecture, high-performance computing, multicore and manycore systems, cache and memory management, hardware acceleration for genomics and AI, RISC-V processor design, processing-in-memory, interconnection networks, and real-time systems. These interests are reflected in his extensive publication record and collaborative projects. The most recent articles highlight a significant trend toward interdisciplinary research, particularly the application of advanced computer architecture techniques to bioinformatics and healthcare. Key themes include the acceleration of genomic sequence alignment using novel hardware such as processing-in-memory, the development of benchmarks for ARM-based HPC systems in genomics, and the creation of AI-based 3D decision support tools for neurosurgical applications. His work also continues to advance core computer architecture topics like cache management, power-aware resource allocation in heterogeneous systems, and the design of secure, post-quantum cryptographic hardware based on RISC-V. Fulbright Award 2011 HiPEAC Paper Award HiPEAC Paper Award 2024 HiPEAC Paper Award Moreto has been a principal investigator or key contributor to multiple competitive R&D+i projects, such as the STRATUM project for neurosurgical tools, REDIOH for open hardware, and the Laboratorio Zettaescala de Barcelona. He has advised several doctoral students, including López, G., Kostalampros, I., and Haghi, A., and is a core member of the CAP (High Performance Computing) research group at UPC. His work is characterized by strong collaborations with leading researchers like Mateo Valero, Eduard Ayguadé, and Jesús Labarta, often bridging the gap between UPC and BSC-CNS. His laboratory and team affiliations are centered around the CAP group and the Barcelona Supercomputing Center, where he contributes to cutting-edge research in high-performance and embedded computer architectures. His recent work on the BIMSA accelerator and the STRATUM project demonstrates a clear future direction toward applying high-performance computing solutions to critical problems in genomics and medicine.

• Computer Architecture
• High-Performance Computing
• Multicore and Manycore Systems
• +7 more

Ricardo Fernández Pascual is an Associate Professor at the Computer Engineering Department (DITEC) of the Universidad de Murcia , Spain. He teaches introductory and advanced computer architecture courses like ' Estructura y Tecnología de Computadores ' and ' Organización y Arquitectura de Computadores '. His academic work focuses on computer architecture , particularly in memory hierarchies for chip multiprocessors cache coherence protocols fault tolerance energy-efficient design His PhD thesis (2009) at the Universidad de Murcia, titled ' Fault-tolerant Cache Coherence Protocols for CMPs ', was supervised by José Manuel García Carrasco and Manuel Eugenio Acacio Sánchez. He has also collaborated with institutions like Intel Barcelona Research Center and FORTH. Recent research trends in his publications include optimizing coherence directories for manycore scalability hybrid photonic-electronic interconnects fault-tolerant mechanisms in CMP architectures transactional memory enhancements dynamic resource management private-shared cache organization He has advised PhD student Antonio García Guirado, who completed his thesis on energy-efficient cache-coherent multi-cores in 2013. His work has been published in leading journals like IEEE Transactions on Parallel and Distributed Systems, Journal of Parallel Distributed Computing, and conferences including ICS, HPCA, and SBAC-PAD.

• Computer Architecture
• Memory Hierarchies
• Cache Coherence Protocols
• +5 more

Juan Luis Aragon Alcaraz is a Full Professor in Computer Architecture at the University of Murcia (Spain), affiliated with the Faculty of Informatics and the Department of Computer Engineering and Technology. He obtained his PhD in Computer Engineering from the University of Murcia in 2003 and held a postdoctoral position as a Visiting Assistant Professor and Researcher at the University of California, Irvine. He has held visiting researcher positions at EPFL (2013) and Princeton University (2015–2022). His research focuses on computer architecture, emphasizing heterogeneous parallel systems, GPUs, memory hierarchies, and energy-efficient microarchitecture design. He has advised 7 PhD theses and co-authored over 60 publications in top-tier conferences and journals. His work includes contributions to GPU-accelerated medical imaging, energy-efficient graphics pipelines, and hardware-software co-design for parallel systems. Key research trends in his articles include optimizing GPU performance for real-time applications, energy efficiency in graphics rendering, and scalable latency tolerance in manycore systems. His patents include innovations in presbyopia correction devices leveraging GPU and FPGA technologies. Dr. Aragón has taught numerous courses in computer architecture and design, including Computer Architecture and Organization, Advanced Aspects in Multicore Architectures, and Embedded Systems Technologies. His labs and collaborations span academic-industrial partnerships, emphasizing practical applications of his theoretical contributions.

• Computer Architecture
• Heterogeneous Parallel Systems
• GPU Computing
• +4 more

Prof. José Carlos Cabaleiro Domínguez is a Full Professor at the Department of Electronics and Computing, University of Santiago de Compostela. He holds a BS (1989) and PhD (1994) in Physics from the same university. His academic journey includes roles as an associate professor at the University of A Coruña (1990–1994) and associate professor at US圣地亚哥 de Compostela until 2022. He is affiliated with the Center for Research in Intelligent Technologies (CiTIUS) and leads the ARQCOMP research group in Computer Architecture. His research focuses on high-performance computing, parallel systems architecture, LiDAR data processing, and cloud computing. Notable contributions include optimizing parallel algorithms for sparse matrices, developing frameworks like BigOPERA for big data, and advancing LiDAR-based applications in infrastructure mapping and autonomous systems. He has led over 20 national/international projects, including HiPerHC2DA (2023–2026) and TLIX2 (2017–2018). Prof. Cabaleiro’s work spans 150+ peer-reviewed publications, with recent emphases on digital forensics (e.g., Android private browsing analysis), graph-based LiDAR segmentation, and energy-efficient thread migration strategies for NUMA systems. His research integrates hardware performance analysis, parallel algorithm design, and real-world applications in geomatics, bioinformatics, and cybersecurity.

• High Performance Computing
• Parallel Systems Architecture
• Parallel Algorithms
• +7 more