Ove Edfors is a Professor at the Department of Electrical and Information Technology, Lund University, affiliated with the Faculty of Engineering (LTH). His primary research focuses on radio systems, statistical signal processing, and massive MIMO technologies. He is a core member of the LTH Profile Area: AI and Digitalization and the LU Profile Area: Natural and Artificial Cognition. Edfors leads the NEXTG2COM Vinnova Competence Centre and contributes to ELLIIT initiatives. His research spans multi-carrier systems, low-complexity algorithms, and wireless communication applications. Key projects include 6G radio testbed development and millimeter-wave channel characterization. He has co-authored over 225 publications and supervised 22 graduate students. Notable achievements include the IEEE Signal Processing Society Donald G. Fink Award (2023) and the IEEE Communications Society Best Tutorial Paper Award (2018). Recent work emphasizes indoor localization via multi-sensor fusion (LuViRA Dataset) and energy-efficient MIMO processors. Active collaborations involve global institutions and industry partners in 5G/6G infrastructure. Edfors' contributions align with UN SDGs for affordable and clean energy (Goal 7) through energy-efficient wireless systems and innovation (Goal 9).
Rajit Manohar is the John C. Malone Professor of Electrical & Computer Engineering at Yale University, with appointments in Applied & Computational Mathematics and Computer Science. He is a core member of the interdisciplinary Computer Systems Lab (CSL), which bridges ECE and CS departments. His research focuses on asynchronous VLSI design, neuromorphic computing, and hardware-software co-design. Education: Manohar holds a B.S., M.S., and Ph.D. from the California Institute of Technology. His academic career spans over two decades, with notable contributions to asynchronous circuit theory and neuromorphic engineering. Research Interests: Manohar's work emphasizes energy-efficient asynchronous architectures, concurrency control, and biologically inspired computing. He explores topics like formal methods for circuit verification, cognitive systems, and dynamic sensor networks. His lab develops tools like Fluid (asynchronous synthesis) and Neurobench (neuromorphic benchmarking). Publications: Recent work includes advancements in asynchronous logic synthesis (Maelstrom), neuromorphic frameworks (Neurobench), and scalable brain-computer interfaces (SCALO). His research often intersects NSF-funded projects in energy-aware computing and neuromorphic systems. Awards: Inaugural Misha Mahowald Prize (2025), MIT TR35 (2000s), IBM Goldberg Award (2023) Grants & Labs: Manohar leads NSF-supported initiatives in carbon-aware networking and neuromorphic hardware. The Computer Systems Lab collaborates across disciplines to advance sustainable computing and neuro-inspired architectures.
Dr. José Manuel Claver Iborra is a Full Professor at the Department of Computer Science, School of Engineering (ETSE-UV), University of Valencia. He holds a PhD in Computer Science (Parallel and Distributed Computing program) from the Technical University of Valencia and an MSc in Physics (specialized in Electronics and Computer Science) from the University of Valencia. As an IEEE Senior Member, he focuses on cloud computing, video coding, parallel/distributed systems, reconfigurable computing, and network protocols for real-time applications. Current Research: Cloud-based video encoding, GPU acceleration for DNA analysis, FPGA-based network protocols, and indoor localization systems Academic Leadership: Coordinator of the UV-Tirant node in the Spanish Supercomputing Network (RES) His recent publications analyze GPU-based motion estimation, heterogeneous computing for video standards (H.264/AV1), and QoS scheduling algorithms. He supervises PhD and Master's theses on sensor networks, FPGA programming platforms, and parallel applications. Scientific Awards IEEE Senior Member He has directed funded projects on cloud infrastructure, distributed video processing, and reconfigurable systems since the 1990s.
Vyacheslav S. Kharchenko is a researcher affiliated with the National Aerospace University in Kharkiv, Ukraine, specializing in cybersecurity, artificial intelligence, and dependable computing. His work focuses on safety and security assessment of UAVs, IoT systems, and programmable systems, with a strong emphasis on Markov models, penetration testing, and hardware-based security solutions. Recent research includes cybersecurity frameworks for unmanned aircraft, blockchain quality models , and resilience engineering for AI systems. Collaborative efforts with colleagues like Oleg Illiashenko and Herman Fesenko address AI-powered cyberattacks, LiFi network reliability, and resource-constrained AI security. His publications span journals such as IEEE Access , Sensors , and Algorithms , covering topics like stochastic modeling for data evaluation, cache memory optimization , and UAV swarm reliability . Despite no explicit awards listed, his extensive contributions to safety-critical systems and Industry 4.0 cybersecurity underscore significant academic impact.
Rohan Basu Roy is an Assistant Professor (tenure-track) at the University of Utah, affiliated with the Kahlert School of Computing and the SCI Institute. His research focuses on optimizing parallel and distributed computing systems, including cloud, serverless, and HPC environments, with an emphasis on sustainability and cost-effectiveness. He holds a Ph.D. in Computer Engineering from Northeastern University, advised by Prof. Devesh Tiwari. Affiliations: University of Utah (Kahlert School of Computing), SCI Institute. His research interests include scheduling algorithms, energy efficiency, and environmental sustainability in computing systems. He has pioneered open-source tools like GreenMix and ECOLIFE , widely adopted in the systems research community. Awards: ACM-IEEE CS George Michael Memorial HPC Fellowship (2023), MLCommons ML and Systems Rising Star (2023), Northeastern University Excellence in Research Award (2023). Rohan has served as a program committee member for top-tier conferences (ASPLOS, HPCA, SC) and co-chaired tracks such as AI/ML for Systems at HiPC 2025. He has also delivered invited talks at Google Brain and ParslFest 2023.
Sumeet Syal is a Lecturer and Faculty & Academic Programs Lead at San José State University's College of Information, Data & Society. He also serves as Adjunct Faculty at Santa Clara University's Graduate School of Engineering and teaches at UC Santa Cruz. His academic roles focus on Management of Tech & AI Innovations, Leadership, and Marketing, drawing from his extensive executive background in Silicon Valley. UC Berkeley-Haas: Executive Coaching Certification (2021) Stanford Graduate School of Business: Leading Change & Org Renewal (2010) UCLA Anderson & National University of Singapore: Executive MBA (2007) Cal Poly, SLO: B.S. in Computer Engineering (1996) Sumeet’s research and teaching interests span a broad spectrum of technology and society, including Data Analytics, Health Informatics, Human-Computer Interaction, Information Policy, Technology Integration, and Strategic Marketing. His work emphasizes multicultural engagement, storytelling in tech, and leadership in innovation. As a tech executive, he brings practical insights into how information systems transform enterprise strategies. His recent publications, featured in TechCrunch, Engadget, and Business Insider, center on mobile chip technologies, LTE integration, and Intel’s strategic roadmap. These reflect his deep involvement in semiconductor innovation and mobile computing, highlighting trends in processor design, wireless communication, and Silicon Valley’s evolving tech ecosystem. Award-winning coaching & consulting company (3Doshas.com) featured on Bloomberg TV and Apple TV Sumeet has advised and mentored global teams at Intel, guiding leadership development and high-performance culture. Though no formal PhD students are listed, his role as an educator and coach involves significant advising of startup founders and executives. He has not received public research grants, but his industry leadership includes forging multi-billion-dollar partnerships with Google, Apple, Dell, and HP. He leads academic programming initiatives at SJSU and is building educational bridges between academia and Silicon Valley through experiential learning and industry-aligned curriculum development.
Nicolaj Haarhøj Malle is an Assistant Professor at the University of Southern Denmark’s Institute of Mechanical and Electrical Engineering and a member of the SDU Digital and High-Frequency Electronics group. He earned his PhD in Robotics in November 2023 with a dissertation on autonomous power-line perception and continues as a post-doctoral researcher until July 2025. Education PhD in Robotics, University of Southern Denmark (2020–2023) Post-doctoral Researcher in Aerial Robotics for Power-line Maintenance, University of Southern Denmark (2023–2025) Research Interests Malle’s work lies at the intersection of aerial robotics, power-line engineering, and embedded intelligence. He develops fully autonomous drones capable of landing on live overhead cables to recharge, inspect, and maintain critical infrastructure. His research integrates mm-wave radar sensing , computer vision , FPGA-accelerated perception , and machine learning to achieve robust navigation in GPS-denied, high-voltage environments. He also pioneers open-source hardware-software architectures for rapid prototyping of safety-critical drone swarms. Scientific Awards & Recognition Although no formal awards are listed, Malle’s work has received extensive national press coverage, including features in Information , DR Forskerfesten PhD Cup , and international tech media highlighting his “vampire drone” concept. Grants & Projects EU H2020 Drones4Safety (2020-2023) – PhD student participant EU H2020 Aerial Core (2019-2023) – PhD student participant InnoExplorer AIR-Ops (2023-2024) – Project participant Spin-outs Denmark OnGrid Aerial Systems (2024-2025) – Project participant Laboratories & Collaborations Malle collaborates closely with the SDU UAS Center and conducts experimental flights at dedicated drone test sites. He maintains an international network via visiting research stays (University of Zürich, Oct–Dec 2022) and active IEEE membership.
Adriano José Conceição Tavares is an Associate Professor at the School of Engineering, University of Minho, Portugal. He serves as a Senior Researcher at Centro ALGORITMI, where he is affiliated with both the IE R&D Group and the ESRG R&D Lab. His academic credentials include a PhD in Industrial Electronics from the University of Minho, a Master of Science in Information Technology from the University of Coimbra, and an undergraduate degree in Informatics from the University of Coimbra. Professor Tavares specializes in embedded systems with particular expertise in: Embedded systems modeling and design System software design System-on-chip design Real-time operating systems Hardware acceleration and FPGA design Virtualization for embedded systems IoT frameworks and protocols His publication record demonstrates a strong research trajectory in hardware-software co-design, with recent work showing an increasing integration of machine learning techniques into embedded systems. His publications span theoretical frameworks to practical implementations addressing real-time performance, resource constraints, and security challenges. Among his scholarly metrics: h-index of 18 126 publications with 1148 citations 20 publications in Q1/Q2 journals Author of a book on microcontroller programming Professor Tavares has supervised students including Miguel Ângelo Fernandes Silva and has established international collaborations through the Erasmus Program with institutions in China, Iran, Thailand, Jordan, and Cambodia. He teaches advanced courses on embedded and real-time systems modeling, compiler design, system-on-chip design, real-time operating system design, and advanced computer architectures at University of Minho.
Marc Geilen is an Associate Professor at the Electronic Systems group of Eindhoven University of Technology (TU/e) . He leads the Model-Based Design Lab within the CompSOC Lab and High Tech Systems Center .
Andrew Nelson is a part-time Assistant Professor at the Electronic Systems department, College of Engineering , Eindhoven University of Technology . He also serves as a founder and R&D lead at Verintec Solutions B.V. . Research Focus : Predictable and composable embedded systems, real-time robotics, multi-sensor fusion for industrial positioning, multi-core processor optimization. Key Contributions : Development of the CompSOC platform, CompROS architecture for ROS2, and novel multi-rate control strategies. Recent Article Trends : His work emphasizes predictable execution on multi-core platforms, sensor fusion techniques (linear encoders + vision systems), and real-time robotics. Articles span 2015–2025, highlighting collaborations with institutions like TU/e and ECSEL JU grant projects IMOCO4.E (2021–2023) and COMP4DRONES (2021).
Håkan Grahn is a Professor of Computer Engineering at the Department of Computer Science, School of Computing, Blekinge Institute of Technology (BTH) in Sweden. He has been a faculty member since 1996, becoming a full professor in 2007. His academic leadership includes serving as Head of Department (1999-2002) and Dean of Research (2011-2013) at BTH. He leads multiple significant research projects including GPAI (General Purpose AI Computing) and Green Clouds, with funding from ELLIIT, the Knowledge Foundation, and Vinnova. His educational background includes: M.Sc. in Computer Science and Engineering (1990) from Lund University Ph.D. in Computer Engineering (1995) from Lund University Håkan's research spans several interconnected domains in computer science and engineering, with a strong emphasis on practical applications. His work in computer architecture focuses on optimizing system performance through innovative cache coherence protocols and memory management techniques. In the realm of parallel computing , he investigates multicore systems, GPU computing, and thread-level speculation to enhance computational efficiency. His research in AI and machine learning addresses energy efficiency, data stream mining, and practical applications in areas like district heating systems and airborne networks. The integration of image processing with machine learning forms another significant strand of his work, particularly in historical document analysis and medical imaging applications. These research areas converge in his leadership of major initiatives like BigData@BTH and GPAI, where he bridges theoretical advances with real-world implementation challenges. Analysis of Håkan's recent publications reveals a clear trajectory toward increasingly applied research with strong industry connections. While maintaining foundational work in computer architecture, his output increasingly focuses on practical AI applications, energy efficiency in computing, and domain-specific implementations in sectors like telecommunications, energy systems, and defense. The interdisciplinary nature of his work is evident in collaborations spanning computer science, engineering, and domain-specific applications, with a growing emphasis on sustainability and resource optimization in computing systems. Håkan has successfully supervised numerous doctoral students, with ten graduates and six current Ph.D. candidates. His research has been supported by substantial funding from: The Knowledge Foundation (BigData@BTH, HINTS, Green Clouds) ELLIIT (GPAI project) Vinnova (FANET-MCA, Directed COM & EW) Industry partners including Ericsson, Saab, Telenor, and Fortnox He is actively involved in multiple research groups including DISL (Distributed and Intelligent Systems Lab), CCS-Lab (Communication and Computer Systems Research Lab), and previously PAARTS (Parallel Architectures and Applications for Real-Time Systems). His leadership extends to organizing academic events like the Nordic workshop on Multi-Core Computing and the Swedish Artificial Intelligence Society workshop.
Amirreza Yousefzadeh is an Assistant Professor specializing in computer architecture design for embedded systems. His research focuses on hardware acceleration for artificial intelligence, particularly in energy-efficient neuromorphic computing and edge AI applications. Research Interests Neuromorphic computing architectures Event-driven AI hardware Sparsity exploitation in neural networks Embedded vision systems Digital circuit design for AI Research Trends Recent work (2024-2025) demonstrates expertise in spiking neural networks (SNNs), activation sparsity, and hardware-software co-design for neuromorphic processors. Key areas include object detection, energy efficiency optimization, and digital implementations of synaptic delays. Technical Contributions Developed SENMap for multi-objective data-flow mapping Created SENSIM simulator for multi-core neuromorphic systems Investigated 3D stacking for memory-dominated architectures Explored temporal sparsity in event-based processing
Dr. Johannes Pfau serves as a Scientific Assistant at the Institute for Information Processing Technology (ITIV) within Karlsruhe Institute of Technology (KIT), working in Prof. Becker's research group. His position combines postdoctoral research in advanced FPGA architectures with teaching responsibilities including System-on-Chip internships and academic advising for specialized engineering tracks. Education: Doctorate (Dissertation) in Electrical Engineering and Information Technology, Karlsruhe Institute of Technology, 2024 Research Interests: Pfau's work centers on reconfigurable computing with three interconnected pillars: (1) Next-generation FPGA architectures using emerging technologies like RFETs that require fundamental toolchain redesigns; (2) Digital beamforming systems for satellite Earth observation that replace analog processing with FPGA-based solutions to enable on-orbit data compression; and (3) High-throughput data acquisition systems for 6G prototyping handling multi-100Gbps streams through RFSoC platforms. His research bridges semiconductor physics, hardware architecture, and practical applications in communications and remote sensing. Publication Trends: Pfau's 15 most recent publications (2021-2024) reveal a strong focus on practical FPGA implementations addressing real-world constraints. His work increasingly integrates power management (7 papers), 6G infrastructure (5 papers), and novel semiconductor technologies (4 papers), with a clear trajectory toward hardware solutions for satellite communications and next-generation wireless systems. The research demonstrates consistent progression from architectural innovations (RFET, V-FPGAs) to applied systems (beamforming, 6G testbeds). Advising and Mentorship: Pfau maintains an active student supervision portfolio with documented guidance of 7+ Bachelor's and Master's theses since 2021. His projects emphasize hands-on hardware development, spanning power management techniques, beamforming filter design, and prosthetic control systems. The academic advising role for specializations 13 and 21 positions him at the intersection of computer science and electrical engineering education. Research Context: As a core member of Prof. Becker's group at ITIV, Pfau contributes to KIT's leadership in reconfigurable systems research. The group maintains strong industry connections through 6G initiatives and satellite technology development, with Pfau's work directly supporting German and European efforts in secure communications infrastructure and Earth observation systems.
Kunle Olukotun is a Professor of Electrical Engineering and Computer Science at Stanford University's School of Engineering, where he has been faculty since 1991. He directs the Stanford Pervasive Parallelism Lab (PPL) and co-leads the Transactional Coherence and Consistency (TCC) project. His research focuses on computer architecture, parallel programming environments, and scalable parallel systems. Key areas include chip multiprocessors (CMPs), transactional memory systems, domain-specific languages (DSLs) for heterogeneous computing, and hardware-software co-design for machine learning workloads. His work bridges theoretical foundations with practical systems implementation. Notable contributions include the Stanford Hydra research project (one of the first chip multiprocessors with thread-level speculation), founding Afara Websystems (acquired by Sun Microsystems), and developing the Niagara processor architecture. His DSL frameworks like Green-Marl and Spatial enable efficient graph analysis and hardware acceleration. His publications reveal strong trends in parallel systems evolution: from foundational CMP research (2000s) to transactional memory (2004-2010), then DSLs for heterogeneous computing (2010-2015), and currently foundation model systems (2023-2025). Subfield analysis shows consistent focus on hardware-software co-design, sparse computation, and compiler techniques across decades. ACM Fellow (2006) for contributions to multiprocessors on a chip and multi-threaded processor design Best Paper Award at IEEE International Symposium on Workload Characteristics (IISWC '10) for EigenBench Olukotun actively mentors researchers through the Stanford Pervasive Parallelism Lab (PPL), which seeks to proliferate parallelism across application domains. His projects have secured significant industry partnerships, including the acquisition of his startup Afara Websystems by Sun Microsystems. Current research focuses on compiler frameworks for foundation model systems and hardware acceleration for sparse machine learning workloads, supported by collaborations with major tech companies. He leads the Stanford Pervasive Parallelism Lab (PPL), which develops compiler and runtime systems for heterogeneous architectures. The lab's work spans DSLs, hardware acceleration, and parallel programming models, with strong industry ties to companies like NVIDIA and Google. Current initiatives include the Mosaic compiler framework and Stardust architecture for sparse tensor computation.
Vincent Weaver is an Associate Professor in the Electrical and Computer Engineering Department at the University of Maine's College of Engineering. He leads the VMW Research Group, focusing on low-level systems research including hardware performance counters, computer architecture, and operating systems. Weaver received his BS in Electrical Engineering from the University of Maryland College Park in December 2000, followed by MS (January 2009) and PhD (May 2010) degrees in Electrical and Computer Engineering from Cornell University. He joined the University of Maine faculty in July 2012 as an Assistant Professor and earned tenure and promotion to Associate Professor in September 2018. His research centers on hardware performance analysis, architectural simulation, and systems programming with emphasis on Linux kernel development and embedded systems. Weaver's work bridges theoretical computer architecture with practical systems implementation, often resulting in open-source tools that advance the field. His publications reveal a consistent focus on performance analysis techniques, code optimization, and security through low-level system understanding. Weaver maintains an active teaching schedule including courses in embedded systems, operating systems, and network engineering. He values students with strong programming skills and encourages open source contributions as part of the learning process. His research group provides hands-on experience with cutting-edge processor architectures and performance analysis tools.
