Michael McAlpine is a Professor in the Mechanical Engineering department at the University of Minnesota . He also holds affiliations with the Biomedical Engineering and Electrical and Computer Engineering departments. His research focuses on 3D printing functional materials & devices , Nanoscale inks , Biomedical devices , Bioelectronics , and Flexible Microsystems . Research Interests : 3D Printing, Biomedical Engineering, Nanotechnology, Flexible Electronics, Microfluidics Labs : ME 361/363 Contact : mcalpine@umn.edu , (612) 626-3303, ME 117 Recent Research Trends include 3D Printed Biomedical Devices , Flexible Electronics , and Bioprinting Applications . His work spans from Spinal Organoid Formation to Programmable Drug Release Capsules . Scientific Award : Circulation Research 2020 Best Manuscript Award
José F. Martínez holds the Lee Teng-hui Professorship of Engineering at Cornell University's College of Engineering, where he leads research in computer architecture and systems. His roles include Vice Chair of ACM SIGARCH, IEEE Fellow, and past leadership roles in ISCA, MICRO, and IEEE Computer Society journals. He has received prestigious awards such as the NSF CAREER Award, IBM/Qualcomm Faculty Awards, and multiple teaching accolades including Tau Beta Pi Professor of the Year (2011). Education: Licenciado en Informática de Sistemas (1996), Universidad Politécnica de Valencia M.S. (1999) and Ph.D. (2002) in Computer Science, University of Illinois at Urbana-Champaign His research focuses on computer architecture , including microprocessors, multiprocessors, memory subsystems, embedded systems, and processing-in-memory (PIM) innovations. He co-leads the DARPA/SRC ACE Center for Evolvable Computing and NSF's CROPPS Center, and previously co-founded Cornell's Institute for Digital Agriculture (CIDA). His work bridges hardware-software co-design and sustainable computing. Key Contributions: Advancing energy-efficient multiprocessor architectures Developing PIM frameworks like PUMICE and Membrane Market-based resource allocation systems (e.g., XChange, ReBudget) His advising spans over 15 graduate students and has guided Merrill Presidential Scholars. Current research explores evolvable computing paradigms and AI hardware acceleration, reflecting his dual focus on foundational architecture and applied systems innovation.
Manoj Sachdev is a Professor in the Department of Electrical and Computer Engineering at the University of Waterloo, Faculty of Engineering. His research focuses on semiconductor devices, low-power electronics, and secure hardware systems. He leads projects in flexible electronics, nanotechnology, and radiation-hardened circuits, with applications in displays, memory technologies, and biomedical sensors. His work integrates advanced materials science with circuit design to address challenges in energy efficiency and security. Education: Not explicitly stated in provided text. Research interests span thin-film transistors (TFTs), resistive switching memories, neuromorphic computing, and physically unclonable functions (PUFs). Recent efforts include developing low-power circuits for flexible substrates and secure microprocessors. His contributions to semiconductor device physics and integration techniques have advanced applications in wearable electronics and medical diagnostics. Publications highlight innovations in low-power flip-flops, energy-efficient display drivers, and memristor-based systems. He collaborates on interdisciplinary projects combining photonics, nanoelectronics, and biomedical engineering. Awards: None explicitly listed in provided text. Grants and advising: Advises on semiconductor fabrication, secure hardware design, and radiation effects in electronics. Leads research groups focused on next-generation memory technologies and flexible integrated systems. Labs/Teams: Active in the University of Waterloo's semiconductor and flexible electronics research clusters, contributing to both academic and industry partnerships.
Robert Pilawa-Podgurski is a Professor in the Electrical Engineering and Computer Sciences Department at UC Berkeley and founding director of the Berkeley Power and Energy Center (BPEC). He earned BS, MEng, and PhD degrees from MIT. His research focuses on power electronics, including renewable energy systems, electric vehicles, and high-efficiency power converters. He has received prestigious awards such as the IEEE Fellow (2024), Bakar Fellows Spark Award (2024), and the IEEE Richard M. Bass Outstanding Young Power Electronics Engineer Award (2014). His work emphasizes experimental validation through hardware prototypes. Education: BS in Physics and EECS (MIT, 2005), MEng (MIT, 2007), PhD in EECS (MIT, 2012). Research interests include power electronics for renewable energy, electric vehicles, energy harvesting, and advanced converter topologies. His lab has developed high-power density converters and innovative control techniques for flying capacitor multilevel converters. Recent publications focus on hybrid switched-capacitor architectures, voltage balancing, and ultra-high-current applications. Awards include over 17 IEEE prize papers and teaching accolades like the 2023 UC Berkeley EECS Outstanding Teaching Award. His group has advised numerous students, including postdocs and PhD candidates working on cutting-edge power electronics projects. Labs/Teams: Pilawa Research Group at UC Berkeley, collaborating on power electronics for clean energy and high-performance computing.
Christof Paar is a Professor of Embedded Security at Ruhr University Bochum's Faculty of Computer Science. His work focuses on hardware security, cryptography, and embedded systems security. He leads the Embedded Security Group within the CASE Cluster of Excellence (Cyber Security in the Age of Large-Scale Attacks), addressing cutting-edge challenges in hardware Trojans, side-channel attacks, and cryptographic engineering. His research spans FPGA and IoT security, with contributions to physical-layer security, wireless jamming defenses, and tamper-resistant systems. Research Interests: Paar's expertise lies in hardware-software co-design for security, with a focus on embedded systems. His work includes analyzing vulnerabilities in FPGAs, developing countermeasures against side-channel attacks, and exploring physical-layer security mechanisms. He also investigates the human factors in hardware reverse engineering and the implications of adversarial machine learning on security systems. Notable Work: Recent publications highlight breakthroughs in detecting hardware Trojans across CMOS generations, breaking industry-standard IP protection mechanisms (IEEE 1735), and proposing novel defenses like IRShield against adversarial wireless sensing. His group actively contributes to standards for secure embedded systems and IoT devices, emphasizing practical implementations.
Prof. Baker Mohammad serves as Professor and Director of the System on Chip Lab in the Department of Computer and Information Engineering at Khalifa University. With over 15 years of industrial experience at Intel and Qualcomm designing microprocessors and DSP chips, he bridges academic research with real-world engineering challenges in high-performance computing and low-power systems. His educational background includes: Ph.D. in Electrical and Computer Engineering, University of Texas at Austin (2008) M.S. in Electrical and Computer Engineering, Arizona State University B.S. in Electrical Engineering, University of New Mexico Dr. Mohammad's research spans cutting-edge domains where VLSI design converges with AI acceleration and emerging memory technologies . His work pioneers Memristor applications in environmental sensing (radiation, vacuum, glucose) and neuromorphic computing, while advancing energy harvesting systems for wearable electronics. The integration of in-memory computing with security primitives represents a paradigm shift in hardware design, moving beyond traditional CMOS limitations. His publication trajectory reveals accelerating focus on self-powered neuromorphic systems and RRAM-based architectures, with recent work (2021-2023) emphasizing hardware-software co-design for edge AI. Over 75% of his recent publications involve cross-disciplinary collaborations spanning materials science, chemistry, and biomedical engineering. Notable scientific recognition includes: IEEE TVLSI Best Paper Award 2016 IEEE MWSCAS Myrill B. Reed Best Paper Award Qualcomm Qstar Award for Performance Leadership KUSTAR IP Excellence Award Multiple SRC Techon Best Session Papers As a dedicated mentor, he has supervised over 15 graduate students while securing competitive funding from Khalifa University, ADEK, Qualcomm, Tii, and UAE space agencies. His grant portfolio demonstrates exceptional translational impact, converting fundamental research in memristive devices into drone flight computers and medical sensors. Current projects integrate academic rigor with industrial deployment timelines. The System on Chip Lab operates as a multidisciplinary hub where semiconductor physicists collaborate with AI researchers to develop RISC-V-based secure processors and piezoelectric nanogenerator systems. Recent expansions include partnerships with Tii for aerospace applications and medical device startups for glucose monitoring technology.
Tosiron Adegbija is an Associate Professor in the Department of Electrical and Computer Engineering at the University of Arizona, where he serves as Director of Graduate Studies and Thomas R. Brown Endowed Fellow. He is a member of the Graduate Faculty and actively contributes to research and teaching in computer architecture and embedded systems. Education: PhD in Electrical and Computer Engineering, University of Florida, 2015 MS in Electrical and Computer Engineering, University of Florida, 2011 BS in Electrical Engineering, University of Ilorin, Nigeria, 2005 His research centers on energy-efficient computing with a focus on bio-inspired computer architecture , including spiking neural network (SNN) accelerators and in-memory computing. He also explores domain-specific architectures , adaptable memory systems , and microprocessor optimizations for IoT . His work leverages novel memory technologies like STT-RAM to enhance performance and reduce energy consumption in embedded and resource-constrained systems. Recent publications highlight trends in hybrid SNN acceleration, domain-specific accelerator generation, and system-level design space exploration. His research is increasingly focused on neuromorphic computing, automated hardware design, and ultra-efficient architectures using emerging materials like antiferromagnetic tunnel junctions. Scientific Awards: National Science Foundation (NSF) CAREER Award (2019) Elected IEEE Senior Member (2020) Best Paper Award at IEEE ISVLSI (2014) Teaching Award, University of Arizona (2018) ACM GLSVLSI Travel Award (2015) He advises numerous graduate and undergraduate students, many of whom have pursued careers at institutions like Pacific Northwest National Labs, Micron Technology, and Amazon. He has secured significant funding, including a $1.9M NSF FuSE2 grant for energy-efficient computing. His lab collaborates with UA Physics, CMU, and UNL. He has also developed educational tools for Chipyard and RISC-V, supporting hands-on learning in computer architecture. Labs and Research Teams: Leads a research group focused on bio-inspired and domain-specific computing, fostering innovation in energy-efficient hardware. The lab emphasizes hardware/software co-design, neuromorphic engineering, and real-world deployment in IoT and biomedical applications.
Jens S. Andersen is a Professor in the Department of Biochemistry and Molecular Biology at the University of Southern Denmark, where he leads research in Biomedical Mass Spectrometry and Systems Biology. His work is centered on the development and application of quantitative mass spectrometry and microscopy-based proteomics to study human cell biology, particularly the structure and function of organelles such as centrosomes, cilia, autophagosomes, and mitochondria. His research focuses on determining the protein composition and dynamic properties of cellular organelles, the roles of specific protein groups, and their contributions to biological processes and diseases. He investigates cell signaling mediated by post-translational modifications, especially within the DNA damage response, autophagy, and immune systems. His lab, the Jens S. Andersen Lab, is part of the Research Section of Biomedical Mass Spectrometry. The analysis of his recent publications reveals a strong interdisciplinary trend combining proteomics, structural biology, and cell signaling. His work spans cilia biology, RNA metabolism, DNA repair, and cancer mechanisms, with frequent use of advanced techniques like mass spectrometry, CRISPR, and live-cell imaging. The integration of systems biology approaches is evident across his research outputs. Professor, Department of Biochemistry and Molecular Biology, University of Southern Denmark Head of Research, Biomedical Mass Spectrometry and Systems Biology Principal Investigator, Jens S. Andersen Lab ORCID: 0000-0002-6091-140X While no specific scientific awards are mentioned in the provided texts, his extensive publication record in high-impact journals such as Science , Nature Communications , Molecular Cell , and EMBO Journal reflects significant scholarly contributions. He has supervised research projects and collaborated widely across Europe, though specific names of students are not listed. His research is supported by multiple ongoing projects, reflecting sustained funding and academic leadership. The Jens S. Andersen Lab operates at the intersection of proteomics and cell biology, contributing to fundamental understanding of organelle dynamics and disease mechanisms. The lab's work is highly collaborative, involving partnerships with groups in structural biology, RNA research, and cancer biology.
Jiang Hu is a Professor in the Department of Electrical and Computer Engineering at Texas A&M University, holding the Eric D. Rubin '06 Endowed Professorship. He also serves as Co-Director of Graduate Programs and is affiliated with the Computer Science & Engineering department. His research focuses on VLSI design automation, machine learning applications, and hardware security. He has held roles as editor for IEEE Transactions on CAD and ACM Transactions on Design Automation, and chaired the 2012 ACM International Symposium on Physical Design. Education: B.S. in Optical Engineering (Zhejiang University, 1990), M.S. in Physics (1997), and Ph.D. in Electrical Engineering (University of Minnesota, 2001). He worked at IBM Microelectronics before joining Texas A&M in 2002. Research interests include energy-efficient VLSI circuits, on-chip communication fabrics, analog layout automation, and AI-driven EDA. Recent work emphasizes machine learning for design closure, privacy-preserving frameworks, and systolic array-based architectures. Awards: IEEE Fellow (2016) Humboldt Research Fellowship (2012) Multiple best paper awards at DAC, ICCAD, and ASPDAC Advising and grants: Leads initiatives like the SLICE project, NSF workshops on ML-EDA infrastructure, and serves as Editor-in-Chief of ACM TODAES since 2024. His work bridges academic research and industry applications in EDA and semiconductor design. Labs/Teams: Active contributor to open-source tools like ALIGN for analog layout generation and collaborations on machine learning for EDA commons.
Tom Conte is an academic leader with a joint appointment in the School of Electrical & Computer Engineering and School of Computer Science at Georgia Institute of Technology. As the founding director of the Center for Research into Novel Computing Hierarchies (CRNCH), he specializes in computer architecture and compiler optimization. His work focuses on manycore architectures, energy-efficient microprocessor design, and embedded system architectures. Prior to Georgia Tech, he directed the Center for Embedded Systems Research at North Carolina State University. He holds IEEE Fellow status and served as 2015 President of the IEEE Computer Society, co-leading the IEEE Rebooting Computing Initiative since 2011. Dr. Conte earned his bachelor’s degree in Electrical Engineering from the University of Delaware (1986), followed by M.S. and Ph.D. degrees in Electrical Engineering from the University of Illinois at Urbana-Champaign (1988 and 1992). His research has been recognized with prestigious awards including the IEEE Computer Society’s Golden Core Member award and the National Science Foundation’s CAREER Award (1996). His research interests span quantum computing, 3D chip architectures, energy-efficient processing, and post-Moore computing innovations. He has pioneered initiatives like the Superstrider architecture and CREEPY energy-efficient processing frameworks. Recent work includes advancements in quantum programming languages (e.g., Qwerty) and hybrid quantum-classical systems. Awards: IEEE Fellow, Young Alumni Achievement Award, CAREER Award Leadership: IEEE Computer Society President (2015), CRNCH Director Key Projects: Rebooting Computing Initiative, Superstrider Architecture His lab’s contributions include novel compiler optimizations for manycore systems, smart NIC offloading techniques, and thermodynamically inspired computing models. Conte’s work bridges academic research with industry needs through interdisciplinary collaborations and standardization efforts.
Roger Chamberlain is a Professor in the Department of Computer Science & Engineering at Washington University in St. Louis , affiliated with the McKelvey School of Engineering . He has been on faculty since 1989, specializing in digital systems, parallel processing, computer architecture, embedded systems, and reconfigurable logic. Education: DSc, Washington University in St. Louis, 1989 MS, Washington University in St. Louis, 1985 BS, Washington University in St. Louis, 1983 Research Interests: His work focuses on architecturally diverse computing systems, including specialized architectures for astrophysics and biology. He explores high-performance parallel/distributed applications, energy-efficient computation, and high-capacity I/O systems. He collaborates with industry partners like Exegy, Inc., VelociData, Inc., and BECS Technology, contributing to commercialization of university-developed technologies for data analysis and microprocessor-based controls. Grants & Awards: In 2021, he was a co-investigator on a $5M gamma ray astronomy mission grant. In 2018, he led an NSF-funded project ($1.2M) to enhance streaming application efficiency on diverse architectures. His consulting and industry ties reflect a commitment to bridging academic research with practical applications. Professional Contributions: He co-founded Exegy, VelociData, and BECS Technology. His lab website and Google Scholar profile provide additional insights into his work.
Russell Tessier is a Professor and Department Head of Electrical and Computer Engineering at the University of Massachusetts Amherst, affiliated with the Manning College of Information and Computer Sciences. His research focuses on reconfigurable computing, FPGA architectures, and hardware security, with notable contributions in CAD algorithms for FPGAs, embedded systems, and multi-tenant FPGA vulnerability analysis. Education: B.S.C.S.E., Rensselaer Polytechnic Institute (1989) M.S. and Ph.D., Massachusetts Institute of Technology (1992 and 1999) Research Interests: Dr. Tessier's work spans FPGA security (e.g., side-channel attacks, power distribution vulnerabilities), reconfigurable cloud computing, and hardware acceleration for applications like SAR imaging and machine learning. His lab, the Reconfigurable Computing Group, develops open-source FPGA cores (e.g., FlexGrip GPGPU, DE4 NetFPGA) and explores cutting-edge security countermeasures. Awards and Honors: Chancellor's Leadership Fellow (2015-2016) NSF Information Technology Research Grant Lilly Teaching Fellow (2002-2003) Multiple College of Engineering Excellence Awards Grants and Projects: Active funding includes NSF SaTC grants on reconfigurable cloud security and NASA support for snowpack measurement systems. His research also addresses FPGA-based solutions for cybersecurity, such as intrusion detection and power-side channel mitigation. Labs and Teams: Leads the UMass Reconfigurable Computing Group, which collaborates on open-source FPGA tools, security frameworks, and embedded system designs. The group maintains platforms like the DE4 NetFPGA and FlexGrip architecture.
Kyprianos Papadimitriou is a Researcher at the Microprocessor and Hardware Laboratory within the School of Electrical and Computer Engineering at the Technical University of Crete . He holds a PhD in Electronic and Computer Engineering (2012) and has been involved in teaching laboratory courses such as Logic Design , Computer Architecture , and VLSI/ASIC Circuit Design . Research Areas : His work spans Reconfigurable Systems , Hardware Design , Computer Architecture , RFID Systems , and Real-Time Systems . He has developed innovative approaches in FPGA-based dynamic reconfiguration, MPSoC security, and 3D stereo vision for surveillance. Key Trends : Runtime reconfiguration for FPGAs Security frameworks for NoC-based MPSoCs Low-cost embedded vision systems Optimization of reconfiguration overhead Hardware task scheduling methodologies Genetic algorithm implementations on FPGAs Scientific Contributions : 1 USA patent (2005) Co-author of VLSI-SoC 2013 paper nominated for 1st Prize Active member of scientific committees (FPL, ReConFig) Peer reviewer for IEEE, Elsevier, and Springer journals Session chair at IEEE CNS and HPCC conferences Grants & Projects : Participated in competitive European and national programs, serving as scientific manager, coordinator, and technical coordinator. Developed spin-off company (2003-2005) to commercialize master's thesis research. Laboratory & Teaching : Affiliated with the Microprocessor and Hardware Laboratory , focusing on practical training in digital systems, processor-based systems, and VLSI design.
Yiorgos Makris is a Professor in the Department of Electrical and Computer Engineering at the Erik Jonsson School of Engineering & Computer Science, The University of Texas at Dallas, since July 2011. Previously, he was a faculty member at Yale University for over a decade. He holds a Ph.D. in Computer Engineering from the University of California, San Diego, and a Diploma in Computer Engineering from the University of Patras, Greece. Education: Ph.D. in Computer Engineering, University of California, San Diego (2001) M.S. in Computer Engineering, University of California, San Diego (1997) Diploma in Computer Engineering and Informatics, University of Patras, Greece (1995) Research Interests: Hardware Security and Trustworthiness Statistical Side-Channel Fingerprinting Machine Learning in Semiconductor Manufacturing Trusted and Reliable Integrated Circuits Hardware Trojans in Wireless Cryptographic ICs On-Die Learning and Emergent Technologies His work focuses on enhancing hardware security through statistical methods, machine learning, and formal verification, with applications in analog/RF ICs, post-production calibration, and secure IC design. Key Contributions: Co-Founder and Site-PI of NSF CHEST I/UCRC (Hardware and Embedded System Security and Trust) Leader of the Safety, Security, and Healthcare Thrust at TxACE (Texas Analog Center of Excellence) Director of the Trusted and RELiable Architectures (TRELA) Lab Grants and Funding: NSF, NIH, SRC, ARO, AFRL, AFWERX, DARPA, DOE, and industry partnerships with Boeing, Northrop Grumman, IBM, Intel, Qualcomm, etc. Recent grants include projects on DNA storage security, analog neural networks, and malicious hardware detection. Awards and Recognition: IEEE Fellow (2025) Best Paper Awards at DATE'13, VTS'15, DCAS'22 Best Hardware Demonstration Awards at HOST'16 and HOST'18 Erik Jonsson School Faculty Research Award (2020) Labs and Teams: TRELA Lab (Focus: Secure Hardware Design, Trusted Architectures) CHEST I/UCRC (Industry-University Collaboration)
Hossein Valavi is a Lecturer and Assistant Director of Undergraduate Studies at Princeton University, contributing to advancements in computer architecture and hardware acceleration. His research focuses on in-memory computing, neural networks, and energy-efficient systems, with notable work in reconfigurable architectures and mixed-signal processing. He has received multiple teaching awards, including recognition for innovative pandemic-era Car Lab courses and collaborative work honored by the Edison Patent Award. His academic contributions span academic positions since 2018, emphasizing both research and pedagogical excellence. Key technical areas include scalable in-memory computing systems, analog neural network accelerators, and low-power matrix factorization algorithms. His work addresses critical challenges in data movement reduction and hardware-software co-design for modern computing systems. Awards: Teaching Excellence Awards (2021, 2023), Edison Patent Award (2023) Grants & Projects: Leading developments in in-memory computing accelerators and embedded microprocessor designs Research teams under his guidance have produced impactful IP in semiconductor layouts, CNN accelerators, and programmable architectures, aiming to bridge theoretical computer science with practical hardware implementations.
