Find Academic Supervisors

Hossein ValaviView profile

Lecturer

• In-Memory Computing
• Neural Networks
• Hardware Acceleration
• +3 more

Hossein Valavi is a Lecturer and Assistant Director of Undergraduate Studies at Princeton University, contributing to advancements in computer architecture and hardware acceleration. His research focuses on in-memory computing, neural networks, and energy-efficient systems, with notable work in reconfigurable architectures and mixed-signal processing. He has received multiple teaching awards, including recognition for innovative pandemic-era Car Lab courses and collaborative work honored by the Edison Patent Award. His academic contributions span academic positions since 2018, emphasizing both research and pedagogical excellence. Key technical areas include scalable in-memory computing systems, analog neural network accelerators, and low-power matrix factorization algorithms. His work addresses critical challenges in data movement reduction and hardware-software co-design for modern computing systems. Awards: Teaching Excellence Awards (2021, 2023), Edison Patent Award (2023) Grants & Projects: Leading developments in in-memory computing accelerators and embedded microprocessor designs Research teams under his guidance have produced impactful IP in semiconductor layouts, CNN accelerators, and programmable architectures, aiming to bridge theoretical computer science with practical hardware implementations.

Rajendran JeyavijayanView profile

Associate Professor

• Hardware Security
• Computer Security
• Hardware Fuzzing
• +4 more

Jeyavijayan 'JV' Rajendran is an Associate Professor in the Department of Electrical and Computer Engineering at Texas A&M University, part of the College of Engineering. He is an ASCEND Fellow and leads the Secure and Trustworthy Hardware (SETH) Lab. His research focuses on hardware security, computer security, and novel applications of AI in secure hardware design. Education: PhD in Electrical Engineering (NYU 2015), MS in Computer Engineering (NYU Tandon 2010), BE in Electronics and Communication Engineering (Anna University 2008). Research Interests: Hardware Security, Computer Security, Logic Locking, Hardware IP Protection, and Reinforcement Learning for Security. He explores AI-driven approaches to detect vulnerabilities, protect intellectual property, and enhance secure hardware design through fuzzing, obfuscation, and formal verification. Notable Awards: 2022 Office of Naval Research Young Investigator Award, 2021 IEEE CEDA Ernest Kuh Early Career Award, 2017 NSF CAREER Award. Lab and Teams: The SETH Lab focuses on trustworthy hardware design, developing techniques to secure integrated circuits against reverse engineering and IP theft. Current projects include LLM-based hardware code generation, formal approaches for hardware fuzzing, and AI-driven vulnerability detection.

Yanan GuoView profile

Assistant Professor

• Computer Architecture
• Cybersecurity
• GPU Computing
• +4 more

Yanan Guo is an Assistant Professor in the Department of Computer Science at the University of Rochester, specializing in computer architecture and cybersecurity. Her research focuses on GPU memory safety, side-channel attacks, quantum computing, and machine learning security, with recent projects exploring cross-VM side-channel vulnerabilities and quantum circuit simulation. PhD, University of Pittsburgh (advisor: Dr. Jun Yang) Her work bridges hardware and software security, addressing issues like GPU cache eviction mechanisms, memory corruption attacks, and adversarial threats in neural networks. She actively collaborates with researchers like Youtao Zhang and Jun Yang, with publications in top venues including USENIX Security, MICRO, and ICML. Recent publications highlight trends in GPU security (memory safety, side-channel attacks), quantum computing optimizations, and adversarial machine learning. Her team’s projects have received recognition such as the NSF OAC grant for AI workflow security and features in IEEE Transactions on Computers. Featured Paper in IEEE Transactions on Computers (02/22 issue) Shortlisted for Top Picks in Hardware and Embedded Security 2023 Dr. Guo mentors PhD students and offers weekly office hours for undergraduates, emphasizing career paths, graduate applications, and research guidance. She serves on program committees for conferences like USENIX Security and ASPLOS.

Angshuman KarmakarView profile

Assistant Professor

• Post-Quantum Cryptography
• Computation On Encrypted Data
• Side-Channel Analysis
• +4 more

Angshuman Karmakar is an Assistant Professor in the Department of Computer Science and Engineering at the Indian Institute of Technology Kanpur, India. His research focuses primarily on Post-Quantum Cryptography (PQC) and Computation On Encrypted Data (COED), which are critical areas in modern cryptography and computer security. Dr. Karmakar received his Ph.D. from Katholieke Universiteit Leuven (KU Leuven), Belgium, where he worked under Prof. Ingrid Verbauwhede in the COSIC research group. He was awarded the prestigious Erasmus Mundus fellowship for his doctoral studies and the FWO (Fonds voor Wetenschappelijk Onderzoek – Vlaanderen) fellowship for his post-doctoral research at KU Leuven. His research spans theoretical development of cryptographic schemes, implementation algorithms, side-channel and fault attack analysis, and countermeasure development. Dr. Karmakar has established extensive international collaborations with researchers and engineers worldwide to address complex challenges in cryptography and security. Recent publications demonstrate a strong focus on practical post-quantum cryptographic implementations with particular attention to hardware and software efficiency, side-channel resistance, and novel attack methodologies. His work bridges theoretical cryptography with real-world implementation challenges across diverse platforms from IoT devices to high-performance computing systems. Erasmus Mundus fellowship for doctoral studies at KU Leuven FWO fellowship for post-doctoral study at KU Leuven Google India Research Award for work on practical transition to post-quantum cryptography Dr. Karmakar is actively seeking graduate students and postdoctoral researchers to collaborate on cutting-edge research in cryptography and computer security. His work has significant implications for securing future communication systems against quantum computing threats, with applications spanning blockchain technologies, IoT security, and general-purpose computing systems.

Timothy M. JonesView profile

Professor

• Computer Architecture
• Compilers
• Microarchitecture
• +5 more

Timothy M. Jones is a Professor of Computer Architecture and Compilation at the University of Cambridge's Computer Laboratory, serving as Director of the Computer Architecture and Semiconductor Design Centre (CASCADE) and Fellow/Director of Studies at Gonville and Caius College. His research focuses on parallelism extraction in applications to enhance performance and address energy efficiency/reliability challenges in compilers, binary translators, and microarchitectures. Current work includes novel cache prefetching techniques, thread-level parallelism schemes, and advanced core prediction methods. He has an Erdős number of 4 and a Dijkstra number of 4 via collaborative networks. Research interests span computer architecture fundamentals, compiler optimizations, hardware security mechanisms, and fault tolerance strategies. Notable contributions include speculative vectorization, heterogeneous parallel error detection (MEEK/FireGuard), and security tools like MarkUs and MineSweeper. CASCADE oversees interdisciplinary projects addressing future microprocessor/system challenges. Jones supervises PhD students through CASCADE's 2025 intake program. Publications emphasize architectural innovations in memory systems, security, and energy efficiency. Key works include MASCOT (memory dependence prediction), Scalar Vector Runahead (2024), and Decoupled Vector Runahead (2023). His work integrates hardware-software co-design principles to tackle real-world processor bottlenecks.

Andrew KwongView profile

Assistant Professor

• Computer Security
• Applied Cryptography
• Side-Channel Attacks
• +4 more

Andrew Kwong is an Assistant Professor at the University of North Carolina at Chapel Hill in the Department of Computer Science. His research focuses on computer security and applied cryptography, particularly side-channel attacks and defenses, including Rowhammer, Spectre, and cache timing vulnerabilities. He teaches courses such as Hardware Security and Side-Channels and Research Topics in Computer Security , covering topics like transient execution attacks, speculative probing, and cryptographic implementation flaws. Department of Computer Science, UNC Chapel Hill Assistant Professor Teaching COMP 790-184 (Hardware Security) and COMP 790-185 (Computer Security Research) His research involves cutting-edge work on hardware vulnerabilities, including Rowhammer-based key recovery in post-quantum cryptography, cache eviction side-channels, and speculative execution attacks. His publications appear at top venues like IEEE S&P, CCS, and USENIX Security. He received a Best Paper Award Honorable Mention at CCS 2022 for his work on FrodoKEM exploitation. Key trends in his publications include leveraging hardware flaws for data leakage, cryptographic protocol breakdowns, and combining transient execution with memory corruption attacks. His work has implications for hardware design security and cryptographic implementation practices. Best Paper Award Honorable Mention, CCS 2022 Contact: andrew@cs.unc.edu

• Superconducting Logic
• Bio-based Architectures
• Novel Computing Mediums
• +6 more

Dr. Jennifer Volk is an Assistant Professor at the College of Engineering, University of Wisconsin-Madison, specializing in Electrical & Computer Engineering. Her research focuses on leveraging novel technologies like superconductor electronics and photonics to create efficient systems for datacenters, neuromorphic computing, quantum computing, and space/sensing applications. She employs a holistic approach spanning circuit design, materials science, and computer microarchitecture. PhD (2024), University of California, Santa Barbara BS (2016), University of California, Santa Cruz Her research interests include superconducting logic , bio-based architectures , and novel computing mediums , emphasizing co-optimization of logic and circuit blocks. Her work develops design abstractions to simplify adoption of unconventional technologies. Dr. Volk's publications demonstrate expertise in superconducting circuit design, radiation-hardened CMOS for particle physics, and photonic materials. She has received numerous awards including the 2025 John D. Wiley Assistant Professorship and IEEE fellowships in applied superconductivity. 2025 John D. Wiley Assistant Professorship 2024 UC Santa Barbara President's Dissertation Year Fellowship 2023 IEEE CSC Graduate Study Fellowship in Applied Superconductivity 2022 IEEE Micro Top Picks Honorable Mention 2021 IEEE Micro Top Picks She teaches E C E 340 - Electronic Circuits I (Spring 2025). Her work bridges materials science, circuit design, and system architecture to enable next-generation computing platforms.

David CockView profile

Senior Lecturer

• Formal Verification
• Operating Systems
• Hardware-Software Co-Design
• +3 more

Dr. David Cock is a Senior Lecturer and Senior Researcher at ETH Zürich's Department of Computer Science, affiliated with the Systems Group. He holds a PhD from UNSW (2014) and a B.Sc. (hons) from UNSW (2004). His research focuses on formal verification, trustworthy systems, and hardware-software co-design, with notable contributions to projects like Enzian (a CPU/FPGA platform) and seL4 (formally verified kernel). He teaches Advanced Operating Systems and Informal Methods courses. Key achievements include the ACM Software System Award (2022) for seL4 and leadership in projects addressing hardware complexity and security. Research interests include formal methods for hardware modeling (Sockeye project), runtime verification, and mitigating timing channels. His work bridges theoretical foundations with practical systems, emphasizing secure and reliable computing platforms. Projects like Trustworthy BMC aim to enhance baseboard management systems' assurance. Collaborations span academia and industry, with open-source contributions to hardware designs and formal tools. Publications span formal verification, hardware modeling, and secure systems, with recent focus on heterogeneous computing and declarative hardware specifications. Teaching emphasizes practical formal techniques and OS design, leveraging real-world hardware (e.g., Barrelfish). His lab, the Systems Group, explores cutting-edge challenges in systems software and architecture.

Simon MooreView profile

Professor

• Computer Architecture
• Computer Security
• Hardware Security
• +3 more

Simon Moore is a Professor of Computer Engineering at the University of Cambridge's Department of Computer Science and Technology. He leads the Computer Architecture research group, focusing on secure processors and subsystems, particularly the CHERI project. His work emphasizes formal verification, hardware-software co-design, and scalable security solutions. He is a Fellow and Director of Studies at Trinity Hall, overseeing undergraduate admissions and mentoring in Computer Science. Research Interests: Moore's primary focus is the CHERI secure processor architecture, integrating RISC-V cores with formal verification. His work spans secure hardware design, memory safety, and embedded systems. Notable contributions include the CHERI-RISC-V microarchitecture, CheriABI, and formal verification frameworks. Key Projects: CHERI, CheriBSD, Morello (ARM collaboration) Recent Achievements: Test of Time Award (IEEE Security & Privacy 2025), finalist for Bhattacharyya Award (2022) Grants: Innovate UK Digital Security by Design, DARPA Mission Oriented Resilient Clouds Publications: Over 200 papers on secure architectures, including influential work on CHERI's capability model, formal verification, and hardware security. Recent focus areas include temporal memory safety, embedded system security, and GPU-based capability systems. Labs/Teams: Directs the Computer Architecture Group and collaborates with industry partners like ARM and Microsoft on CHERI implementations.

• Computer Architecture
• Accelerated Machine Learning
• Computer Science Education
• +3 more

Thomas Yeh is an Assistant Professor of Teaching in the Department of Computer Science at the University of California, Irvine. His academic background includes a Ph.D. in Computer Science from UCLA and a BS in Electrical Engineering and Computer Science from UC Berkeley. Prior to academia, he gained industry experience across research, architecture, design, verification, marketing, and management roles. His educational credentials: Ph.D. in Computer Science, UCLA BS in Electrical Engineering and Computer Science, UC Berkeley Dr. Yeh's research spans computer architecture, accelerated machine learning, and computer science education. In architecture, he pioneers error-tolerant physics simulation and heterogeneous computing. His ML work focuses on adaptive precision techniques for energy-efficient acceleration. In education, he develops interactive tools for novice programmers and experiential learning frameworks for computer architecture. His cross-disciplinary approach bridges hardware-software co-design with pedagogical innovation. Publication trends reveal consistent focus on computational efficiency across physics simulation, ML acceleration, and educational technology. His work connects real-time systems optimization with emerging AI applications, particularly in interactive environments and physics-based animation. No scientific awards are documented in the provided materials. While advising details and grant funding specifics are absent from available information, his industry-academia transition informs practical research directions. Teaching responsibilities include core courses like Introduction to CS, Data Structures, and Efficient ML Computing. Research infrastructure details remain unspecified, though his publications suggest collaborations in physics simulation and heterogeneous computing environments.

• Security Engineering
• Hardware Security
• Post-Quantum Cryptography
• +4 more

Prof. Tim Güneysu is a full Professor and Head of the Security Engineering department at the Faculty of Computer Science, Ruhr-Universität Bochum. He serves as Vice Dean for Strategy and Finances (since 2023) and previously as Speaker of the Horst-Görtz Institute for IT-Security (2020-2023). His academic journey includes roles as Associate Professor at the University of Bremen (2015-2017) and Assistant Professor at Ruhr-Universität Bochum (2011-2015). He also holds positions at the German Research Center for Artificial Intelligence (DFKI) and has conducted postdoctoral research at UMass Amherst. His research focuses on Security-by-Design principles, CAD for Security, and countermeasures against physical attacks. He emphasizes efficient cryptographic implementations and system-level hardware security. Key areas include post-quantum cryptography, side-channel resistant designs, and secure embedded systems. He has contributed over 200 publications in top venues, with recent work on FPGA-based cryptographic accelerators, secure hardware extensions (e.g., KeyVisor), and post-quantum algorithms for IoT. His research themes include agile signature acceleration, fault attack mitigation, and hardware-software co-design for security. Notable projects include CONVOLVE (edge-AI security) and QuantumRISC (quantum-safe systems). His work bridges theoretical cryptography with practical hardware implementations, emphasizing real-world security applications.

Eric RotenbergView profile

Professor

• Computer Architecture
• High-Performance Computing
• Low-Power Design
• +3 more

Dr. Eric Rotenberg is a Professor in the Department of Electrical and Computer Engineering at North Carolina State University. His research focuses on high-performance, low-power, and reliable processor architectures, with contributions to 3D stacked circuits, heterogeneous multi-core systems, and adaptive microarchitecture design. Education: Ph.D. in Computer Sciences, University of Wisconsin-Madison (1999) M.S. in Computer Sciences, University of Wisconsin-Madison (1996) B.S. in Electrical Engineering, University of Wisconsin-Madison (1991) Research Interests: Computer Architecture and Systems 3D-Stacked Integrated Circuits Heterogeneous Multi-Core Processors Microarchitecture Optimization Energy Efficiency in Processors Key Awards: IEEE Fellow (2015) NSF CAREER Award (2001) NC State Outstanding Teacher Award (2004) 2015 Micro Test-of-Time Award (co-authored) Professional Contributions: Developed the AnyCore adaptive processor framework and the H3 3D-stacked heterogeneous multi-core processor. Explored post-silicon microarchitecture adaptation and slipstream processors for improved performance and fault tolerance.

Maria MushtaqView profile

Associate Professor

• Embedded System Security
• Microarchitectural Security
• Artificial Intelligence Applications in Security
• +2 more

Maria Mushtaq is an Associate Professor at Telecom Paris , affiliated with the Information Processing and Communication Laboratory (LTCI) and the Secure and Safe Hardware (SSH) Lab . She received her PhD in Information Security from the University of South Brittany, France (2019) and completed 2 years of postdoctoral research at LIRMM, University of Montpellier under the CNRS excellence post-doc grant. Research Focus: Microarchitectural vulnerability assessment, runtime mitigation against side/covert-channel attacks, cryptanalysis, OS-based security primitives, and hardware-software interface security Technical Expertise: Cache timing attacks, transient execution attacks (Spectre/Meltdown), Hardware Performance Counter analysis, gem5 simulation Her recent work involves RISC-V security analysis using gem5 simulations and machine learning for attack detection. She serves as Guest Editor for the Journal of Applied Sciences special issue on Side Channel Attacks in Embedded Systems and has been on the Program Committee for the European Test Symposium (2020-2021). 2021 HiPEAC Collaboration Grant recipient Organized IP Paris Winter School on Microarchitectural Security (2022) Active in international conferences as panelist and keynote speaker

Joshua San MiguelView profile

Associate Professor

• Approximate computing
• Processor microarchitecture
• Intermittent computing
• +4 more

Associate Professor Joshua San Miguel leads research in computer architecture and systems at the University of Wisconsin-Madison, with an affiliate role in Computer Sciences. His work focuses on energy-efficient computing for IoT devices, microarchitecture innovations, and networks-on-chip. He holds a PhD (2017) and BASc (2012) from the University of Toronto. Education: PhD in Electrical & Computer Engineering, University of Toronto (2017) BASc in Engineering Science (ECE), University of Toronto (2012) Research Interests: Approximate computing for energy harvesting systems Branch prediction and value prediction in processors Cache architectures and networks-on-chip for many-core processors Intermittent computing resilience His recent work emphasizes value-level parallelism (Carat/uSystolic), RTL simulation acceleration (TaroRTL), and personalized neural network inference (CAP’NN). His research has been recognized with the NSF CAREER Award (2021) and multiple IEEE Micro Top Picks. Grants & Advising: Active in supervising advanced independent studies and master’s/dissertation research. Extensive grant funding includes the NSF CAREER Award and the Grainger Faculty Scholarship. Labs & Teams: Leads research groups focused on approximate computing and energy-efficient architectures within the Electrical & Computer Engineering department.

Gururaj SaileshwarView profile

Assistant Professor

• Microarchitectural Security
• System Security
• Memory Safety
• +5 more

Gururaj Saileshwar is an Assistant Professor in the Department of Computer Science at the University of Toronto, within the Mathematical and Computational Sciences school. His research focuses on securing computing hardware and systems, with a focus on microarchitectural security (cache side-channels, Rowhammer attacks), system security (memory safety), and security for machine learning systems. Education: PhD in Computer Science from Georgia Institute of Technology (2019), advised by Prof. Moinuddin Qureshi. B.Tech and M.Tech from Indian Institute of Technology Bombay (India). Prior to UofT, he was with NVIDIA Research. Research interests include developing new attacks, defenses, and tools for automated security analysis. His work has received multiple awards including the IEEE Top Pick in Hardware and Embedded Security, HPCA Best Paper Award, and IEEE HOST Best PhD Dissertation Award. He teaches courses on secure computer systems and hardware security, including CSC427 (Computer Security) and a topics course on secure computer systems. His lab focuses on hardware-software co-design solutions for security and reliability challenges in modern computing systems. Labs/Teams: Leads the Secure Hardware Systems Lab at UofT, collaborating on Rowhammer mitigation, cache attack defenses, and machine learning security. Grants: Active funding from NSF, industry partnerships with NVIDIA, and other hardware security initiatives. Advising: Currently recruiting PhD students interested in hardware security, system security, and machine learning systems security.