David I. August is a Professor of Computer Science at Princeton University, affiliated with the Department of Electrical Engineering. He earned his Ph.D. from the University of Illinois at Urbana-Champaign in 2000. His research focuses on compilers and computer architecture, emphasizing synergistic design between compilers and microarchitecture. He leads the Liberty Research Group, which explores topics such as automatic parallelization, memory profiling, and speculative execution. August joined Princeton in 1999 as a lecturer, advancing to full professor in 2012. He has served as program chair for MICRO 2009 and on committees for ISCA, PLDI, and ASPLOS. His notable accolades include the IEEE Fellow designation, Best Paper Awards at PLDI and CGO, and teaching awards from Princeton's School of Engineering. His work spans compiler optimizations, hardware-software co-design, and security architectures like TrustGuard. Recent research includes GPU scheduling (GhOST), memory profiling frameworks (PROMPT), and instruction prefetching (PDIP). He advises over 20 graduate students, many now leading roles at tech companies and academia. August teaches courses such as COS-126 (Intro to CS), COS-375 (Computer Architecture), and graduate seminars. His projects often bridge theory and practice, with tools like NOELLE and Liberty Research Group initiatives advancing compiler infrastructure and parallelism extraction.
Natalie Enright Jerger is a Professor in the Department of Electrical and Computer Engineering at the University of Toronto's Faculty of Applied Science and Engineering. She holds the Canada Research Chair in Computer Architecture and serves as Director of the Division of Engineering Science (2023-2028). Previously, she was the Percy Edward Hart Professor (2016-2019). She received her B.S. in Computer Engineering from Purdue University (2002), and M.S./Ph.D. in Electrical Engineering from University of Wisconsin-Madison (2004/2008). Her research focuses on: Multi/many-core architectures and on-chip networks Cache coherence protocols and memory hierarchy optimization Approximate computing and sustainable systems Intermittent computing for energy-harvesting devices Hardware acceleration for machine learning Her publications demonstrate strong emphasis on networks-on-chip (NoC) innovations, including routing algorithms, deadlock handling, power-efficient designs, and topology optimizations. Recent work expands into approximate computing, mobile architectures, and ML-driven hardware design. Major Awards: Fellow of Engineering Institute of Canada (2023) McLean Senior Fellow (2019) IEEE Micro Top Picks (2016) ACM/IEEE Microarchitecture Hall of Fame (2015) Sloan Research Fellowship (2015) Canada Research Chair (current) Distinguished Scientist, ACM Fellow, IEEE She leads the NEJ research group and collaborates with industry partners including Intel, AMD, Qualcomm, and IBM. Her work is funded by NSERC, CFI, and industrial grants. She co-chaired ASPLOS 2023 and HPCA 2014, and actively promotes diversity through WICARCH and ACM initiatives.
Aviral Shrivastava is a Professor at the School of Computing and Augmented Intelligence, Arizona State University, leading the Make Programming Simple Lab. He holds a Ph.D. and M.S. from the University of California-Irvine (2006, 2002) and a Bachelor’s from IIT Delhi (1999). His research focuses on making programming simple for embedded and cyber-physical systems, with a particular interest in manycore and accelerated computing, software for CPS, and resilient/fault-tolerant computing. He has co-authored over 120 publications in top venues like DAC, ESWEEK, and ACM TECS, with more than 3000 citations and 5 granted patents. His work has been recognized with multiple awards, including the 2010 NSF CAREER award and best paper nominations. Research Areas: Embedded and Cyber-Physical Systems Compiler Design for Modern Architectures Resilient and Fault-Tolerant Computing Scientific Awards: 2010 NSF CAREER award DAC 2017 Best Paper Award Candidate VLSI 2016 Best Student Paper Award LCTES 2010 Second Highest Ranked Paper ASPDAC 2008 Best Paper Candidate Advising & Grants: He has mentored 9 Ph.D. and over 20 Masters students. His research has been funded by NSF, DOE, NIST, SFAZ, and industry partners, totaling $3.5M. He teaches courses on computer organization, architecture, and embedded systems, with student evaluations averaging over 4/5. He also serves as General Chair of Embedded Systems Week (ESWEEK) and holds editorial roles in IEEE ESL, ACM TCPS, and ACM TECS.
Michael Ferdman is an Associate Professor in the Department of Computer Science at Stony Brook University, where he leads research in computer architecture and systems. His office is located in Room 343 at Stony Brook, NY 11794-2424, and he can be contacted via phone (631-632-8449) or email. Ferdman directs the Computer Architecture and Systems Laboratory (compas.cs.stonybrook.edu), focusing on next-generation server infrastructure. Ferdman's research spans the entire computing stack with emphasis on: FPGA integration for server environments (Intel HARP, Microsoft Catapult) Machine learning accelerators for convolutional neural networks Server systems optimization in the post-Moore era Network processing and software-defined networking Programming models for emerging memory technologies (HBM, 3D XPoint) Reconfigurable hardware and high-level synthesis His work addresses both performance and security challenges in modern computing infrastructure. Analysis of his 15 most recent publications (2022-2025) reveals consistent focus on: Hardware acceleration techniques (FPGAs, specialized processors) Memory hierarchy optimization and cache management Security vulnerabilities in web applications and systems Post-Moore computing architectures Parallel processing and distributed systems His research shows strong emphasis on practical implementations bridging hardware and software layers. Awards recognizing his contributions include: Graduate Teaching Award (2014) Best Paper Award at ASPLOS XVII Best Paper Finalist at HPCA XVII Three IEEE Micro Top Picks selections (2009, 2012) He teaches advanced courses including CSE 502, CSE 602, and CSE 506 at Stony Brook University.
Caroline Trippel is an Assistant Professor in the Departments of Computer Science and Electrical Engineering at Stanford University. Her research focuses on ensuring correctness and security in computer systems through formal methods, with particular emphasis on hardware verification, memory consistency models, and mitigating vulnerabilities like Spectre/Meltdown. She previously worked at Facebook’s FAIR SysML group before joining Stanford. Education: PhD in Computer Science, Princeton University BS in Computer Engineering, Purdue University Her work has influenced the RISC-V ISA memory consistency model and produced tools like CheckMate, which automatically synthesizes hardware exploits for security verification. She explores privacy-preserving ML, ML-driven hardware optimizations (e.g., neural recommendation), and datacenter reliability. Her research has earned awards including the 2020 ACM SIGARCH Dissertation Award and NVIDIA Fellowship. Key contributions include: Formal analysis of RISC-V memory models Exploitation synthesis frameworks (CheckMate) Hardware-software contracts for security Defenses against microarchitectural side-channel attacks Current projects include: VeriCoder: LLM-enhanced RTL code verification Multi-μPATH synthesis for security validation Near-data processing (RecSSD) for recommendation systems
Arrvindh Shriraman is an Associate Professor and Program Director of Software Systems at Simon Fraser University's School of Computing Science in Surrey. His research focuses on energy-efficient software, multicore memory systems, and optimizing hardware/software interfaces for parallel programming. He holds a Ph.D. (2010) and M.S. (2006) in Computer Science from the University of Rochester, and a B.Eng. (2004) from the University of Madras. He teaches courses on parallel programming and energy-conscious software design. His research interests include synchronization mechanisms for domain-specific architectures, cache optimization, and FPGA-based acceleration. He has contributed to frameworks like Mu-grind for HLS-generated RTL instrumentation and TAPAS for parallel accelerator generation. Notable projects include RANGE-BLOCKS for synchronization in domain-specific systems and TapeFlow for gradient computation in neural networks. His work emphasizes real-time verification of autonomous systems and safety-critical trajectory planning for underwater vehicles. Shriraman collaborates closely with the Tangent Lab, exploring cutting-edge solutions in hardware-software co-design and embedded systems. His teaching and research bridge theoretical computer science with applied engineering challenges, addressing scalability, efficiency, and safety in modern computing systems.
Gang (Gary) Tan is a Professor at the Pennsylvania State University's College of Engineering, specializing in computer security, formal methods, and programming languages. He co-directs the Institute for Networking and Security Research (INSR) and leads the Security of Software (SOS) Group, focusing on compiler, programming language, and formal method techniques to enhance computer security. Education: B.E. in Computer Science from Tsinghua University Ph.D. in Computer Science from Princeton University His research integrates formal verification with practical security applications, particularly emphasizing: Compiler-based security enforcement Side-channel mitigation in speculative execution Fairness analysis in machine learning systems Formal grammar approaches for software reliability Key article trends show: Security-focused formal methods (15% of publications) ML fairness verification (20% of recent work) Compiler-based security solutions (30% of output) Side-channel defense mechanisms (25% of research) Parser design and formal grammar synthesis (10% of contributions) Scientific achievements include: NSF CAREER Award Google Research Awards (2x) PLDI 2024 Best Paper James F. Will Career Development Professorship Outstanding Research Award at Penn State Ruth and Joel Spira Excellence in Teaching Award Dr. Tan actively contributes to academic communities through: DARPA ISAT study group membership Program committee roles (CGO 2024, ECOOP 2018, etc) Leadership in security research initiatives
Tom Conte is an academic leader with a joint appointment in the School of Electrical & Computer Engineering and School of Computer Science at Georgia Institute of Technology. As the founding director of the Center for Research into Novel Computing Hierarchies (CRNCH), he specializes in computer architecture and compiler optimization. His work focuses on manycore architectures, energy-efficient microprocessor design, and embedded system architectures. Prior to Georgia Tech, he directed the Center for Embedded Systems Research at North Carolina State University. He holds IEEE Fellow status and served as 2015 President of the IEEE Computer Society, co-leading the IEEE Rebooting Computing Initiative since 2011. Dr. Conte earned his bachelor’s degree in Electrical Engineering from the University of Delaware (1986), followed by M.S. and Ph.D. degrees in Electrical Engineering from the University of Illinois at Urbana-Champaign (1988 and 1992). His research has been recognized with prestigious awards including the IEEE Computer Society’s Golden Core Member award and the National Science Foundation’s CAREER Award (1996). His research interests span quantum computing, 3D chip architectures, energy-efficient processing, and post-Moore computing innovations. He has pioneered initiatives like the Superstrider architecture and CREEPY energy-efficient processing frameworks. Recent work includes advancements in quantum programming languages (e.g., Qwerty) and hybrid quantum-classical systems. Awards: IEEE Fellow, Young Alumni Achievement Award, CAREER Award Leadership: IEEE Computer Society President (2015), CRNCH Director Key Projects: Rebooting Computing Initiative, Superstrider Architecture His lab’s contributions include novel compiler optimizations for manycore systems, smart NIC offloading techniques, and thermodynamically inspired computing models. Conte’s work bridges academic research with industry needs through interdisciplinary collaborations and standardization efforts.
Alaa Alameldeen is an Associate Professor in the School of Computing Science at Simon Fraser University (SFU), part of the Faculty of Applied Sciences. Previously, he worked as a Research Scientist at Intel Labs (2006–2020) and held an Adjunct Faculty position at Portland State University (2008–2018). He earned a PhD in Computer Sciences from the University of Wisconsin-Madison (2006), and earlier degrees from Alexandria University, Egypt. His research focuses on computer architecture, including memory systems (processing-in-memory, cache/memory compression, security), energy-efficient architectures, and hardware-software co-design for machine learning. He advises PhD and MSc students in these areas and teaches advanced computing science courses. Key contributions include innovations in memory hierarchies, cache compression techniques, and mitigating hardware vulnerabilities. His work has been published in top conferences (e.g., ISCA, MICRO, HPCA) and patented in areas like near-memory processing and error correction. Alameldeen currently leads a research group exploring secure and high-performance memory architectures. He has supervised multiple graduate students, with many progressing to roles at leading tech companies and academic institutions.
David Wentzlaff is a Professor of Electrical and Computer Engineering at Princeton University, with associated faculty roles in Computer Science and the High Meadows Environmental Institute (HMEI). He leads research in computing architecture, green computing, and sustainable system design. As Director of Undergraduate Studies, he shapes educational programs in his field. Education: Ph.D., Electrical Engineering, MIT (2012) M.S., Electrical Engineering and Computer Science, MIT (2002) B.S., Electrical Engineering, University of Illinois at Urbana-Champaign (2000) Research Focus: Future Computing Systems: Designing manycore architectures, cloud computing infrastructure, and chiplet-based systems for exascale computing. Sustainability: Developing energy-efficient hardware, recyclable computing systems, and eco-friendly decommissioning strategies. Hardware-Software Co-Design: Exploring FPGA integration, in-memory computing, and parallel processing frameworks. Advising & Grants: Advises 8 current graduate students, focusing on topics like chiplet design, neural acceleration, and sustainable computing. Recipient of NSF grants for projects like OpenPiton (open-source manycore research platform) and CAREER awards for energy-efficient architectures. Labs & Collaborations: Leads the Wentzlaff Research Group at Princeton. Develops open-source frameworks like PRGA (FPGA prototyping) and OpenPiton (manycore processor).
Timothy M. Jones is a Professor of Computer Architecture and Compilation at the University of Cambridge Computer Laboratory, where he leads research in systems-level computing. He is also a Fellow at Gonville and Caius College, contributing to academic leadership and student mentorship within the collegiate system. His primary affiliation with the Computer Laboratory positions him at the forefront of systems research within the university. Dr. Jones's research focuses on extracting various forms of parallelism (thread-level, data-level, memory-level) to enhance computational performance while addressing energy efficiency and reliability challenges. His work spans compiler design, binary translation, and microarchitecture optimization, with specific interest areas including: Compiler technologies for functional and parallel programming Hardware reliability and fault tolerance mechanisms Binary analysis and instrumentation frameworks Memory system optimization and virtual memory management Security enhancements through binary modification Runtime systems for heterogeneous architectures Analysis of his recent publications reveals strong emphasis on systems-level innovation, particularly in fault tolerance techniques, binary analysis tools, memory optimization, and parallel execution frameworks. His work consistently bridges theoretical computer science with practical hardware implementation challenges. Dr. Jones maintains active participation in the academic community through conference leadership roles, including serving as Program Co-Chair for CGO 2026 and committee positions at premier venues including ISMM, CGO, and ECOOP. He contributes to open-source academic resources through GitHub and maintains professional engagement via Twitter.
Dr. Bin Zhu is a Research Fellow in the School of Mechanical Engineering Sciences at the University of Surrey, affiliated with the Centre for Engineering Materials. He obtained his PhD from the same institution, focusing on multiscale residual stress evaluation and mechanical property characterization using microscopy and large-scale facilities. His research develops techniques for harsh environments to enhance material longevity by managing manufacturing-induced residual stress, with applications in nuclear fusion components. Education PhD, University of Surrey (Research focus: Multiscale residual stress evaluation and mechanical property characterization) Research Focus Dr. Zhu's research centers on three interconnected areas: 1) Multiscale residual stress evaluation using advanced techniques like plasma-focused ion beam and neutron diffraction; 2) In situ mechanical testing under extreme conditions; and 3) Computational modeling for predicting stress distributions and material behavior. His work primarily addresses nuclear fusion reactor challenges, particularly laser-welded Eurofer97 steel components, where residual stress critically impacts structural integrity. Publication Trends Dr. Zhu's recent publications (2021-2025) demonstrate three key themes: 1) Advanced residual stress analysis in nuclear materials using machine learning, neutron imaging, and synchrotron techniques; 2) High-temperature mechanical performance of welded joints for fusion reactors; and 3) Biomimetic material characterization, including bioinspired composites and biological light-diffraction mechanisms. His methodologies consistently integrate multiscale experimental approaches with computational modeling.
Prof. Dr. Estela Suarez is a Professor of High Performance Computing at the Institute for Computer Science, University of Bonn (W2 in the Jülich Model) and Joint Lead of the Division "Novel System Architecture Design" at the Jülich Supercomputing Centre (JSC), Forschungszentrum Jülich GmbH. She also leads the Research Group "Next Generation Architectures and Prototypes" at JSC and serves as Spokesperson of Helmholtz Information Program 1, Topic 2. Currently on sabbatical during the 2024/2025 and 2025 academic years, she remains active in research leadership roles. 2010: PhD in Physics from University of Geneva, Switzerland 2004: Master in Physics, Specialization in Astrophysics, University Complutense of Madrid, Spain Professor Suarez specializes in high performance computing with particular expertise in heterogeneous HPC system architectures and modular supercomputing architecture (MSA). Her research spans hardware prototyping and evaluation, system software development, operational data analysis, and co-design methodologies. She has pioneered approaches to address hardware heterogeneity through system-wide orchestration of diverse computing resources, enabling more efficient scientific computing across multiple domains. Her work bridges theoretical computer architecture with practical implementation challenges in exascale computing environments, focusing on real-world applications that require specialized hardware configurations. Professor Suarez's publication record shows a clear evolution from foundational work on the DEEP project (2016) through the development of modular supercomputing concepts (2019-2021) to current applications across diverse scientific domains (2022-2024). Her recent publications demonstrate how modular architectures can be effectively applied to climate modeling, neuroscience simulations, quantum chemistry calculations, and other computationally intensive fields. This trend highlights her focus on practical implementation challenges and the growing importance of adaptable computing architectures in modern scientific research. 2023/2024 Lehrpreis der Universität Bonn: UniBonn teaching award Professor Suarez has secured significant research funding through major projects including NUMERIQS (Projects A05, B02, and Z02), European Processor Initiative (EPI), DEEP-SEA (Software for Exascale Architectures), IFCES2 (optimization of simulation algorithms for exascale supercomputers), and AIDAS (virtual laboratory between Forschungszentrum Jülich and CEA on AI and data analytics). While currently not accepting new students due to sabbatical, she has previously mentored graduate students in high performance computing techniques and has delivered numerous invited lectures at international conferences. Professor Suarez leads the "Next Generation Architectures and Prototypes" research group at JSC and serves as Joint Lead of the "Novel System Architecture Design" division. She chairs the Research and Innovation Advisory Group (RIAG) from EuroHPC Joint Undertaking since 2024. Her work involves close collaboration with international research teams on advancing supercomputing architectures, including contributions to the University of Bonn's new HPC system "Marvin" which ranks on both the TOP500 and GREEN500 lists.
Chester Rebeiro is an Associate Professor at the Department of Computer Science and Engineering within the Indian Institute of Technology Madras . His work spans hardware and software security with a focus on cryptographic implementations and microarchitectural vulnerabilities. Research interests include hardware security, applied cryptography, side channel analysis, and operating system security. He develops frameworks for automatic vulnerability detection and mitigation in cryptographic systems. Editorial Board: Associate Editor at Journal of Hardware and Systems Security (Springer, 2021-2024) Conference Leadership: General Co-Chair for SPACE 2024, Program Co-Chair for ATS 2024, and Program Co-Chair for INDOCRYPT 2023 Professional Activities: Organizer of e-CTF Embedded Capture The Flag and contributor to cybersecurity workshops across India and abroad Scientific contributions highlight two major awards: a Distinguished Paper Award at USENIX Security 2024 and a Best Paper Award at IEEE HOST 2020. His research focuses on practical security solutions for processors and cryptographic systems. Advising includes mentoring 11 PhD students and 7 MS by Research candidates, with notable co-guided projects in fault attack detection and side-channel mitigation. He actively contributes to educational initiatives through courses on Secure Processor Microarchitecture and Operating Systems.
Trevor E. Carlson is an Assistant Professor at the School of Computing, National University of Singapore (NUS), focusing on high-efficiency microarchitectures, hardware/software co-design, and secure chip design for IoT and server applications. He earned his Ph.D. in Computer Science from Ghent University (2014) and B.Sc./M.Sc. in Electrical & Computer Engineering from Carnegie Mellon University (2002/2003). Research Interests include energy-efficient processors, secure computing platforms, neuromorphic accelerators, and fast simulation methodologies. He co-developed the Sniper Multi-Core Simulator used globally for performance/power evaluation. Scientific Awards : Best Paper Award, International Conference on Embedded Computer Systems (2016) Best Paper Award, International Symposium on Performance Analysis of Systems and Software (2013) Heidelberg Laureate Forum participation (2015) HiPEAC Technology Transfer Award for Sniper Simulator (2013) Current Research involves secure Systems-on-Chip (SOCure project), hardware security for IoT, and simulation methodologies. He leads a lab with researchers working on topics like Capstone for trustless secure memory access and LABS for laser fault injection benchmarks.
