Find Academic Supervisors

• Emerging memory and storage technologies
• Embedded systems
• Cyber-Physical Systems (CPS)
• +5 more

Dr. Yiran Chen is the John Cocke Distinguished Professor at Duke University's Department of Electrical and Computer Engineering, leading the NSF AI Institute for Edge Computing (Athena) and the Duke Center for Computational Evolutionary Intelligence (DCEI). A global leader in neuromorphic computing, emerging memory systems, and edge AI, he holds prestigious roles including IEEE Fellow and Editor-in-Chief of IEEE Transactions on Circuits and Systems for AI. His research spans machine learning accelerators, security-hardened hardware, and co-design of EDA tools with LLMs. With over 700 publications and 96 patents, he has been awarded 15 paper awards and 17 nominations, including rare Technical Achievement Awards from IEEE societies. He advises over 60 PhD students and 4 postdocs, many of whom hold academic positions worldwide. His work bridges academia and industry, contributing to startups and venture capital through his board roles. Education: B.S. (Tsinghua, 1998) → M.S. (Tsinghua, 2001) → Ph.D. (Purdue, 2005). Career path: Assistant/Associate Professor at University of Pittsburgh (2010–2014) → Duke since 2014. Awards include the ACM SIGDA Outstanding New Faculty Award (2014), NSF CAREER Award (2013), and the Stansell Family Distinguished Research Award (2022). Research focuses on innovations in: (1) Non-volatile memory architectures for AI acceleration, (2) Hardware-software co-design for edge computing, (3) Security in neuromorphic systems, and (4) Large-scale ML for EDA. His group pioneered ReRAM-based accelerators like ReBNN and MARC, and introduced novel edge AI frameworks like Ecco and Prosperity. These works address scalability, energy efficiency, and real-time performance challenges. Key initiatives include the NSF IUCRC for Alternative Sustainable & Intelligent Computing (ASIC), advancing sustainable computing through novel materials and architectures. His leadership in standard-setting bodies like the IEEE Circuits and Systems Society ensures cutting-edge research translates into industry practices. Grants: Lead PIs for multiple NSF AI Institutes and industry partnerships. Labs: Directs the Athena Institute and DCEI, fostering collaboration between academia and industry. Current projects include quantum computing placement algorithms (QPlacer), federated learning frameworks (FedGPT), and neuro-symbolic architectures.

• Control Technology
• Distributed Optimization
• Machine Learning
• +4 more

Mikael Johansson is a Professor at Kungliga Tekniska Högskolan (KTH), specializing in Control Technology . He teaches and coordinates courses such as Distributed Optimization (FEL3311) and various advanced-level degree projects in computer science, electrical engineering, and systems engineering. His research spans Control Systems , Machine Learning , and Optimization , with a focus on asynchronous algorithms, federated learning, and applications in energy systems and construction. His work includes 15 recent publications on topics like neural networks, distributed optimization, and battery technology. Notable areas of contribution are in asynchronous learning, federated learning with privacy constraints, and quasi-Newton methods for optimization. His research bridges theoretical advancements with practical applications in urban design, healthcare, and autonomous systems.

• Memory Systems Design
• High-Performance Computing
• Exascale Systems Architecture
• +7 more

Bruce Jacob is a Keystone Professor and Full Professor in the Department of Electrical & Computer Engineering at the University of Maryland College Park's College of Engineering. His research primarily focuses on memory systems design and exascale computing architectures, with significant contributions to DRAM simulation and high-performance computing systems. Dr. Jacob received his A.B. in Mathematics from Harvard University (1988), followed by his M.S. and Ph.D. in Computer Science & Engineering from the University of Michigan (1995 and 1997 respectively). His research interests include memory systems design, exascale computing architectures, embedded systems, circuit integrity, and algorithmic composition. His recent publications demonstrate a strong focus on next-generation memory technologies, particularly ReRAM and advanced DRAM architectures. His work bridges the gap between theoretical modeling and practical implementation, with significant contributions to memory system simulation through projects like DRAMsim. His research shows a consistent trajectory toward solving the memory bottleneck problem in high-performance computing systems. Named Fellow, IEEE (2021) Multiple University of Maryland Research Leader awards (2006, 2010, 2012, 2016, 2017) Clark School of Engineering Keystone Professor (2006) National Science Foundation CAREER Award (2000) University of Maryland Award for Teaching Excellence (2004) Dr. Jacob has led significant research initiatives including the University of Maryland Exascale Systems Research and Memory-Systems Research groups. He has developed important computational artifacts such as DRAMsim (a public-domain DRAM-system simulator) and BioBench (a set of bioinformatics workloads). His work has influenced both academic research and industry practices in memory system design.

Christian PlesslView profile

Professor

• High-Performance Computing
• Reconfigurable Computing
• FPGA Acceleration
• +3 more

Prof. Dr. Christian Plessl is a W3 Professor of High-Performance Computing at the Institute of Computer Science, University of Paderborn. He leads the Paderborn Center for Parallel Computing (PC²), a national HPC center within the NHR alliance. His roles include Director of PC², Board Member of the NHR association, and member of the Sonderforschungsbereich 901. Education: PhD (Dr. sc. ETH) in Computer Engineering, ETH Zürich (2006) MSc in Electrical Engineering, ETH Zürich (2001) Postdoc at ETH Zürich (2007–2011) Research Interests: Architecture and tools for high-performance parallel and reconfigurable computing, FPGA acceleration, quantum chemistry, scientific computing, adaptive systems, and energy-efficient HPC solutions. Key projects include EKI-App (FPGA-based neural networks), FPGA4XPCS (X-ray spectroscopy), and HighPerMeshes (unstructured grid frameworks). Publications: Over 100 peer-reviewed works, focusing on FPGA acceleration, HPC frameworks, and quantum computing. Recent trends emphasize energy-efficient neural networks, FPGA-based quantum computing, and scalable HPC algorithms. Awards: Best Paper Awards at HEART 2023, ReConFig 2012/2014 Paderborn University Research Awards (2018, 2009) SEW-EURODRIVE Student Award (2001) Grants & Projects: Principal investigator in DFG, BMBF, and EU-funded projects. Collaborates with AMD/Xilinx, Intel/Altera, and Fujitsu. Leads initiatives like PerficienCC (custom computing) and HighPerMeshes. Labs/Teams: Directs the High-Performance Computing group at PC², focusing on FPGA supercomputing and HPC infrastructure. Active in the NHR alliance for national HPC coordination.

Luo MaiView profile

Assistant Professor

• Computer Systems
• Machine Learning Systems
• Data Management
• +3 more

Luo Mai is an Assistant Professor at the University of Edinburgh's School of Informatics , with an upcoming promotion to Associate Professor (UK Reader) in August 2025. He leads the Large-Scale Machine Learning Systems Group and co-leads the UK EPSRC Centre for Doctoral Training in Machine Learning Systems and an ARIA Project on Scaling AI Compute by 1000X . PhD in Computer Science (Imperial College London, 2018) MRes in Advanced Computing (Imperial College London, 2012) His research focuses on the intersection of computer systems , machine learning , and data management . Key contributions include award-winning systems like WaferLLM (wafer-scale LLM inference), Tenplex (elastic ML), and ServerlessLLM (serverless LLM serving), published at top venues (OSDI, SOSP, ICML, NeurIPS, JMLR). Recent publications demonstrate trends in GPU-based distributed systems , LLM optimization , and adaptive machine learning . His team has developed groundbreaking open-source projects including TensorLayer , TorchOpt , and ServerlessLLM . Awarded Microsoft Research StarTrack Scholar (2024) , secured ARIA grant (2024) with Imperial College & Cambridge University, and received Google Fellowship during PhD (2012-2016). As an educator, he designed Edinburgh's popular Machine Learning Systems course (150+ students). His group supervises multiple PhD students including Yao Fu (recognized as 2024 Rising Star in ML & Systems) and Leyang Xue .

Bryan S. KimView profile

Assistant Professor

• Data Storage Systems
• Computer Architecture
• Operating Systems
• +4 more

Bryan S. Kim is an Assistant Professor in the Department of Electrical Engineering and Computer Science at Syracuse University. His research focuses on computer systems, particularly data storage systems, emphasizing performance, reliability, and scalability in the context of heterogeneous hardware. He holds a Ph.D. and M.S. in Computer Science and Engineering from Seoul National University and a B.S. in Electrical Engineering and Computer Science from UC Berkeley. Prior to academia, he worked as a postdoctoral researcher at Seoul National University and as a manager at SK Telecom. Key research interests include SSD reliability, storage system design, and overcoming hardware limitations through innovative architectures. Notable recent work includes projects on capacity-variant storage systems, CXL-enabled SSDs, and RAID adaptations for heterogeneous SSDs. He has been awarded two NSF grants: the DESC proposal (CHIPLETS360) in 2025 and a CAREER award for bridging memory/storage gaps in 2025. Education: Ph.D. in Computer Science and Engineering, Seoul National University M.S. in Computer Science and Engineering, Seoul National University B.S. in Electrical Engineering and Computer Science, UC Berkeley Recent Awards: NSF DESC Proposal Award (2025) NSF CAREER Proposal Award (2025) Teaching: CSE486: Design of Operating Systems CIS341: Computer Organization & Programming Systems CIS700: Storage Systems for Big Data His students include Shao-Peng Yang, Xiangqun Zhang, and Omkar Desai. He advises on projects related to storage systems, and his work has been published in top-tier conferences like FAST, ATC, EuroSys, and OSDI.

David AndrewsView profile

Professor

• Embedded Systems
• Computer Architecture
• Reconfigurable Computing
• +5 more

David Andrews is a Professor in the Department of Computer Science and Computer Engineering at the University of Arkansas College of Engineering. He holds the Mullins Endowed Chair of Computer Engineering and directs research through the Computer Systems Design Laboratory (CSDL). His work bridges hardware and software systems with a focus on practical implementation. His educational background includes: Ph.D. in Computer Engineering from Syracuse University Computer Engineer Degree from Syracuse University M.S.E.E. from University of Missouri-Columbia B.S.E.E. from University of Missouri-Columbia Andrews' research centers on embedded systems architectures from a holistic systems perspective, examining interactions between programming languages, runtime systems, and hardware components. His work spans reconfigurable computing, FPGA-based acceleration, and hybrid CPU/FPGA systems. A key contribution is the HybridThreads (hthreads) platform, which abstracts hardware/software boundaries to enable thread-based programming for heterogeneous systems. Recent publications demonstrate his focus on accelerating machine learning workloads on FPGAs, particularly transformer models and attention mechanisms, while addressing resource scheduling and real-time constraints. His publication trends reveal a consistent evolution from foundational work in parallel and distributed embedded systems toward specialized hardware acceleration for modern AI workloads. The research increasingly focuses on memory-centric architectures, computational overlays, and practical implementations for real-time applications across diverse domains including cultural heritage documentation and cybersecurity. As director of the Computer Systems Design Laboratory, Andrews leads interdisciplinary research in real-time embedded systems, reconfigurable computing, multiprocessor systems on chip, and hardware/software co-design. The lab integrates knowledge into undergraduate and graduate curricula covering digital design, computer organization, embedded systems, and systems modeling. CSDL supports a collaborative environment with undergraduate, master's, and PhD students working alongside visiting researchers from global institutions.

Anuj PathaniaView profile

Assistant Professor

• Low Power Design
• Sustainable Systems
• Electronic Design Automation
• +4 more

Anuj Pathania serves as an Assistant Professor in the Parallel Computing Systems (PCS) group within the Informatics Institute at the University of Amsterdam's Faculty of Science. His research pioneers sustainable computing systems operating under severe power, thermal, and reliability constraints, with significant contributions to energy-efficient hardware design and embedded systems. Education: PhD in Computer Science (2018), Karlsruhe Institute of Technology MSc in Computer Science (2012), National University of Singapore B.Tech in Computer Science (2009), Maharaja Agrasen Institute of Technology Pathania's research centers on low-power design and sustainable systems for constrained environments, with particular expertise in thermal management of 3D-stacked architectures and energy-efficient machine learning inference . His work bridges electronic design automation with real-world reliability challenges, developing novel power budgeting techniques like T-TSP that incorporate transient temperature effects ignored by conventional methods. Current projects include EU-funded initiatives on energy labeling for digital services, addressing ecological impacts through technological, behavioral, and legal frameworks. His publication trajectory reveals a strategic evolution toward zero-waste computing , with recent work (2023-2025) focusing on hardware-software co-design for edge AI, energy modeling across computing continua, and parameter-efficient neural adaptation. Key themes include thermal-aware scheduling for S-NUCA many-cores, cooperative processor utilization in heterogeneous systems, and sustainability metrics for digital services. Scientific Recognition: Best Paper Award Nomination at IEEE Computer Society Annual Symposium on VLSI 2023 for 3D-TTP power budgeting technique Pathania actively mentors 4 PhD students (Ehsan Aghapour, Saeedeh Baneshi, Sudam Wasala, Yixian Shen) and has successfully supervised 5 Master's theses (including Cum Laude defenses by Joris op ten Berg and Jurre Wolff). His research is supported by major grants including Energy Labels for Ecologically Sustainable Digital Services (2023-2024) and Towards Zero-Waste Computing (2021-2025), developing simulation frameworks like HotSniper and CoMeT for thermal analysis. The PCS group maintains strong industry collaborations with ARM and NVIDIA, particularly through tools like ARM-CO-UP for heterogeneous processor utilization.

Joe DeviettiView profile

Associate Professor

• Computer Architecture
• Parallel Programming
• Concurrency
• +4 more

Joseph Devietti is an Associate Professor in the Department of Computer & Information Science at the University of Pennsylvania. His research focuses on improving programmability and performance of multiprocessor systems through architectural and programming model innovations. He actively advises PhD students and has supervised numerous graduates now employed at leading tech companies and academic institutions. Education: PhD (2012), MS (2009) in Computer Science and Engineering from University of Washington; BSE (2006) in Computer Science and BA (2006) in English from University of Pennsylvania. Employment: Associate Professor (2020–present), Assistant Professor (2013–2020) at University of Pennsylvania; Principal Scientist & Co-founder at Cloudseal, Inc. (2018–2020). Devietti’s research spans computer architecture, parallel programming, and deterministic execution. Key areas include cache/memory optimization (prefetching, false sharing repair), GPU programming models (race detection, block-size independence), and hardware-software co-design for concurrency safety. His recent work addresses dynamic runtime prefetch tuning (RPG 2 ), online code layout optimization (OCOLOS), and intelligent BTB prefetching (Twig) for data center applications. His publications from 2024–2017 reveal trends in instruction/cache optimization (2024–2020), GPU determinism (2018–2017), and race detection (2018–2016). Awards include the 2024 Penn Engineering Ford Motor Company Award, Radhia Cousot Best Paper (2018), and IEEE Micro Top Picks recognition (2023, 2009, 2008). Scientific Awards : 2024 Penn Engineering Ford Motor Company Award Radhia Cousot Young Researcher Best Paper Award (SAS 2018) IEEE Micro Top Picks (2023, 2009, 2008) Intel Early Career Faculty Honor Program (2013) Intel Ph.D. Fellowship (2011) Advising : Supervised 15+ PhD/Master’s students with placements at Google, Microsoft, Amazon, NYU, and the United States Naval Academy. Collaborations : Works with industry leaders (NVIDIA, Facebook) and academic institutions (University of Washington, Penn).

• Compiler Optimization for High Performance Computing
• Optimization of Sparse/Dense Matrix/Tensor Computations
• Scalable Machine Learning
• +1 more

P. (Saday) Sadayappan is a Professor in the School of Computing at the University of Utah. He serves as a lead researcher in high-performance computing, with a focus on compiler optimization and algorithm-architecture co-design. His current projects include NIH SBIR Phase 2 funding for large-scale image analysis and NSF grants for tensor applications and cyber-infrastructure for AI. Research Interests : Compiler Optimization for High Performance Computing Optimization of Sparse/Dense Matrix/Tensor Computations Scalable Machine Learning Algorithm-Architecture Co-Design Optimization Research Trends in Publications : His work emphasizes optimizing computational workflows for emerging hardware architectures, with a focus on accelerating machine learning and scientific computing through compiler-level innovations. Recent trends include co-design for CNNs, sparse matrix optimizations, and distributed algorithms. Scientific Awards : ACM SIGPLAN Most Influential PLDI Paper Award (2018) Grants & Projects : NSF (2022–2027): Comprehensive Framework for Tensor Applications NSF AI Institute ICICLE (2021–2026): Cyber-infrastructure for environmental AI NIH SBIR (2023–2025): Next-gen machine learning for image analysis Labs & Teams : Collaborates with institutions like Ohio State University and RNET Technologies on projects involving parallel computing, sparse algorithms, and compiler design.

Alexandra FedorovaView profile

Professor

• Systems Software
• Memory and Storage Management
• Accelerator-Centric Computing
• +4 more

Dr. Alexandra Fedorova is a Professor in the Department of Electrical and Computer Engineering at the University of British Columbia (UBC), with an Associate Member role in the Computer Science department. She leads the Systopia systems research group, focusing on system software design, memory/storage management, and accelerator-centric computing. Her work emphasizes performance optimization, energy efficiency, and hardware-software co-design. She holds a PhD from Harvard University (2006), where she researched operating system scheduling under Margo Seltzer. Prior to UBC, she was an Associate Professor at Simon Fraser University (2006–2015). Fedorova is a recipient of the Alfred P. Sloan Research Fellowship and the Anita Borg Early Career Award. She consults for MongoDB's storage engine team and collaborates with industry on storage and performance challenges. Her research spans tools like Non-sequitur for program trace visualization, studies on storage-class memory (e.g., Optane), and frameworks for GPU acceleration. Recent efforts include Sunstone (spatial accelerator scheduling) and ExtMem (application-aware memory management). Her work bridges low-level systems with high-performance computing needs. Key contributions include optimizing NUMA systems, improving storage engine performance, and exploring processing-in-memory architectures. Fedorova’s projects often involve open-source collaboration, reflected in her GitHub repositories such as vividperf and perf-logging , which support performance analysis tools.

• Computer Architecture
• Reconfigurable Computing
• Network-on-Chip (NoC)
• +7 more

Ioannis Sourdis is a Full Professor at the Department of Computer Engineering, Chalmers University of Technology, Sweden. His research focuses on computer architecture, reconfigurable computing, network-on-chip (NoC) design, memory systems, and fault-tolerant embedded systems, with applications in biomedical informatics and hardware security. Current projects include EUMMSS (Efficient Uncore Mechanisms for Multicore Space Systems, funded by the Swedish National Space Board) and eProcessor (European Processor Ecosystem, funded by the European Commission). Past initiatives include the DeSyRe project (on-demand system reliability), ECOSCALE (exascale reconfigurable computing), and SHARCS (secure hardware-software architectures). His work spans NoC router design (e.g., FastTrackNoC, DDRNoC), memory compression (MemSZ, L2C), and biomedical security applications (heartbeat-based protocols). He has published extensively in venues like DATE, ICS, PACT, and IEEE Transactions on Networking. Key research areas: Chiplet-based systems , hybrid memory architectures , FPGA acceleration , and real-time stream aggregation .

Rohan TabishView profile

Assistant Professor

• Real-Time Systems
• Embedded Systems
• Multicore Processors
• +5 more

Rohan Tabish is an Assistant Professor in the Department of Computer Science at the University of Illinois at Urbana-Champaign (UIUC), specializing in real-time systems, embedded systems, and cybersecurity. His work focuses on developing predictable and secure software frameworks for multi-core and heterogeneous architectures. Education: Ph.D. in Computer Science and Engineering Master's in Computer Science and Engineering B.Sc. in Electrical Engineering with Telecommunications specialization Research Interests: Real-Time Task Scheduling Fault Tolerance in Embedded Systems Inter-Core Communication Frameworks Memory Bandwidth Management Cyber-Physical Systems Scratchpad-Centric Operating Systems Awards: Outstanding Paper & Best Paper Award (RTSS 2020) Outstanding Paper & Best Student Paper Award (RTSS 2020) Best Presentation Award (RTAS 2016) Nominated for Best Paper Award (ECRTS 2019) Teaching: CS 431: Embedded Systems (Instructor, 2015-2018) CS 424: Real-Time Systems (Instructor, 2019) CS 438: Communication Networks (TA, 2019) Labs/Teams: Active member of the Real-Time Systems Lab (RTSL) at UIUC, focusing on safety-critical embedded systems and real-time software frameworks.

Dharanidhar DangView profile

Assistant Professor

• Photonic Computing
• AI Hardware Acceleration
• Memristor-based Computing
• +3 more

Dharanidhar Dang serves as Assistant Professor in the Department of Computer Engineering at the College of AI, Cyber and Computing, The University of Texas at San Antonio (UTSA), where he advances hardware-centric artificial intelligence solutions through photonic and memristor technologies. Education Ph.D., Texas A&M University His research program bridges hardware innovation and biomedical applications, with primary focus on photonic computing architectures for real-time AI acceleration and memristor-based neuromorphic systems. He investigates critical challenges in hardware reliability (particularly degradation in memristor crossbars), energy efficiency in photonic accelerators, and co-design methodologies that optimize both algorithms and physical implementations. His biomedical work applies machine learning to macrophage biology, identifying predictive signatures for inflammatory diseases through computational immunology approaches. Analysis of his 2020-2025 publications reveals three dominant research trajectories: 1) Silicon photonic accelerators (P-ReTI, P-ReTiNA, SOFTONIC) targeting real-time and energy-efficient AI, 2) Memristor reliability frameworks addressing aging effects in deep learning hardware, and 3) Translational biomedical applications where machine learning deciphers macrophage behavior in inflammatory bowel disease and preterm infant lung conditions. This tripartite focus demonstrates exceptional versatility across hardware engineering and life sciences.

David AtienzaView profile

Professor

• Embedded Systems
• Low-Power Computing
• Edge AI
• +3 more

David Atienza is a Professor in the Department of Electrical Engineering at the School of Engineering, Swiss Federal Institute of Technology in Lausanne (EPFL), renowned for pioneering embedded systems education and research in ultra-low power computing. His innovative teaching methods, including using Nintendo DS consoles and smartphones to teach embedded systems, earned him the 2015 EPFL Teaching Award in Electrical Engineering. His research focuses on Embedded Systems , Edge AI , and Wearable Healthcare , with breakthroughs in energy-efficient hardware-software co-design for biomedical applications. Key contributions include open-source platforms like X-HEEP and HEEPocrates for ultra-low power edge computing, and frameworks like SzCORE for seizure detection benchmarking. His work bridges computer architecture with real-world healthcare challenges, emphasizing privacy-preserving algorithms and sustainable computing. Recent publications (2023-2025) reveal a dominant trend toward biomedical edge AI and sustainable computing , with 70% of articles targeting healthcare wearables (seizure detection, cough monitoring) and 30% addressing energy efficiency in data centers and edge devices. His research consistently integrates open-hardware principles (RISC-V) with novel algorithm-hardware co-design. Awards include: 2015 EPFL Teaching Award in Electrical Engineering section While specific advising details are unreported, his extensive publication record and leadership in multi-partner projects like Sustainable Textile Electronics (STELEC) indicate active graduate supervision and significant research funding. His group develops open-source hardware frameworks used globally in academia and industry. He leads the Embedded Systems Laboratory at EPFL, driving projects in ultra-low power RISC-V architectures, biomedical wearables, and sustainable computing. Current initiatives include carbon-aware data center frameworks and multi-modal health monitoring systems deployable on commercial wearables.