Alastair F. Donaldson is a Professor in the Department of Computing at Imperial College London's Faculty of Engineering, where he leads the Multicore Programming Group. He also works as a Software Engineer at Google in the Android Graphics Team. Previously, he served as Director of GraphicsFuzz, an Imperial College spinout company acquired by Google in 2018. His research spans programming languages, compilers, verification, and testing, with a particular focus on randomized and fuzz testing techniques for compilers and program analyzers. Donaldson has developed several influential testing frameworks including GraphicsFuzz, RustSmith, and GrayC, which have significantly advanced compiler testing methodologies. Analysis of his recent publications reveals a strong trend toward practical applications of compiler testing techniques across diverse domains including GPU programming, verification-aware languages, and memory models. His work increasingly incorporates continuous integration practices and focuses on addressing real-world challenges in compiler development and verification. Donaldson maintains active involvement in the programming languages research community, serving on program committees for major conferences including PLDI, POPL, ASPLOS, and SPLASH. He has contributed significantly to advancing compiler testing methodologies and has mentored numerous researchers through PLMW (Programming Languages Mentoring Workshop). He leads the Multicore Programming Group at Imperial College London, which focuses on challenges in parallel and concurrent programming. His work bridges theoretical computer science with practical software engineering challenges, particularly in the areas of compiler correctness and verification.
Todd Miller is an Affiliate Professor at the School of Freshwater Sciences and Associate Professor in Environmental Health Sciences at the Zilber College of Public Health, University of Wisconsin-Milwaukee. He holds additional roles as Research Associate at the Center for Limnology and Department of Bacteriology, University of Wisconsin-Madison, and served as a Postdoctoral Scholar in Environmental Health Engineering at Johns Hopkins School of Public Health. Education: PhD in Marine Estuarine Environmental Sciences from the University of Maryland and BS in Biological Sciences from St. Norbert College. Research focuses on microbial regulation of toxin exposure in water/wastewater systems, with emphasis on cyanobacterial harmful algal blooms (HABs), toxin dynamics, and ecosystem impacts. His work integrates field monitoring technologies (e.g., Panther Buoy) with microbial community analysis to model toxin production and degradation in aquatic environments. Publications highlight advancements in real-time HAB monitoring, toxin epidemiology in vulnerable communities, and phosphorus dynamics in eutrophic systems. Collaborative efforts include community-driven initiatives like CLEAR (Community leaders engaged in aquatic research) to enhance urban waterway understanding. Labs/Teams: Directs the Miller Laboratory, pioneering innovations in water quality monitoring systems and cyanotoxin research. Current projects address toxin mitigation strategies, climate-driven bloom shifts, and interdisciplinary solutions for public health protection.
Vittorio Fra is a Fixed-term Assistant Professor at the Interuniversity Department of Regional and Urban Studies and Planning (DIST) at Politecnico di Torino, where he conducts research in artificial intelligence, neuromorphic computing, edge computing, and robotics. He is a member of the PIC4SeR Interdepartmental Center for Service Robotics and contributes to interdisciplinary research bridging engineering, nanotechnology, and smart urban systems. His research interests center on AI and neuromorphic computing for industrial and IoT applications , with strong emphasis on brain-inspired computing, memristive devices, and nanoscale technologies. His work spans from low-level hardware characterization to high-level algorithm design, integrating machine learning, bio-inspired computing, and scientific simulation. He actively explores neuromorphic solutions for real-world edge applications such as human activity recognition, smart traffic control, and assistive technologies like Braille readers. The trend across his recent publications (2022–2025) reveals a consistent focus on deploying spiking neural networks and neuromorphic architectures on commercial edge devices, optimizing neural execution, developing benchmarking tools (e.g., NeuroBench, WiN-GUI), and validating neuromorphic solutions on practical problems like Sudoku and the knapsack problem. His work bridges theoretical AI with applied engineering, targeting sustainability and innovation in infrastructure and urban communities. Scientific Awards: No scientific awards explicitly mentioned in the text. Advising and Grants: Vittorio Fra supervises Filippo Aisa , a PhD candidate in Electrical, Electronic, and Communications Engineering. He leads a commercially funded research project titled Supporto allo sviluppo di un smart digital water distributor monitoring system (2025–2026) , serving as the Scientific Responsible. His teaching roles include PhD instruction, course collaboration, and invited membership in academic councils across engineering and planning programs. Labs and Research Teams: He is a member of the PoliTO Interdepartmental Centre for Service Robotics (PIC4SeR) , a multidisciplinary research center focused on robotics for societal applications. His collaborations span multiple institutions and projects, involving teams working on neuromorphic ecosystems (e.g., Lava-Loihi), wireless sensor networks, and brain-inspired computing frameworks.
Timo Hämäläinen is a Professor of Computer Engineering at Tampere University, leading the Unit of Computing Sciences within the Faculty of Information Technology and Communication Sciences. He is a core member of the System-on-Chip research group and the Computer Engineering Team, actively contributing to the System-on-Chip Hub initiative. His research focuses on System-on-Chip (SoC) design methodologies, FPGA-based high-level synthesis, real-time embedded systems, and open-source hardware-software co-design frameworks like RISC-V and HEVC encoding. He has pioneered work on agile SoC development processes and validation techniques for large-scale hardware systems. Key research areas include: High-level synthesis (HLS) optimization for FPGAs Real-time processor architectures and context-switching latency reduction Formal verification of IP-XACT-compliant SoC designs Resilient RISC-V MPSoC implementations Hardware-accelerated algorithms for signal processing and networking His recent publications (2023-2025) emphasize agile SoC development frameworks, hardware-software co-design for real-time systems, and validation methodologies for large-scale embedded systems. He has contributed to open-source projects like Kvazaar HEVC encoder and the Kactus2 IP-XACT toolchain. Academic advising includes students such as Santéri Mäki-Äijö (formal verification), Arto Oinonen (RISC-V tooling), and Sakari Lahti (processor modeling). His work integrates academic research with industrial collaboration through frameworks like the Fault-slip-Through quality assessment methodology.
Joanna F. Defranco is an Associate Professor of Engineering at the Engineering Division (Great Valley) of Pennsylvania State University. Her research focuses on software development, internet of things (IoT), blockchain, and artificial intelligence, with a particular emphasis on quality assurance, security, and practical implementations in engineering and healthcare. Research Interests Defranco's work addresses critical challenges in IoT security, digital twins for manufacturing, and AI-driven software quality analysis. She explores secure data sharing frameworks, blockchain applications in healthcare, and the evolution of low-code/no-code platforms. Her recent publications highlight interdisciplinary approaches to telemedicine, smart agriculture, and urban infrastructure. Publication Trends Her 2023-2025 publications show increasing focus on IoT integration with AI, secure healthcare data systems, and the societal implications of emerging technologies. Key themes include digital twin adoption in SMEs, generative AI's impact on software development, and cybersecurity resilience. Collaborations She collaborates with institutions like IEEE and researchers such as Paul Laplante, Joseph Voas, and Thrasyvoulos Speicher. Her work bridges engineering education with real-world applications in manufacturing, agriculture, and healthcare.
Hassen AZIZA is a senior Associate Professor and Head of the Memory Team (MEM) within the IM2NP research unit at Aix-Marseille University, specializing in microelectronics and emerging memory technologies. His work bridges academic research and industrial applications through collaborations with ST-Microelectronics, CEA-Leti, Thales, and international universities. He earned both his Master of Science in Electrical Engineering (MSEE) and PhD with honors from Aix-Marseille University. His educational background established the foundation for his expertise in semiconductor devices and memory systems. His research centers on Microelectronics , Emerging Memories , and Neuromorphic Computing , with specific focus on RRAM reliability, computation-in-memory architectures, and hardware security. Current projects address critical challenges in RRAM variability, fault tolerance, and energy-efficient neural network implementations using memristive crossbars. His work spans from fundamental device physics to system-level integration for IoT and biomedical applications. Analysis of his 15 most recent publications reveals dominant trends in RRAM reliability engineering (35% of articles), neuromorphic hardware implementation (30%), and sensor system development (20%). Key subfields include fault-tolerant memory design, variability-aware neural networks, and low-power IoT circuit optimization, demonstrating consistent focus on bridging device physics with practical system requirements. Best Paper Award at IEEE ETS (2021) for RRAM fault analysis CoolGames Silver Medal (2019) for high-altitude balloon project Eiffel Scholarship for PhD student (2018) Guillemin-Cauer Best Paper Award (2014) Multiple IEEE conference best paper awards (2013, 2011) SIMagine contest finalist/silver medalist (2010, 2009) He has supervised 10 PhD students (8 graduated via industry-oriented CIFRE theses), including Eiffel scholarship recipient Hussein BAZZI. His research is funded through strategic industry partnerships with ST-Microelectronics, CEA-Leti, and Thales Silicon Security, plus European initiatives like the French Tech LAB grant for the SMILE air quality monitoring startup project. Current grants focus on RRAM commercialization and neuromorphic hardware development. As leader of the Memory Team (MEM) within IM2NP's Department of Analysis and Design of Electronic Systems, he directs research on resistive memories, neuromorphic circuits, and sensor interfaces. The team maintains strong industry links through joint projects with semiconductor manufacturers and participates in international standardization efforts for emerging memory technologies.
Alastair F. Donaldson is a Professor in the Department of Computing at Imperial College London, where he leads the Multicore Programming Group. His primary affiliation is with Imperial College London's Department of Computing within the broader Faculty of Engineering structure. He serves as a Program Committee Member for major conferences including ASE, PLDI, and POPL. His research spans Programming Languages , Compilers , Verification , Testing , and Multicore Programming , with significant contributions to randomized testing techniques. He pioneered GraphicsFuzz (acquired by Google in 2018) and developed innovative approaches like grammar mutation for parser testing, metamorphic fuzzing for C++ libraries, and specialized tools for GPU API validation. His work bridges theoretical foundations with industrial impact, particularly in compiler correctness and GPU computing. Analysis of his recent publications reveals a strong trend toward fuzzing infrastructure development (40%), GPU/compiler testing (30%), and formal methods integration (30%). His research increasingly focuses on large-scale automated testing for complex systems including WebGPU, Dafny, and Rust, while maintaining rigorous theoretical grounding in concurrency models and memory semantics. Donaldson has held significant leadership roles including General Chair for PLDI 2020 and Program Chair for ECOOP. His research has been supported through conference organizational roles and industrial collaborations, notably the GraphicsFuzz spinout. He actively contributes to the PL community through mentoring initiatives like PLMW and community-building efforts such as The PLDI Song. He leads the Multicore Programming Group at Imperial College London, focusing on practical tools for compiler and GPU driver validation. The group's work combines theoretical program analysis with real-world testing frameworks, maintaining strong industry connections through projects adopted by Google and other technology companies.
Luciano Lavagno is a prominent academic in computer science and engineering, specializing in asynchronous circuit design, logic synthesis, and embedded systems. He has collaborated extensively with researchers like Alberto Sangiovanni-Vincentelli, Joaquim Cortadella, and Alex Yakovlev. Key contributions: Hazard-free asynchronous circuits, STG manipulation, FPGA synthesis frameworks Research focus: Formal verification, design methodologies, hardware-software co-design His publications from 1991–2025 demonstrate sustained innovation in asynchronous control logic, embedded system validation, and machine learning hardware acceleration. Notable works include SIS (sequential synthesis) and Petrify (asynchronous controller tool). While his 2018 DiracDeltaNet work extended into neural network optimization, his core expertise remains rooted in formal methods for circuit design.
Manolis G.H. Katevenis is a Professor at the Department of Computer Science, University of Crete, and the founder and Head of the Computer Architecture and VLSI Systems (CARV) Laboratory at the Institute of Computer Science (ICS), Foundation for Research and Technology – Hellas (FORTH) in Heraklion, Crete, Greece. He has held academic positions since 1986 and played a pivotal role in establishing the Computer Science Department at the University of Crete. His research spans computer architecture, interconnection networks, VLSI systems, and high-performance computing, with a strong focus on scalable, low-power, manycore systems and RISC-V. He has led numerous European R&D initiatives, including serving as Coordinator of the ExaNeSt project. PhD in Computer Science, University of California, Berkeley (1983) MSc in Electrical Engineering and Computer Science, University of California, Berkeley (1980) Diploma of Electrical Engineering, National Technical University of Athens (1978) Manolis Katevenis's research focuses on advancing scalable system architectures for high-performance and big data computing. His work in computer architecture includes RISC-V, exascale computing, and manycore systems. He has made foundational contributions to interprocessor communication, particularly through remote-write, remote-DMA, and remote-enqueue mechanisms, and has pioneered innovations in interconnection networks and low-latency network interfaces. His research integrates hardware and software co-design to optimize performance, energy efficiency, and scalability in large-scale computing systems. The recent publications highlight a strong trend in exascale computing, interconnection networks, and FPGA-based prototyping of manycore systems. His work emphasizes scalable, low-power architectures, with recurring themes in congestion management, fair scheduling, crossbar design, and hardware-software integration for HPC. The articles span high-impact journals such as IEEE/ACM Transactions on Networking, IEEE Micro, and Computer Networks, reflecting sustained contributions to computer architecture and networking. ACM Doctoral Dissertation Award (1984) David J. Sakrison Memorial Prize (1983) IBM PhD Fellowship (1981–1983) Greek State Fellowship (1973–1978) Stelios Pichoridis Award for Outstanding University Teaching (2015) Member of Academia Europaea (elected 2012) Award by the Secretary General of the Region of Crete (2003) IEEE Milestone recognition for the RISC Project (2015) Manolis Katevenis has supervised over 50 graduate theses and mentored many prominent Greek computer architects, including recipients of the ACM Maurice Wilkes Award. He has served as Principal Investigator or co-PI in over 30 R&D projects with a total budget exceeding 18 million euros, including major European initiatives such as ExaNeSt (which he coordinated), EuroEXA, EcoScale, SARC, ENCORE, and multiple HiPEAC Network of Excellence projects. His leadership extends to project coordination, architectural design, FPGA prototyping, and systems software development. Katevenis founded and leads the CARV Laboratory at FORTH-ICS, a major research team with 80–100 members focused on computer architecture and VLSI systems. The lab has spun off the Distributed Computing Systems (DCS) Laboratory and is central to European exascale computing efforts, including participation in the European Processor Initiative. CARV has developed large-scale prototypes such as the 768-core ExaNeSt system and the Formic FPGA platform for manycore research.
Dr. Mihai Teodor Lazarescu is an Associate Professor at the Department of Electronics and Telecommunications (DET), Politecnico di Torino , where he contributes to research and teaching activities. He is also a member of the PolitoBIOMed Lab (Biomedical Engineering Lab) and the Ambient Sensing and Processing research group. Scientific Affiliation: IEEE Member (2019-present) Editorial Roles: Guest Editor for SENSORS, ELECTRONICS, and ACM Transactions on Embedded Computing Systems His research interests focus on hardware acceleration for machine learning algorithms, particularly using FPGAs for data center and embedded applications. He works on high-level synthesis optimization flows, capacitive sensor design for indoor monitoring, and low-power embedded systems . His work intersects Internet of Things , Wireless Sensor Networks , and Machine Learning with applications in human localization, environmental monitoring, and industrial automation. Recent publications demonstrate expertise in neural network optimization , DSP resource sharing , and multi-FPGA allocation . His teaching spans Applied Electronics , Digital Electronic Design , and Embedded Systems Optimization across bachelor's and master's programs in Electronic Engineering and Computer Engineering . Patents: Noise cancellation for single-plate capacitive sensors Capacitive sensor for space change detection Projects: Scientific Manager for Horizon 2020-S2RJU project (2018)
Lucian Patcas serves as an Adjunct Assistant Professor in the Department of Computing and Software within McMaster University's Faculty of Engineering. His academic profile centers on bridging theoretical models with practical software engineering solutions for embedded and safety-critical systems development. His research encompasses Software Engineering , Model-Based Development , and Embedded Systems , with specialized expertise in requirements implementation, real-time analysis, and domain-specific tooling. Key contributions include advancing the Four-Variable Model for safety-critical systems and developing methodologies for Simulink-based embedded design documentation. His work integrates formal methods with practical engineering tools, targeting automotive and safety-critical application domains. Recent publications (2013-2018) demonstrate sustained focus on model-driven approaches for embedded software, requirements traceability, and web service composition. The publication trajectory reveals evolution from foundational web services research toward specialized embedded systems engineering, with strong emphasis on verification and validation techniques. Patcas maintains active collaborations with McMaster researchers including Mark Lawford (6 co-authored publications), Vera Pantelic, and Alan Wassyng, focusing on formal verification methods for embedded systems. While no active grants appear in VIVO records, his research demonstrates tangible impact through patent references and academic readership (29 Mendeley readers).
Seunghee Shin is an Assistant Professor at the Department of Computer Science within the School of Computing at SUNY Binghamton. He holds a PhD from North Carolina State University (2018), an MS in Computer Science from Northeastern University (focusing on computer networks), and a BS in Computer Engineering from Myongji University, South Korea. His research focuses on advancing computer architecture and systems, particularly exploring how emerging technologies influence memory systems. Notably, he received the NSF CAREER Award for research addressing faster cloud computing. With over five years of industry experience in system software development for mobile and storage systems, he bridges academic innovation with practical implementation. Currently, he is actively hiring PhD students to contribute to his research endeavors. Education: PhD, Electrical and Computer Engineering, North Carolina State University (2018) MS, Computer Science, Northeastern University BS, Computer Engineering, Myongji University Research Interests: Dr. Shin’s work centers on optimizing memory systems through novel architectures, including studies on non-volatile memory (NVM), GPU memory management, and serverless computing efficiency. His investigations into device-driven security vulnerabilities (e.g., IOMMU side-channel attacks) highlight a commitment to safeguarding modern computing systems. Key themes include: Emerging memory technologies and their integration Performance optimization in cloud/serverless environments Hardware-software co-design for latency reduction Awards: NSF CAREER Award (2024): Funds research into scalable serverless computing frameworks Advising & Grants: Dr. Shin oversees student research into cutting-edge memory systems and collaborates with industry on storage system development. While specific grant details are not listed, his NSF award underscores sustained external funding. Labs/Teams: His research group focuses on interdisciplinary projects at the intersection of architecture, systems, and security, leveraging SUNY Binghamton’s resources for experimental validation.
Prof. Dr. Alexander Carôt is a Professor of Media Informatics at Anhalt University of Applied Sciences, leading the Faculty of Computer Science and Languages as its Dean. His work bridges physics, computer science, and music, with a focus on networked music performance and low-latency audio systems. He developed the SoundJack software, enabling remote collaborative music-making, and contributed to projects like FAST-MUSIC and 5GUK trials for distributed music sessions. His research spans telemedicine applications, real-time streaming optimization, and quantum effects in telecommunications. Education: Ingenieursdiplom (2004) Doctorate in Engineering (2009) Research Interests: Prof. Carôt explores interdisciplinary fields combining technology and music. Key areas include: Real-time audio networking for live performances 5G-enabled tele-music systems Medical tele-rehabilitation using music feedback Low-latency multimedia streaming protocols Grants & Projects: Led initiatives like the FAST-MUSIC project and 5G trials, focusing on distributed music collaboration. Active in EU-funded research on telematic systems and networked audio. Labs/Teams: Directs the SoundJack development team and collaborates with industry partners on 5G infrastructure for arts and healthcare.
Chris Hawblitzel is a Senior Principal Researcher at Microsoft Research's Systems Research Group . His work spans programming languages, operating systems, formal verification, and security, with a focus on integrating systems concepts into safe language environments. Research Themes : Systems verification, security, concurrent programming, and type systems Awards : Distinguished Artifact Awards (2025, 2024), Jay Lepreau Best Paper Award (2024), Best Paper Awards (PLDI 2010, EuroSys 2006) His recent publications (2025-2022) focus on Rust verification ( Verus ), storage/distributed systems verification ( PoWER , IronFleet ), and cryptographic systems ( EverCrypt ). He contributes to foundational work in linear types, ghost state, and automated proof generation for systems code. Notable collaborations include work with Bryan Parno , Jon Howell , and Jay Lorch on verification frameworks and security modules for modern computing environments.
PD Dr. Josef Weidendorfer is a qualified private lecturer at Technische Universität München (TUM) and leads the Future Computing Group at the Leibniz Computing Centre (LRZ). He holds a dual affiliation with TUM's Department of Informatics, Chair of Computer Architecture and Parallel Systems (Prof. Schulz), and the Leibniz Rechenzentrum der Bayerischen Akademie der Wissenschaften. His work focuses on developing smooth migration strategies for future HPC systems and evaluating novel technologies to improve system-level and workload analysis tools. Weidendorfer's research interests encompass Parallel Computer Architectures, High Performance Computing, Multi-/Manycore architectures, GPGPU, Performance analysis and optimization, Cache Simulation, Virtual Machines, and dynamic code generation. He is particularly interested in strategies for improving computational efficiency across various hardware structures, including specialized accelerator hardware for HPC codes. He regularly organizes the UCHPC workshop (since 2010 with Euro-Par) about unconventional hardware for HPC computing and is co-organizer of the PSTI workshop series. His recent publications reveal a strong focus on HPC system optimization, with particular emphasis on load balancing techniques, cache partitioning, application malleability, and performance monitoring. The research trajectory shows increasing attention to practical implementation challenges in modern heterogeneous computing environments, especially regarding GPU utilization, resource partitioning under power constraints, and phase-aware system monitoring. Weidendorfer maintains the open-source tools Callgrind/KCachegrind for cache simulation and has supervised numerous student projects across bachelor's, master's, and guided research programs. He teaches courses including Virtualization Techniques, Parallel Programming Systems, and Advanced Computer Architecture, demonstrating strong commitment to both research and education in computer architecture and parallel systems. As principal investigator for multiple large-scale projects including EU Project SEANERGYS (2025-2028) and BMBF Project ScalNext (2022-2025), he leads significant research initiatives focused on future computing technologies and HPC system development.
