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Matthias BucherView profile

Professor

• Analog/RF Integrated Circuits Design
• MOSFET Compact Modeling
• Wide-band Device Characterization
• +3 more

Matthias Bucher is a Professor at the Department of Electronics and Computer Engineering, Technical University of Crete. He specializes in analog/RF integrated circuits design, MOSFET compact modeling, and device characterization. His research focuses on nanoscale CMOS, wide-band semiconductor devices, and high-voltage MOSFETs. He leads the Electronics Laboratory and teaches courses such as Electronics II and CMOS Analog IC Design. Education: Ph.D. in Electrical Engineering, Swiss Federal Institute of Technology (EPFL), 1999 M.S. in Electrical Engineering, Swiss Federal Institute of Technology, 1993 Research Interests: Prof. Bucher’s work emphasizes charge-based compact models (e.g., EKV3), RF device modeling, and noise analysis in MOSFETs/JFETs. His contributions include open-source tools for Verilog-A modeling and parameter extraction methodologies for advanced CMOS technologies. Labs/Teams: He directs the Electronics Laboratory , focusing on nanoelectronics and high-reliability circuits. His team collaborates on semiconductor device modeling for aerospace and industrial applications. Grants/Awards: While not explicitly listed, his extensive publication record and leadership in open-source projects indicate sustained recognition in semiconductor research communities.

Papadimitriou KyprianosView profile

Researcher

• Reconfigurable Systems
• Hardware Design
• Digital Systems
• +7 more

Kyprianos Papadimitriou is a Researcher at the Microprocessor and Hardware Laboratory within the School of Electrical and Computer Engineering at the Technical University of Crete . He holds a PhD in Electronic and Computer Engineering (2012) and has been involved in teaching laboratory courses such as Logic Design , Computer Architecture , and VLSI/ASIC Circuit Design . Research Areas : His work spans Reconfigurable Systems , Hardware Design , Computer Architecture , RFID Systems , and Real-Time Systems . He has developed innovative approaches in FPGA-based dynamic reconfiguration, MPSoC security, and 3D stereo vision for surveillance. Key Trends : Runtime reconfiguration for FPGAs Security frameworks for NoC-based MPSoCs Low-cost embedded vision systems Optimization of reconfiguration overhead Hardware task scheduling methodologies Genetic algorithm implementations on FPGAs Scientific Contributions : 1 USA patent (2005) Co-author of VLSI-SoC 2013 paper nominated for 1st Prize Active member of scientific committees (FPL, ReConFig) Peer reviewer for IEEE, Elsevier, and Springer journals Session chair at IEEE CNS and HPCC conferences Grants & Projects : Participated in competitive European and national programs, serving as scientific manager, coordinator, and technical coordinator. Developed spin-off company (2003-2005) to commercialize master's thesis research. Laboratory & Teaching : Affiliated with the Microprocessor and Hardware Laboratory , focusing on practical training in digital systems, processor-based systems, and VLSI design.

Eleni StaiView profile

Assistant Professor

• Optimization
• Communications Networks
• Data Analytics
• +4 more

Eleni Stai is an Assistant Professor at the School of Electrical and Computer Engineering, National Technical University of Athens (NTUA), affiliated with the Division of Communication, Electronic and Information Engineering. She holds advanced degrees in Electrical Engineering, Mathematics, and Applied Mathematical Sciences from NTUA and the National and Kapodistrian University of Athens. Her academic credentials include: Diploma in Electrical and Computer Engineering, NTUA (2009) B.Sc. in Mathematics, National and Kapodistrian University of Athens (2013) M.Sc. in Applied Mathematical Sciences, NTUA (2014) Ph.D. in Electrical Engineering, NTUA (2015) Dr. Stai's research integrates advanced optimization techniques with communications networks and energy systems. She develops stochastic and deterministic optimization frameworks for network resource allocation, data analytics on complex topologies, and smart-grid control applications. Her work bridges theoretical foundations with practical implementations in energy-harvesting networks, network slicing, and reinforcement learning for distributed systems. Analysis of her recent publications reveals dominant research thrusts in AI-driven network management (particularly O-RAN and network slicing), energy-integrated communications, and optimization of energy communities. A significant portion of her work addresses the convergence of 5G/6G networking with power systems, emphasizing real-time control and sustainability. Her scientific contributions have been recognized through prestigious awards: Chorafas Foundation Best Ph.D. Thesis award Thomaidis Foundation Best M.Sc. Thesis award Best Paper Award at ICT 2016 Best Presenter Award at IEEE ENERGYCON 2022 Dr. Stai serves on technical program committees for major international conferences and has co-authored the book "Evolutionary Dynamics of Complex Communications Networks". She teaches undergraduate courses in Queuing Systems, Computer Networks, and Social Network Analysis, reflecting her expertise in network theory and applications. Her research trajectory demonstrates continuous evolution from fundamental network optimization to AI-enhanced solutions for next-generation communication-energy systems. Her work builds upon her postdoctoral experience at EPFL (2016-2020) and ETH Zurich (2020-2023), where she developed advanced frameworks for communications networks and energy systems.

• VLSI Design
• Built-In Self-Test (BIST)
• Test Data Compression
• +7 more

Chr. Kavousianos is an Assistant Professor in the Department of Informatics at the University of Ioannina, Greece. He is actively engaged in research and teaching in the fields of VLSI design, testability, and low-power testing. He has been involved in major national and international research programs such as Heracleitus II, Pythagoras, and NSF-SRC (USA). Research Interests: His research focuses on advanced techniques in built-in self-test (BIST), test data compression, scan-based testing, fault tolerance, and embedded control architectures. He explores methods to reduce test data volume, power consumption during testing, and improve defect coverage in integrated circuits. Publication Trends: His recent publications (2004–2011) show a strong trend toward defect-aware testing, power-efficient test compression, and multicore SoC testing. He frequently collaborates with leading researchers, including Prof. Krishnendu Chakrabarty (Duke University). His work on multilevel Huffman coding and reseeding techniques has been highly influential, with one paper among the most accessed in 2004. Special Distinction for Excellent Academic Performance from TEE, 1996 Doctoral Scholarship 'In Memory of Professor Maritsa', 1999 Postdoctoral Scholarship from IKY, 2002 Advising and Grants: He has supervised multiple postdoctoral researchers, PhD candidates (e.g., Vasilis Tenentes, Emmanouil Kalligeros), and master’s students. He has led research projects such as 'Embedded Control Architectures' (Heracleitus II) and 'Design Techniques for Embedded Self-Control Circuits' (Pythagoras II). His international collaboration with Duke University included a postdoctoral research role in 2009. Labs and Teams: He leads a research group at the University of Ioannina with postdocs, PhD students, and visiting professors, including Prof. Krishnendu Chakrabarty. His team works on cutting-edge VLSI testing and design methodologies.

Brandon LuciaView profile

Professor

• Intermittent Computing
• Energy-harvesting Systems
• Concurrency
• +7 more

Brandon Lucia is a Full Professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University's College of Engineering. He leads the abstract research group focusing on the intersection of computer architecture, systems, and programming languages. His work bridges theoretical foundations with practical implementations in energy-constrained environments. Lucia's research centers on intermittent computing systems and edge computing in extreme environments. His work on energy-harvesting systems has established fundamental principles for batteryless computing, while his orbital edge computing research pioneers computational intelligence for nanosatellite constellations. These research thrusts address critical challenges in reliability, efficiency, and programmability for systems operating under severe power constraints. His publication record shows a clear evolution from foundational work on intermittent computing models to sophisticated applications in space computing and edge intelligence. Recent publications demonstrate increasing integration of dataflow architectures with energy-harvesting constraints, particularly in satellite constellations where computational resources must be managed across distributed, power-constrained platforms operating in extreme environments. NSF CAREER Award (2017) IEEE TCCA Young Computer Architect Award (2019) Sloan Foundation Fellowship (2021) ASPLOS Best Paper Awards (2018, 2020) OOPSLA Distinguished Paper and Artifact Awards (2015) Lucia actively mentors numerous PhD students including Brad Denby, Zhuo Cheng, and Emily Ruppel, many of whom contribute significantly to his research program. His abstract research group maintains strong industry connections while pursuing fundamental advances in computing systems. The group has developed multiple open-source tools including Legerdemain for program analysis and MultiCacheSim for cache coherence simulation. His laboratory work spans from theoretical foundations of intermittent computing to practical implementations in space systems. Current projects include computational nanosatellite constellations, energy-minimal dataflow architectures, and secure edge computing systems that operate reliably despite frequent power failures.

Labros BisdounisView profile

Professor

• CMOS Circuit Design
• Low-Power Electronics
• Embedded Systems
• +4 more

Labros Bisdounis is a Professor at the Department of Electrical and Computer Engineering, University of the Peloponnese, Greece. He previously held positions at the Technological Educational Institute of Western Greece, including Associate Professor, Full Professor, and Dean of the School of Technological Applications (2016–2018). He has extensive industry experience as a senior research engineer and project manager at Intracom S.A. (2000–2008), focusing on VLSI circuits and telecom applications. His research interests include CMOS circuit timing/power modeling, low-power/high-speed design, MOSFET modeling, and sensor applications. He has authored over 30 papers with 740+ citations and is an IEEE member. Education: Diploma in Electrical Engineering (1992), University of Patras Ph.D. in Electrical Engineering (1999), University of Patras Research Interests: CMOS circuit timing and power dissipation modeling Deep-submicron/nano-CMOS circuit design MOSFET device modeling Low-power embedded systems and SoC Sensor applications and organic electronics Leadership Roles: Dean of the School of Engineering, University of the Peloponnese (2023–present) Director of Training & Lifelong Learning Centre (2019–2019) Board Member, Hellenic NARIC (2016–2019) Collaborations: Active at the Hellenic Open University as a tutor in Computer Architecture and Digital Systems modules. Co-developed the AETHER framework for pervasive computing and contributed to energy-aware SoC designs for 5 GHz WLANs.

• Wireless Networks
• Mobile Networks
• Satellite Networks
• +5 more

Evangelos Papapetrou is an Associate Professor in the Department of Computer Science and Engineering at the University of Ioannina, Greece. He holds a Diploma (1998) and PhD (2003) in Electrical and Computer Engineering from Aristotle University of Thessaloniki. His research focuses on wireless and mobile networks, including mobile ad-hoc networks, opportunistic networks, satellite networks, quality of service (QoS), and network coding. He has contributed to over 50 peer-reviewed publications and actively participates in EU/nationally funded projects. Research interests include: Wireless/Mobile Network Architectures Opportunistic and Social Mobile Networks Satellite Communication Systems Network Coding Techniques Routing Protocol Design His work emphasizes practical implementations of network protocols, with recent trends focusing on ultra-reliable low-latency communication, energy-efficient broadcasting, and protocol optimizations for 5G/IoT environments. He has developed simulation tools like Adyton for opportunistic networks and contributed to privacy-preserving routing solutions. Teaching responsibilities include courses on Computer Networks I and Wireless Networks (2024/25). He maintains active IEEE/ACM memberships and serves on conference review committees.

George N. KarystinosView profile

Professor

• Communication Theory and Systems
• Wireless Communications
• Signal Processing
• +9 more

George N. Karystinos is currently a Professor and Dean of the School of Electrical and Computer Engineering at the Technical University of Crete , Greece. He joined TUC in 2005 and was promoted to full Professor in 2019. His academic journey began with a Ph.D. in Electrical Engineering from SUNY Buffalo (2003) and a Diploma in Computer Engineering and Science from the University of Patras (1997). Specialty: Communication theory, coding theory, adaptive signal processing Key research areas: Wireless communications, signal waveform design, L1-norm principal component analysis Leadership: Dean of School of ECE (2021–present) His work focuses on noncoherent detection for RFID/IoT systems and L1-norm PCA for robust signal processing. Recent publications explore power line communication and low-complexity sequence detection . Scientific Awards: 2003 IEEE Transactions on Neural Networks Outstanding Paper Award 2001 IEEE ICT Best Paper Award 2018 IEEE MOCAST Best Student Paper Award 2015 IEEE ICASSP Best Student Paper Award 2013 IEEE ISWCS Best Paper Award 2011 IEEE RFID-TA Second Best Student Paper Award He is affiliated with the Telecommunications Laboratory at TUC and has supervised award-winning research in wireless systems and signal processing.

Changhee JungView profile

Associate Professor

• Compilers
• Computer Architecture
• Performance Optimization
• +8 more

Changhee Jung is the Samuel D. Conte Associate Professor in the Department of Computer Science at Purdue University. His research focuses on compilers and computer architecture with an emphasis on performance, reliability, and security. His educational background includes a Ph.D. from Georgia Tech (2013) under the supervision of Prof. Santosh Pande. Professor Jung's research spans compilers and computer architecture with a focus on performance, reliability, and security. He has developed program analysis and microarchitecture optimization techniques for soft error resilience, concurrency bug detection, and system security such as memory safety and Linux kernel permission check. Currently, he is working on energy-efficient intermittent computation and nonvolatile memory crash consistency. He often leverages compiler-architecture codesign and repurposes existing hardware features to develop cost-effective solutions for complex computing challenges. His recent publications demonstrate a clear trajectory toward intermittent computing systems, nonvolatile memory architectures, and security mechanisms for energy-constrained environments. His work shows innovative approaches to power failure recovery, capacitor vulnerability exploitation, and EMI attack defense in intermittent systems, with significant contributions to whole-system persistence, cache design, and prefetching techniques for low-power computing. His notable scientific achievements include: NSF CAREER Award (2018) Inducted into MICRO Hall of Fame (2021) Best Paper Honorable Mention in ISCA 2025 Memorable Paper Award Finalist in NVMW 2024 Dissertation Advisor of 2023 ACM SIGBED Paul Caspi Memorial Dissertation Award winner Jongouk Choi 2017 AMD Faculty Research Award Professor Jung has successfully advised numerous graduate students, many of whom have secured prominent positions at leading technology companies including Google, Intel, and Samsung Electronics. His lab, the CompArch (Compiler and Architecture) research group, was formed in 2013 at Virginia Tech and continues at Purdue, focusing on compiler-architecture cooperation to address cross-cutting concerns involving performance, reliability, and security. The lab has received significant research funding, including an NSF CAREER Award in 2018 and an AMD Faculty Research Award in 2017.

• Wireless transmission
• Wireless relay networks
• Software-defined radio
• +7 more

Aggelos Bletsas Aggelos Bletsas is a Professor at the School of Electrical and Computer Engineering (ECE) at the Technical University of Crete (TUC). He holds a PhD from MIT and has expertise in wireless communication, backscatter radio, and IoT. His research focuses on ultra-low-cost sensor networks and ambiently-powered systems. Education PhD in Media Arts and Sciences, MIT (2005) MSc in Media Arts and Sciences, MIT (2001) 5-year Diploma in Electrical & Computer Engineering, Aristotle University of Thessaloniki (1998) Research Interests Bletsas' work spans scalable wireless networks, backscatter radio, RFID systems, and energy harvesting. He pioneers batteryless IoT devices and environmental sensing technologies. His lab develops hardware and algorithms for low-cost, long-range communication. Awards & Recognition IEEE Fellow (2023) 2012-2013 TUC Research Excellence Award Multiple Best Paper Awards (ISWCS, RFID-TA, SENSORS) IEEE ComSoc and RFID Council Distinguished Lecturer (2022-2025) Labs & Projects Bletsas leads the Telecommunications Laboratory at TUC, focusing on batteryless sensors, scatter radio, and robotic inventory systems. Key projects include 'Internet of Plants' and ambiently-powered inference networks.

Athanasios D. PanagopoulosView profile

Professor

• Communications
• Wireless Communications
• Radio Communications
• +9 more

Athanasios D. Panagopoulos is a Full Professor at the School of Electrical and Computer Engineering, National Technical University of Athens (NTUA), specializing in Satellite & Space Communications , Antennas and Propagation , and Quantum Communication . He leads the Division of Information Transmission Systems and Material Technology, with a focus on wireless systems, machine learning, and 5G/6G technologies. Born in Athens (1975), received summa cum laude Diploma and Dr. Engineering from NTUA (1997, 2002). Former roles: part-time Assistant Professor (2003-2007), head of Satellite Division at Hellenic Authority for Information Security (2005-2008). Research Trends emphasize Quantum Key Distribution (QKD) , Reconfigurable Intelligent Surfaces , and Deep Learning Applications in satellite networks. His work bridges atmospheric propagation effects with terrestrial-satellite convergence , including AI-driven excess attenuation prediction and UAV channel modeling. Scientific Awards include URSI General Assembly Young Scientist Award (2002, 2005) Best Paper Awards: IEEE RAWCON 2006, IEEE ISWCS 2015 Grants & Collaborations : Principal Investigator for EU/ESA R&D programs, with editorial roles at IEEE Transactions on Antennas and Propagation, and Elsevier Physical Communication. Member of ITU-R , ETSI Study Groups , and IEEE (Senior) .

Markos AnastasopoulosView profile

Associate Professor

• Optical Communications
• Wireless Networks
• Mobile Computing
• +3 more

Markos Anastasopoulos is Associate Professor at the National and Kapodistrian University of Athens, specializing in optical/wireless networks and mobile computing. His research focuses on 5G/6G network convergence, intent-based management, and AI-driven optimization for telecommunications. Recent publications address THz-optical integration, federated learning in transport networks, and semantic-aware radio systems. Applied work includes intelligent asset management for railways and techno-economic analyses of network deployments. Recognized with best dissertation and best paper awards, his research bridges theoretical networking with industrial applications in transportation and cloud infrastructure.

Konstantinos KantelisView profile

Assistant Professor

• Biological Nanonetworks
• Electromagnetic Nanogrids
• Hybrid Nanonetworks
• +5 more

Konstantinos Kantelis is an Assistant Professor at the Department of Informatics, Aristotle University of Thessaloniki, specializing in Biological Nanonetworks. He holds a PhD in Nanonetworks and has extensive professional experience as a Software Engineer/Manager at Piraeus Bank (2007-2023), preceded by system administration roles at Marfin-Egnatia Bank (2007-2014). Education: PhD in Nanonetworks (2018), Department of Informatics, Aristotle University of Thessaloniki MSc in Nanotechnology and Nanosciences (2012), Department of Physics, Aristotle University of Thessaloniki MSc in Computer Systems Technology (2006), Department of Informatics and Telecommunications, National University of Athens BSc in Mathematics (2003), Department of Mathematics, Aristotle University of Thessaloniki His research focuses on Biological Nanonetworks, Electromagnetic Nanogrids, and energy-efficient wireless communication protocols for IoT systems. He has contributed to projects like Maestro, IntelTriage, and AYGEIAS, developing protocols for LoRaWAN networks and WDM backbone resilience. Recent publications address spatial scheduling in LoRaWAN, earthquake-tolerant routing, and reinforcement learning-assisted protocols. His work bridges nanoscale communication theory with practical IoT implementations, emphasizing energy efficiency and reliability. As an educator, he teaches graduate courses in Communication Networks, Advanced Topics in Biological Nanonetworks, and Applied Mathematics, alongside postgraduate courses in Networks and Internet (2019-2021).

• Digital Circuit Design
• VLSI Systems
• Low-Power Electronics
• +3 more

Dr. Dimitrios Bakalis is an Assistant Professor at the Department of Physics, University of Patras, specializing in Digital Electronic Circuits and Systems. He joined the faculty in 2004 and focuses on the design and control of digital circuits, emphasizing low-power testing and built-in self-test (BIST) methodologies. His academic roles include teaching courses such as Computer Programming I, Digital Electronics, and Microcomputer Architecture at both undergraduate and postgraduate levels. Education: Diploma in Computer Engineering and Informatics (University of Patras) Master’s Degree in Computer Science and Technology (University of Patras) PhD in Computer Engineering and Informatics (University of Patras) Research Interests: His work revolves around VLSI design, arithmetic circuits, and low-power techniques. Key areas include modulo arithmetic circuits, fault-tolerant systems, and reconfigurable computing architectures. He has published over 50 papers in top-tier journals and conferences, contributing to advancements in digital circuit efficiency and reliability. Teaching: He instructs core courses in digital electronics and computer architecture, integrating cutting-edge research into his pedagogy. His MSc courses focus on FPGA-based digital system design, emphasizing practical applications. Labs/Teams: His research aligns with the Electronics & Computers sector within the Department of Physics, collaborating on projects involving arithmetic core optimization and low-power testing strategies.

Christos AntonopoulosView profile

Associate Professor

• Wireless Networks
• Network Communication Protocols
• Embedded Software
• +6 more

Dr. Christos Antonopoulos is an Associate Professor at the Department of Electrical and Computer Engineering, University of Patras. He holds a Diploma and PhD in Electrical Engineering from the University of Patras (2002, 2008) and has participated in over 16 European research projects (FP5, FP6, FP7, Horizon 2020) and 6 national projects. Research Interests: Wireless Networks Cyberphysical Systems Embedded Software Architecture Internet of Things Cross-Layer Protocols Sensor Networks Technical Expertise: His work involves network simulation, power optimization, and reconfigurable computing. He has published >100 journal/conference papers and 13 book chapters with over 1000 citations.