Find Academic Supervisors

Jelle HellingsView profile

Assistant Professor

• Resilient Systems
• High-Performance Data Management
• Database Theory
• +10 more

Jelle Hellings is an Assistant Professor in the Department of Computing and Software at McMaster University , Canada. His research focuses on high-performance large-scale data management systems with a strong theoretical and algorithmic component, including resilient systems (blockchains) , graph databases , and external-memory algorithms . He previously worked as a Postdoc Scholar at the University of California, Davis and earned his PhD from Hasselt University in Belgium. Education: Doctor of Sciences in Computer Science (2018), Hasselt University Master of Science in Computer Science and Engineering (2011), Eindhoven University of Technology His research interests include scalable resilient systems with Byzantine fault tolerance, database theory, graph query languages, constraints on graph data, and external-memory algorithms for large graph datasets. He has authored numerous high-impact publications on blockchain-based resilient systems, query optimization in graph databases, and theoretical advancements in relation algebra expressiveness. Hellings actively contributes to academic service through program committee memberships and tutorial organization, and he currently teaches courses on future resilient databases and foundational computer science topics.

Steven KeltsView profile

Lecturer

• Technology Ethics
• History of Capitalism
• American Political Thought
• +4 more

Steven Kelts is a Lecturer at Princeton University, affiliated with the School of Public and International Affairs (SPIA) and the Department of Computer Science . He leads the Integrated Ethics in CS program and has served as Director of the non-profit All Tech Is Human. Research Focus: Kelts examines ethical frameworks in technology innovation, historical political economies, and the intersection of democratic theory with corporate responsibility. His work spans Measuring ethics education in computing Evolving corporate structures for ethical action Locke's economic justice theories Machiavelli's republican ideals Madison's institutional designs Publications reveal trends in: Utilitarian logic in Agile teams Roman censorship models 17th-century English economic debates Mill's social value legislation Scientific Recognition: Recipient of Princeton's Council on Science and Technology grants for Agile Ethics program Google seed grant for corporate ethics frameworks University-wide award for GradFutures AI ethics leadership Advisory Roles: Includes ethics advisor to the Responsible A.I. Institute and institutional design mentor for political theory projects.

Kenneth PearceView profile

Professor

• Early Modern Philosophy
• Philosophy of Religion
• Metaphysics
• +3 more

Dr. Kenneth Pearce is a Professor of Philosophy and Academic Unit Head at the Department of Philosophy & Religion, James Madison University (since 2022). He previously served as Head of the Philosophy Department at Trinity College Dublin (2020–2022) and held roles including Ussher Assistant Professor in Berkeley Studies (2016–2020). His research focuses on early modern philosophy, particularly George Berkeley, and philosophy of religion, exploring metaphysical questions about divine power, free will, and religious epistemology. He has published extensively, including books like *Is There a God? A Debate* (2022) and *Language and the Structure of Berkeley's World* (2017). His work bridges historical and contemporary philosophy, addressing themes like grounding theory, divine attributes, and early modern critiques of materialism. Awards include the Sanders Prize (2016) and a Royal Institute of Philosophy Grant (2018). He teaches courses on early modern philosophy, philosophy of religion, and metaphysics, and actively advises graduate students. His media engagements include podcasts and radio discussions on religious debates and philosophical topics. Education: B.A./B.A.S., University of Pennsylvania (2007) Ph.D., University of Southern California (2014) Research Interests: Early modern philosophy (Berkeley, Locke, Arnauld) Philosophy of religion (omnipotence, divine freedom) Metaphysics (grounding, free will) Grants & Service: Directed MPhil in Philosophy programs at Trinity College Dublin Organized conferences like *Irish Philosophy in the Age of Berkeley* (2019) Editorial roles at *PhilPapers* and *The Prosblogion* blog Labs/Teams: Engages in digital humanities projects, including exhibits on Berkeley's manuscripts.

Mahesh TripunitaraView profile

Professor

• Information Security
• Authorization and Access Control
• Cryptographic Key Transport
• +7 more

Dr. Mahesh Tripunitara is a Professor in the Department of Electrical and Computer Engineering at the University of Waterloo, serving as Associate Chair for Undergraduate Studies. He holds a PhD (2005) and Master's (1995) in Computer Science from Purdue University, along with a BSc (1993) in Computer Science from Dalhousie University. His research focuses on information security, authorization mechanisms, cryptographic key management, and hardware security, with industry experience at Motorola's R&D labs and Silicon Valley. His work spans theoretical advancements like access control policy analysis and practical applications such as secure payments systems and IoT device reliability. Notable awards include the Best Student Paper at Usenix Security 2013 and Best Paper at ACM SACMAT 2013. He actively serves on program committees for major security conferences including CCS, CODASPY, and SACMAT. Recent publications highlight innovations in cellular security (SUCI-Catchers defense), role-mining optimization, and blockchain smart contract auditing. Teaching includes advanced algorithm design courses (ECE 406/606) and digital computation (BME 121). His research emphasizes balancing security rigor with usability in authorization systems and hardware protection mechanisms.

Kyojin ChooView profile

Assistant Professor

• Charge-domain circuits
• Sensor interfaces
• Energy converters
• +4 more

Kyojin Choo is a Tenure Track Assistant Professor at the Swiss Federal Institute of Technology Lausanne (EPFL) in the School of Engineering , affiliated with the Mixed-Signal Integrated Circuits Lab (MSIC-LAB). He also holds teaching roles in Microengineering and Electrical and Electronics Engineering at EPFL. B.S. and M.S. in Electrical Engineering from Seoul National University (2007, 2009) Ph.D. in Electrical Engineering from the University of Michigan (2018) His research focuses on charge-domain analog/mixed-signal circuits , low-power sensor interfaces , and compact ADCs for IoT, wearables, and millimeter-scale systems. He has pioneered charge-injection cell techniques for energy-efficient circuits in energy management, sensor front-ends, and communication. His work emphasizes reducing power consumption to nanowatt levels while enabling ultra-compact designs. His recent publications highlight advancements in compact SAR ADCs , low-power MEMS accelerometers , millimeter-scale imaging systems , and ultra-low-power timing generators . His research integrates charge-domain circuit design with sensor interface optimization , energy harvesting , and high-speed link architectures . He holds over 20 US patents and has taught courses in Microengineering and Electrical Engineering at EPFL. His group (MSIC-LAB) addresses challenges in battery-free sensor design, power-constrained system scaling, and commercialization of wearables with unconventional form factors.

Kunihiko KanekoView profile

Professor

• Theoretical Biophysics
• Complex Systems
• Chaos
• +6 more

Kunihiko Kaneko is a Professor at the Niels Bohr Institute, University of Copenhagen, with a distinguished career in theoretical biophysics and complex systems. He received his PhD and MSc in Physics from the University of Tokyo, and has held leadership roles at the Universal Biology Institute and Center for Complex Systems Biology. PhD Physics, 1984 - University of Tokyo MSc Physics, 1981 - University of Tokyo His research spans five primary areas: Universal Biology, Evolutionary Constraints, Ecosystem Dynamics, Neural Cognition, and Universal Anthropology. He has published extensively on multi-level consistency principles, dimensional reduction in biological systems, and reciprocity between robustness and plasticity across scales. Recent publications show strong focus on microbial ecosystems (2025), evolutionary game theory (2025), neural modular architectures (2024), and dimensional reduction in cellular systems (2024). His work bridges physics and biology through dynamical systems theory applied to diverse phenomena from protocells to human societies.

Peter MüllerView profile

Professor

• Formal Methods
• Program Verification
• Programming Languages
• +4 more

Prof. Peter Müller is a Full Professor at the Department of Computer Science at ETH Zurich since 2008. Previously, he held positions as Assistant Professor at ETH Zurich (2003-2008), Researcher at Microsoft Research Redmond (2007-2008), and IT project manager at Deutsche Bank. He earned his Diploma in Computer Science from Technical University of Munich (1996) and his Dr. rer. nat. from University of Hagen (2001) with a dissertation on modular verification of object-oriented programs. His research focuses on enabling correct software development through programming languages, verification methods, and tools. Key areas include formal verification for Rust and Go programs (Prusti and Gobra projects), separation logic, security protocols, and distributed systems verification. Müller's work emphasizes practical verification techniques for real-world systems, including secure router implementations and smart contract verification. Recent research trends highlight advancements in hyperproperties, modular reasoning for iterators and closures in Rust, and formal validation of verification tools. His methodologies bridge theoretical foundations with industrial applications, addressing challenges in concurrency, memory safety, and security assurance. Notable contributions include the SCION internet architecture, the Prusti verifier for Rust, and formal verification frameworks for distributed systems. His work often integrates rigorous mathematical foundations with scalable software engineering practices.

• Political Geography
• Geopolitics
• Technology and Security
• +4 more

Professor Louise Amoore holds a faculty position at Durham University's Department of Geography, where she serves as Professor of Political Geography and Deputy Head of Department. Her work explores intersections of geopolitics, technology, and security, with a focus on algorithmic governance and data-driven practices. Co-editor of Progress in Human Geography Appointed to UK ethics body on biometric technologies Recipient of RCUK Global Uncertainties leadership fellowship Her research examines how data and algorithms reshape security paradigms, democracy, and societal norms. Recent projects analyze generative AI, cloud computing, and machine learning's political implications. She has secured funding from Leverhulme Trust, ESRC, EPSRC, AHRC, and NWO. Key article trends reveal expertise in algorithmic sovereignty (2024), border governance (2024), predictive security models (2023), data reuse ethics (2022), and post-9/11 surveillance practices (2021). Her work critically interrogates machine learning's epistemological foundations (2019) and data sovereignty implications (2018). RCUK Global Uncertainties leadership fellowship (2012-2015) Leverhulme Trust funding ESRC, EPSRC, AHRC, NWO grants Current PhD supervisees include Anna Okada and Charlotte Lock. She co-developed the Algorithmic Life book (2015) and serves as editor for Progress in Human Geography , maintaining active research collaborations in Europe.

Joseph FriedmanView profile

Associate Professor

• Artificial Intelligence Hardware
• Beyond-CMOS Computing
• Neuromorphic Computing
• +6 more

Joseph S. Friedman is an Associate Professor of Electrical & Computer Engineering at the University of Texas at Dallas, leading the NeuroSpinCompute Laboratory within the Erik Jonsson School of Engineering and Computer Science. His research focuses on unconventional computing paradigms leveraging nanotechnology, including neuromorphic systems, spintronics, and memristive devices. He specializes in nanomagnet-based logic architectures, neuromorphic computing with domain walls and skyrmions, and hardware security for emerging technologies. His research explores energy-efficient computing through novel paradigms such as reversible skyrmion logic, neuromorphic networks using magnetic tunnel junctions, and stochastic Bayesian inference circuits. He has pioneered spintronic neurons demonstrating 94% accuracy in handwritten digit recognition and developed secure logic locking mechanisms using nanomagnet logic. His work integrates experimental fabrication with SPICE modeling, emphasizing scalable beyond-CMOS systems. Recent advancements include toggle SOT-MRAM architectures, quantum circuit design for neutral atom systems, and neuromorphic networks leveraging superconducting flux quanta. He advises over 20 graduate and undergraduate students, fostering innovation in AI hardware and unconventional computing. Notable projects include the NeuroSpinCompute Lab's domain wall neuromorphic networks, secure logic locking schemes, and collaborations with institutions like Sandia National Labs on neuromorphic reservoir computing. Current research trends emphasize low-energy spintronic architectures, hybrid quantum-classical systems, and neuromorphic applications in edge computing. His research is supported by NSF grants CCF-1910800 and CCF-2146439, focusing on neuromorphic and spintronic systems. He regularly contributes to conferences like IEEE Rebooting Computing and SPIE Spintronics, showcasing breakthroughs in nanomagnetic logic and neuromorphic inference.

Trevor E. CarlsonView profile

Assistant Professor

• Computer Architecture
• Hardware/Software Co-Design
• Performance Modeling
• +4 more

Trevor E. Carlson is an Assistant Professor at the School of Computing, National University of Singapore (NUS), focusing on high-efficiency microarchitectures, hardware/software co-design, and secure chip design for IoT and server applications. He earned his Ph.D. in Computer Science from Ghent University (2014) and B.Sc./M.Sc. in Electrical & Computer Engineering from Carnegie Mellon University (2002/2003). Research Interests include energy-efficient processors, secure computing platforms, neuromorphic accelerators, and fast simulation methodologies. He co-developed the Sniper Multi-Core Simulator used globally for performance/power evaluation. Scientific Awards : Best Paper Award, International Conference on Embedded Computer Systems (2016) Best Paper Award, International Symposium on Performance Analysis of Systems and Software (2013) Heidelberg Laureate Forum participation (2015) HiPEAC Technology Transfer Award for Sniper Simulator (2013) Current Research involves secure Systems-on-Chip (SOCure project), hardware security for IoT, and simulation methodologies. He leads a lab with researchers working on topics like Capstone for trustless secure memory access and LABS for laser fault injection benchmarks.

Kimia Zamiri AzarView profile

Assistant Professor

• Hardware Security
• Verification Formal Methods
• Advanced VLSI Testing
• +3 more

Kimia Zamiri Azar serves as an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Central Florida, focusing on hardware security and verification methodologies. Her research bridges theoretical formal methods with practical security implementations in semiconductor design and testing. Her educational background includes: Ph.D. in Electrical and Computer Engineering, George Mason University (2021) Postdoctoral Research, University of Florida Dr. Azar's research spans hardware security with emphasis on system-level verification, VLSI design-for-trust, and advanced IC testing. She pioneers techniques in logic locking, secure heterogeneous integration, and IC supply chain security, developing frameworks for authenticated encryption in Systems-in-Package and runtime security monitoring. Her work integrates formal verification with innovative testing methodologies to address hardware trust challenges across the semiconductor lifecycle. Analysis of her recent publications reveals two dominant trends: (1) Application of large language models (LLMs) to hardware design tasks including high-level synthesis code generation and RTL optimization, and (2) Advancement of secure heterogeneous integration techniques for System-in-Package architectures with focus on counterfeit prevention and split-test security protocols. These directions address critical gaps in hardware trustworthiness amid increasingly complex semiconductor supply chains. Her scientific contributions have earned significant recognition: Best Paper Award at ICCAD 2019 Best Paper Award at ISVLSI 2020 Best Paper Award at ICCAD 2020 Best Paper Award at IEEE DCAS 2020 Best Paper Award at HOST 2022 Best Paper Award at DATE 2023 Dr. Azar secures substantial research funding from premier agencies including NSF, SRC, DARPA, AFRL, DoD (NG), and Microsemi. Her grants support projects spanning hardware security validation frameworks, secure heterogeneous integration, and AI-augmented verification methodologies. She actively mentors students in her research group, guiding publications in top venues like IEEE D&T, IEEE TC, and DAC while fostering industry-academic collaborations. Her work directly impacts semiconductor security standards through patented innovations and open-source verification tools. As an active IEEE and ACM member, she contributes to community advancement through conference organization (HOST, DATE), journal editorial roles, and workshop leadership on hardware security standards. Her research group collaborates with semiconductor industry leaders to translate theoretical security frameworks into practical design-for-trust methodologies for next-generation integrated circuits.

Yiorgos MakrisView profile

Professor

• Hardware Security
• Trusted Systems
• Machine Learning in Semiconductor Manufacturing
• +9 more

Yiorgos Makris is a Professor in the Department of Electrical and Computer Engineering at the Erik Jonsson School of Engineering & Computer Science, The University of Texas at Dallas, since July 2011. Previously, he was a faculty member at Yale University for over a decade. He holds a Ph.D. in Computer Engineering from the University of California, San Diego, and a Diploma in Computer Engineering from the University of Patras, Greece. Education: Ph.D. in Computer Engineering, University of California, San Diego (2001) M.S. in Computer Engineering, University of California, San Diego (1997) Diploma in Computer Engineering and Informatics, University of Patras, Greece (1995) Research Interests: Hardware Security and Trustworthiness Statistical Side-Channel Fingerprinting Machine Learning in Semiconductor Manufacturing Trusted and Reliable Integrated Circuits Hardware Trojans in Wireless Cryptographic ICs On-Die Learning and Emergent Technologies His work focuses on enhancing hardware security through statistical methods, machine learning, and formal verification, with applications in analog/RF ICs, post-production calibration, and secure IC design. Key Contributions: Co-Founder and Site-PI of NSF CHEST I/UCRC (Hardware and Embedded System Security and Trust) Leader of the Safety, Security, and Healthcare Thrust at TxACE (Texas Analog Center of Excellence) Director of the Trusted and RELiable Architectures (TRELA) Lab Grants and Funding: NSF, NIH, SRC, ARO, AFRL, AFWERX, DARPA, DOE, and industry partnerships with Boeing, Northrop Grumman, IBM, Intel, Qualcomm, etc. Recent grants include projects on DNA storage security, analog neural networks, and malicious hardware detection. Awards and Recognition: IEEE Fellow (2025) Best Paper Awards at DATE'13, VTS'15, DCAS'22 Best Hardware Demonstration Awards at HOST'16 and HOST'18 Erik Jonsson School Faculty Research Award (2020) Labs and Teams: TRELA Lab (Focus: Secure Hardware Design, Trusted Architectures) CHEST I/UCRC (Industry-University Collaboration)

• Computer Architecture
• Hardware Acceleration
• Approximate Computing
• +3 more

Akash Kumar is a Professor at Ruhr University Bochum, Germany, with affiliations to multiple institutions including TU Dresden and National University of Singapore. His research focuses on computer architecture, hardware acceleration, and approximate computing, with a strong emphasis on FPGA-based systems and neural network optimization. He has contributed extensively to embedded systems, mixed-criticality systems, and security in emerging technologies like reconfigurable nanodevices. His work spans cross-layer approximation methodologies, graph neural networks, and energy-efficient processing for edge AI. Collaborations with industry and academia highlight his leadership in VLSI design and secure hardware implementations. Notable contributions include frameworks for bounding time in mixed-criticality systems and resilient logic locking techniques. Research interests include hardware-software co-design, real-time systems, and efficient neural network architectures. His publications in top-tier conferences (DAC, DATE, FCCM) and journals (IEEE Trans. CAD, ACM TECS) underscore his impact in the field.

Rajendran JeyavijayanView profile

Associate Professor

• Hardware Security
• Computer Security
• Hardware Fuzzing
• +4 more

Jeyavijayan 'JV' Rajendran is an Associate Professor in the Department of Electrical and Computer Engineering at Texas A&M University, part of the College of Engineering. He is an ASCEND Fellow and leads the Secure and Trustworthy Hardware (SETH) Lab. His research focuses on hardware security, computer security, and novel applications of AI in secure hardware design. Education: PhD in Electrical Engineering (NYU 2015), MS in Computer Engineering (NYU Tandon 2010), BE in Electronics and Communication Engineering (Anna University 2008). Research Interests: Hardware Security, Computer Security, Logic Locking, Hardware IP Protection, and Reinforcement Learning for Security. He explores AI-driven approaches to detect vulnerabilities, protect intellectual property, and enhance secure hardware design through fuzzing, obfuscation, and formal verification. Notable Awards: 2022 Office of Naval Research Young Investigator Award, 2021 IEEE CEDA Ernest Kuh Early Career Award, 2017 NSF CAREER Award. Lab and Teams: The SETH Lab focuses on trustworthy hardware design, developing techniques to secure integrated circuits against reverse engineering and IP theft. Current projects include LLM-based hardware code generation, formal approaches for hardware fuzzing, and AI-driven vulnerability detection.

• Secure Computing
• Hardware/Software Co-Design
• Machine Learning
• +6 more

Farinaz Koushanfar is a Professor in the Department of Electrical and Computer Engineering at the Jacobs School of Engineering, University of California San Diego (UCSD) . She holds the Siavouche Nemat-Nasser Endowed Chair and serves as Founding Co-Director of the Center for Machine-Intelligence, Computing and Security . Her affiliations include NSF Trust-Hub (Co-PI) and NSF TILOS AI Institute . She also serves on the Editorial Board of The Proceedings of the IEEE . Research Focus: Prof. Koushanfar leads research in secure and efficient computing , including robust/safe AI , hardware/system security , AI-based optimization , and cryptographically secure privacy-preserving computing . Her work pioneered logic obfuscation/locking for chip security, automated co-design of AI systems , watermarking/tracing of deep learning models , and physical proofs of provenance . She explores co-design with cryptographic constructs for privacy preservation and manages nonlinearities in ciphertext domains. Article Trends: Recent publications show expertise in neural watermarking (deepfakes, media authentication), zero-knowledge proof frameworks , Trojan attack defenses in ML models, secure federated learning , and hardware acceleration of cryptographic protocols . Her work combines machine learning , cryptography , and physical design security across 2022-2025 publications. Scientific Awards: Fellow of ACM Fellow of IEEE Fellow of National Academy of Inventors (NAI) Fellow of Kavli Foundation of NAS Inducted to NAI 2024 Fellows Advising & Leadership: She has advised multiple PhD students who became faculty at top universities (e.g., Stanford, Purdue). She chairs conferences like ACM WiSec 2024 and co-led the NSF SaTC decadal review. Her lab ( ACES Lab ) produces award-winning graduates like Bita Rouhani (DAC Under-40 Innovators) and Shehzeen Hussain (UCSD Best Dissertation Award).